A differential signal amplification circuit

Abstract

The application provides a differential signal amplification circuit, which comprises a differential amplifier and a common-mode voltage module. The common-mode voltage module comprises a common-mode voltage detection circuit and a bias circuit, and the common-mode voltage detection circuit and the bias circuit are connected. The differential amplifier has a first signal input end, a second signal input end, a first signal output end and a second signal output end, the first signal input end and the second signal input end are connected with the common-mode voltage detection circuit, and the bias circuit is connected with the differential amplifier. By connecting the differential amplifier with the common-mode voltage module, and by comprising the common-mode voltage detection circuit and the bias circuit, the common-mode voltage range of the input high-speed signal is improved by automatically adjusting the DC working range of the differential amplifier through the common-mode voltage detection of the input signal, wide-range common-mode voltage input is realized, and the cost is low and easy to realize.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a differential signal amplifier circuit. Background Technology

[0002] In high-speed interface communication applications, differential mode is generally used for high-speed data transmission to improve noise immunity. The principle is based on the voltage difference between the two differential ports of the signal to be transmitted. To obtain this difference, a differential amplifier is placed at the receiving end to subtract the differential signals. The DC operating point of this differential amplifier is determined by the common-mode voltage of the differential signals, and the common-mode voltage at the receiving end is the difference between the average value of the differential signals and the ground plane at the receiving end.

[0003] When a high-speed signal is transmitted from the transmitter to the receiver, the ground plane potentials at the transmitter and receiver will deviate due to differences in the environments at both ends. This deviation will be directly superimposed on the common-mode voltage at the receiver. Simultaneously, external noise during transmission through the medium will also be superimposed on this common-mode voltage, causing the common-mode voltage at the receiver to deviate from the voltage value at the transmitter. Furthermore, both the ground plane potential difference and the noise in the transmission medium are unpredictable. To correctly receive signals, the receiver needs a relatively wide tolerance range for the common-mode voltage of the input signal. Summary of the Invention

[0004] The purpose of this invention is to provide a differential signal amplifier circuit that can achieve a wide range of common-mode voltage input, and has a simple structure that is easy to implement.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a differential signal amplification circuit, including a differential amplifier and a common-mode voltage module. The common-mode voltage module includes a common-mode voltage detection circuit and a bias circuit, the common-mode voltage detection circuit and the bias circuit being connected; the differential amplifier has a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal, the first signal input terminal and the second signal input terminal being both connected to the common-mode voltage detection circuit, and the bias circuit being connected to the differential amplifier.

[0006] The beneficial effects of this invention are as follows: by connecting a differential amplifier to a common-mode voltage module, and the common-mode voltage module including a common-mode voltage detection circuit and a bias circuit, the DC operating range of the differential amplifier is automatically adjusted by detecting the common-mode voltage of the input signal, thereby increasing the common-mode voltage range of the input high-speed signal, realizing a wide range of common-mode voltage input, improving the accuracy of the received signal, and being low in cost and easy to implement.

[0007] Optionally, the common-mode voltage detection circuit includes a first resistor array and a second resistor array. The input terminal of the first resistor array is connected to the first signal input terminal; the input terminal of the second resistor array is connected to the second signal input terminal; and the output terminals of the first and second resistor arrays are short-circuited to form a common-mode voltage terminal, which is used to output the common-mode voltage. Its advantage lies in that by connecting the input terminal of the first resistor array to the first signal input terminal, connecting the input terminal of the second resistor array to the second signal input terminal, and short-circuiting the output terminals of the first and second resistor arrays, a common-mode voltage terminal is formed.

[0008] Optionally, the common-mode voltage detection circuit further includes N amplifiers, a comparison logic unit, and an analog switch unit, where N is a positive integer. The positive input terminals of the N amplifiers are all connected to the common-mode voltage terminal, dividing the common-mode voltage terminal into N intervals. The negative input terminals of the N amplifiers are all connected to a reference voltage. The output terminals of the N amplifiers are connected to the comparison logic unit. The comparison logic unit is connected to the analog switch unit, and the comparison logic unit outputs N selection control signals to the selection terminal of the analog switch unit. The input terminals of the analog unit are respectively connected to N bias signals.

[0009] Optionally, the differential amplifier includes a tail current source transistor, an input pair transistor, a cross-coupled transistor, and a load pair transistor; the tail current transistor is connected to the input pair transistor; the input pair transistor is connected to the cross-coupled transistor and the load pair transistor.

[0010] Optionally, the tail circuit source transistor is a first PMOS transistor, the input pair transistors include a second PMOS transistor and a third PMOS transistor, the cross-coupled transistor includes a second NMOS transistor and a third NMOS transistor, and the load pair transistors include a first NMOS transistor and a fourth NMOS transistor; wherein, the gate of the tail circuit source transistor is connected to the bias circuit, and the source of the tail circuit source transistor is connected to the operating voltage; the drain of the tail circuit source transistor is connected to the source of the input pair transistors; the gates of the input pair transistors are respectively the first signal input terminal and the second signal input terminal; the drains of the input pair transistors are respectively connected to the drains of the cross-coupled transistors; the gates and drains of the load pair transistors and the gates of the cross-coupled transistors are both connected to the drains of the input pair transistors, forming the first signal output terminal and the second signal output terminal; the sources of the cross-coupled transistors and the load pair transistors are both grounded.

[0011] Optionally, the tail circuit source transistor is a first NMOS transistor, the input pair transistors include a second NMOS transistor and a third NMOS transistor, the cross-coupled transistor includes a second PMOS transistor and a third PMOS transistor, and the load pair transistors include a first PMOS transistor and a fourth PMOS transistor; wherein, the gate of the tail circuit source transistor is connected to the bias circuit, and the source of the tail circuit source transistor is grounded; the drain of the tail circuit source transistor is connected to the source of the input pair transistors; the gates of the input pair transistors are respectively the first signal input terminal and the second signal input terminal; the drains of the input pair transistors are respectively connected to the drains of the cross-coupled transistors; the gates and drains of the load pair transistors and the gates of the cross-coupled transistors are both connected to the drains of the input pair transistors, forming the first signal output terminal and the second signal output terminal; the sources of the cross-coupled transistors and the load pair transistors are both connected to the operating voltage.

[0012] Optionally, the resistance values ​​in both the first and second resistor arrays can be adjusted. This has the advantage of enabling adjustment of different common-mode voltage values. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the differential signal amplifier circuit provided in an embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram of the common-mode voltage detection circuit provided in an embodiment of the present invention;

[0015] Figure 3 Detailed diagram of the differential signal amplifier circuit provided in the embodiment of the present invention;

[0016] Figure 4 A detailed diagram of another differential signal amplifier circuit provided by the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0018] To address the problems existing in the prior art, embodiments of the present invention provide a differential signal amplifier circuit, with reference to... Figure 1 As shown, the system includes a differential amplifier and a common-mode voltage module. The common-mode voltage module includes a common-mode voltage detection circuit and a bias circuit, which are connected together. The differential amplifier has a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal. Both the first and second signal input terminals are connected to the common-mode voltage detection circuit. The first and second signal output terminals are used to output a pair of differential signals. The bias circuit is connected to the differential amplifier.

[0019] In this embodiment, by connecting a differential amplifier to a common-mode voltage module, and the common-mode voltage module including a common-mode voltage detection circuit and a bias circuit, the DC operating range of the differential amplifier is automatically adjusted by detecting the common-mode voltage of the input signal, thereby increasing the common-mode voltage range of the input high-speed signal, achieving a wide range of common-mode voltage input, and is low in cost and easy to implement.

[0020] It should be noted that, Figure 1 In this context, DIP and DIN are the differential signals input to the first signal input terminal and the second signal input terminal, and DOP and DON are the signals output to the first signal output terminal and the second signal output terminal.

[0021] Optional, combined Figure 2 As shown, the common-mode voltage detection circuit includes a first resistor array and a second resistor array. The input terminal of the first resistor array is connected to the first signal input terminal, and the input terminal of the second resistor array is connected to the second signal input terminal. The output terminals of the first and second resistor arrays are short-circuited to form a common-mode voltage terminal, which is used to output the common-mode voltage. It can be understood that if the voltage at DIP is VDIP and the voltage at DIN is VDIN, then the common-mode voltage provided by the common-mode voltage terminal is: VCM = (VDIP + VDIN) / 2.

[0022] It should be noted that the organization and configuration of the first resistor array and the second resistor array must always be consistent, and the resistance values ​​in both the first and second resistor arrays are adjustable. By connecting the input terminal of the first resistor array to the first signal input terminal, connecting the input terminal of the second resistor array to the second signal input terminal, and short-circuiting the output terminals of the first and second resistor arrays, a common-mode voltage terminal is formed, thereby enabling the adjustment of different common-mode voltage values.

[0023] Optionally, the common-mode voltage detection circuit further includes N amplifiers, a comparison logic unit, and an analog switch unit, where N is a positive integer. The positive input terminals of all N amplifiers are connected to the common-mode voltage terminal, dividing the common-mode voltage terminal into N intervals. The negative input terminals of all N amplifiers are connected to a reference voltage. The output terminals of all N amplifiers are connected to the comparison logic unit. The comparison logic unit is connected to the analog switch unit, and outputs N selection control signals to the selection terminal of the analog switch unit. The input terminals of the analog switch unit are respectively connected to the N bias signals provided by the bias circuit.

[0024] VREF is the reference voltage. The amplifier's output value is obtained based on the voltage difference between VREF and VCM. Table 1 below details the relationship between the amplifier array output and the VREF voltage range:

[0025] Table 1

[0026]

[0027]

[0028] After calculation by a comparison logic unit, the comparison structure outputs N selection control signals. Each selection control signal has only one high bit, with the others low. These selection control signals are input to the selection terminals of a group of N analog switch units, each with its input connected to one of N bias signals. Each selection control signal corresponds to one bit, and the analog switch array outputs a bias signal (VBP_GEN). It can be understood that in this embodiment, the relationship between the output VBP_GEN signal and the VREF potential is as follows: when VREF is high, VBP_GEN is low; when VREF is low, VBP_GEN is high.

[0029] Optionally, the differential amplifier includes a tail current source transistor, an input pair transistor, a cross-coupled transistor, and a load pair transistor. The tail current source transistor is connected to the input pair transistor; the input pair transistor is connected to the cross-coupled transistor and the load pair transistor.

[0030] Specifically, in combination Figure 3As shown, when the source transistor of the tail circuit is a first PMOS transistor (MP0), the input pair transistors are a second PMOS transistor and a third PMOS transistor (MP1 / MP2), the cross-coupled transistors are a second NMOS transistor and a third NMOS transistor (MN2 / MN3), and the load pair transistors are a first NMOS transistor and a fourth NMOS transistor (MN1 / MN4), the gate of MP0 is connected to the bias circuit, and the source of MP0 is connected to the operating voltage; the drain of MP0 is connected to the source of MP1 / MP2; the gates of MP1 / MP2 are respectively the first signal input terminal and the second signal input terminal; the drain of MP1 / MP2 is connected to the drain of MN2 / MN3; the gate and drain of MN1 / MN4 are connected to the drain of MP1 / MP2, and the gate of MN2 / MN3 is connected to the drain of MN1 / MN2; the sources of MN2 / MN3 and MN1 / MN4 are both grounded.

[0031] Combination Figure 4 As shown, when the source transistor of the tail circuit is a first NMOS transistor (MN0), the input pair transistors are a second NMOS transistor and a third NMOS transistor (MN1 / MN2), the cross-coupled transistors are a second PMOS transistor and a third PMOS transistor (MP2 / MP3), and the load pair transistors are a first PMOS transistor and a fourth PMOS transistor (MP1 / MP4), the gate of MN0 is connected to the bias circuit, and the source of MN0 is grounded; the drain of MN0 is connected to the source of MN1 / MN2; the gates of MN1 / MN2 are respectively the first signal input terminal and the second signal input terminal; the drains of MN1 / MN2 are respectively connected to the drains of MP2 / MP3; the gates and drains of MP1 / MP4 and the gates of MP2 / MP3 are both connected to the drains of MP1 / MP2, forming the first signal output terminal and the second signal output terminal; the sources of MP2 / MP3 and MP1 / MP4 are both connected to the operating voltage.

[0032] In this embodiment, the higher the gate DC voltage of the input differential pair, the higher the DC operating point required at its source. In order to provide the same amount of operating current, the lower the DC voltage required at the gate of the tail current source transistor, the more the DC operating range of the differential amplifier is automatically adjusted, and the direct increase of high-speed signal load is avoided.

[0033] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A differential signal amplification circuit, characterized by comprising: include: Differential amplifiers and common-mode voltage modules; The common-mode voltage module includes a common-mode voltage detection circuit and a bias circuit, and the common-mode voltage detection circuit and the bias circuit are connected. The differential amplifier has a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal. The first signal input terminal and the second signal input terminal are both connected to the common-mode voltage detection circuit. The first signal output terminal and the second signal output terminal are used to output a pair of differential signals. The bias circuit is connected to the differential amplifier; The common-mode voltage detection circuit includes a first resistor array, a second resistor array, N amplifiers, a comparison logic unit, and an analog switch unit, where N is a positive integer. The input terminal of the first resistor array is connected to the first signal input terminal; the input terminal of the second resistor array is connected to the second signal input terminal; the output terminals of the first and second resistor arrays are short-circuited to form a common-mode voltage terminal, which is used to output the common-mode voltage; the positive input terminals of the N amplifiers are all connected to the common-mode voltage terminal, dividing it into N intervals; the negative input terminals of the N amplifiers are all connected to a reference voltage; the output terminals of the N amplifiers are connected to the comparison logic unit; the comparison logic unit is connected to the analog switch unit, and outputs N selection control signals to the selection terminal of the analog switch unit; the input terminals of the analog switch unit are respectively connected to N bias signals.

2. The differential signal amplification circuit according to claim 1, characterized by The differential amplifier includes a tail circuit source transistor, an input pair of transistors, a cross-coupled transistor, and a load pair of transistors; The tail circuit source transistor is connected to the input pair transistors; The input pair is connected to the cross-coupled pair and the load pair.

3. The differential signal amplifier circuit according to claim 2, characterized in that: The tail circuit source transistor is a first PMOS transistor, the input pair includes a second PMOS transistor and a third PMOS transistor, the cross-coupled transistor includes a second NMOS transistor and a third NMOS transistor, and the load pair includes a first NMOS transistor and a fourth NMOS transistor; wherein... The gate of the tail circuit source transistor is connected to the bias circuit, and the source of the tail circuit source transistor is connected to the operating voltage. The drain of the tail circuit source transistor is connected to the source of the input pair transistors; The gates of the input transistor pair are the first signal input terminal and the second signal input terminal, respectively; The drains of the input pair transistors are respectively connected to the drains of the cross-coupled transistors; The gate and drain of the load pair transistor and the gate of the cross-coupled transistor are both connected to the drain of the input pair transistor, forming the first signal output terminal and the second signal output terminal; The sources of both the cross-coupled transistor and the load pair transistor are grounded.

4. The differential signal amplifier circuit according to claim 2, characterized in that: The tail circuit source transistor is a first NMOS transistor, the input pair includes a second NMOS transistor and a third NMOS transistor, the cross-coupled transistor includes a second PMOS transistor and a third PMOS transistor, and the load pair includes a first PMOS transistor and a fourth PMOS transistor; wherein... The gate of the tail circuit source transistor is connected to the bias circuit, and the source of the tail circuit source transistor is grounded. The drain of the tail circuit source transistor is connected to the source of the input pair transistors; The gates of the input transistor pair are the first signal input terminal and the second signal input terminal, respectively; The drains of the input pair transistors are respectively connected to the drains of the cross-coupled transistors; The gate and drain of the load pair transistor and the gate of the cross-coupled transistor are both connected to the drain of the input pair transistor, forming the first signal output terminal and the second signal output terminal; The sources of both the cross-coupled transistor and the load pair transistor are connected to the operating voltage.

5. The differential signal amplification circuit of claim 1, wherein, The resistance values ​​in both the first resistor array and the second resistor array are adjustable.

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