Resonators and their formation methods

Abstract

A resonator and its formation method are disclosed. The resonator formation method includes: providing a piezoelectric stack structure, the piezoelectric stack structure including a first region and a second region surrounding the first region, the piezoelectric stack structure having a first surface and a second surface opposite to the first surface; forming a first dielectric layer on the first surface of the piezoelectric stack structure; providing a first substrate, the top of the first substrate having a top doped region; bonding the first dielectric layer and the top of the first substrate together; forming a second dielectric layer on the second surface of the piezoelectric stack structure; etching the first dielectric layer, the piezoelectric stack structure, and the second dielectric layer in the second region to form a first opening and a second opening exposing the top doped region; and forming a first plug and a second plug in the first opening and the second opening, respectively. When the resonator is operating, the first plug is used to draw the static current from the downstream section onto the first substrate, quickly breaking down the Schottky diode and releasing the static electricity from the downstream section, which is beneficial for improving the electrical performance of the resonator.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a resonator and a method for forming the same. Background Technology

[0002] With the development of mobile communication technology, the amount of mobile data transmission has also increased rapidly. Therefore, given the limited frequency resources and the need to use as few mobile communication devices as possible, increasing the transmission power of wireless power transmitting devices such as wireless base stations, micro base stations, or repeaters has become a necessary consideration. At the same time, the requirements for the power of filters in the front-end circuits of mobile communication devices are also becoming increasingly stringent.

[0003] Currently, high-power filters in devices such as wireless base stations are mainly cavity filters, with power reaching hundreds of watts. In addition, some devices use dielectric filters, with an average power of over 5 watts. However, both types of filters are relatively large and difficult to integrate into RF front-end chips.

[0004] Currently, thin-film bulk acoustic resonators (FBARs) based on semiconductor microfabrication technology can effectively overcome the shortcomings of the two types of filters mentioned above. FBARs have high operating frequencies, high power handling capacity, high quality factor (Q value), small size, which is conducive to integration, and FBARs also have advantages such as good compatibility with silicon wafer processes and high reliability. Summary of the Invention

[0005] The problem solved by this invention is to provide a resonator and a method for forming the same, thereby improving the performance of the resonator.

[0006] To address the aforementioned problems, the present invention provides a method for forming a resonator, comprising: providing a piezoelectric stack structure, the piezoelectric stack structure including a first region and a second region surrounding the first region, the piezoelectric stack structure having a first surface and a second surface opposite to the first surface; forming a first dielectric layer on the first surface of the piezoelectric stack structure; providing a first substrate, the top of the first substrate having a top doped region; bonding the first dielectric layer and the top surface of the first substrate together; after bonding the first dielectric layer and the top surface of the first substrate together, forming a second dielectric layer on the second surface of the piezoelectric stack structure; etching the first dielectric layer, the piezoelectric stack structure, and the second dielectric layer in the second region to form a first opening and a second opening exposing the top doped region; filling the first opening and the second opening with conductive material to form a first plug and a second plug, respectively.

[0007] Accordingly, the present invention also provides a resonator comprising: a first substrate, the first substrate including a first region and a second region surrounding the first region, the top of the first substrate having a top doped region; a first dielectric layer located on the first substrate; a piezoelectric stack structure located on the first dielectric layer; a second dielectric layer located on the piezoelectric stack structure; a first plug penetrating the second dielectric layer, the piezoelectric stack structure and the first dielectric layer in the second region and in contact with the first substrate; and a second plug penetrating the second dielectric layer, the piezoelectric stack structure and the first dielectric layer in the second region and in contact with the first substrate, the second plug being spaced apart from the first plug.

[0008] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0009] In the resonator formation method provided in this embodiment of the invention, the first dielectric layer, the piezoelectric stack structure, and the second dielectric layer in the second region are etched to form a first opening and a second opening exposing the top doped region. Conductive material is filled into the first opening and the second opening to form a first plug and a second plug, respectively. The bottom ends of the first plug and the second plug are in contact with the top doped region. The material of the first plug and the second plug is metal, and the material of the top doped region is a semiconductor material doped with ions. The first plug and the top doped region, as well as the second plug and the top doped region, all constitute a Schottky diode. When the Schottky diode is working, the first plug is used to lead the static current of the downstream section to the top doped region. The static electricity of the downstream section is released by breaking down the Schottky diode, making it difficult for static electricity to be applied to the resonator. The piezoelectric stack structure of the resonator is not easily broken down by static electricity, which is beneficial to improving the electrical performance of the resonator.

[0010] In an optional embodiment, the top doped region formed on the top of the first substrate includes a well region; a first doped region and a second doped region are formed on top of the well region, spaced apart, with the dopant ions in the first doped region and the dopant ions in the second doped region having different conductivity types; in the step of forming the first opening and the second opening, the first opening exposes the first doped region, and the second opening exposes the second doped region. A PN junction is formed between the first doped region and the second doped region. In reverse application, the first doped region has a breakdown voltage over the second doped region. The first plug is used to guide the static current of the subsequent stage to the first substrate. When the static current is large, it can instantly break down the diode, quickly releasing the static electricity of the subsequent stage, making it difficult for static electricity to be applied to the resonator. The piezoelectric stack structure of the resonator is not easily broken down by electrostatic discharge, which is beneficial to improving the electrical performance of the resonator. Attached Figure Description

[0011] Figures 1 to 15This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the resonator of the present invention. Detailed Implementation

[0012] As the background technology shows, film bulk acoustic resonators (FBARs) are currently widely used. However, the performance of the resonators produced so far is not good.

[0013] Specifically, conventional thin-film bulk acoustic wave resonator technology does not have a separately designed ESD protection device, so the electrostatic withstand capability of the filter is poor. Under normal circumstances, it can only pass the HBM 1000V test, which is lower than the 2000V requirement of conventional electronic devices. In some application scenarios, the risk is very high, and new solutions are needed to improve the ESD capability of the device.

[0014] To address the aforementioned technical problem, the present invention provides a method for forming a resonator, comprising: providing a piezoelectric stack structure, the piezoelectric stack structure including a first region and a second region surrounding the first region, the piezoelectric stack structure having a first surface and a second surface opposite to the first surface; forming a first dielectric layer on the first surface of the piezoelectric stack structure; providing a first substrate, the top of the first substrate having a top doped region; bonding the first dielectric layer and the top surface of the first substrate together; after bonding the first dielectric layer and the top surface of the first substrate together, forming a second dielectric layer on the second surface of the piezoelectric stack structure; etching the first dielectric layer, the piezoelectric stack structure, and the second dielectric layer in the second region to form a first opening and a second opening exposing the top doped region; filling the first opening and the second opening with conductive material to form a first plug and a second plug, respectively.

[0015] In the resonator formation method provided in this embodiment of the invention, the first dielectric layer, the piezoelectric stack structure, and the second dielectric layer in the second region are etched to form a first opening and a second opening exposing the top doped region. Conductive material is filled into the first opening and the second opening to form a first plug and a second plug, respectively. The bottom ends of the first plug and the second plug are in contact with the top doped region. The material of the first plug and the second plug is metal, and the material of the top doped region is a semiconductor material doped with ions. The first plug and the top doped region, as well as the second plug and the top doped region, all constitute a Schottky diode. When the Schottky diode is working, the first plug is used to lead the static current of the downstream section to the top doped region. The static electricity of the downstream section is released by breaking down the Schottky diode, making it difficult for static electricity to be applied to the resonator. The piezoelectric stack structure of the resonator is not easily broken down by static electricity, which is beneficial to improving the electrical performance of the resonator.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0017] Figures 1 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the resonator of the present invention.

[0018] refer to Figure 1 and Figure 2 A piezoelectric stack structure 107 is provided, the piezoelectric stack structure 107 includes a first region I and a second region II surrounding the first region I, the piezoelectric stack structure 107 has a first surface 109 and a second surface 110 opposite to the first surface 109.

[0019] The piezoelectric stack structure 107 is used to realize the mutual conversion between electrical signals and acoustic signals, so that the resonator can filter the signals.

[0020] In this embodiment, the piezoelectric stacked structure 107 includes a first region I, in which a cavity is subsequently formed. Specifically, in this embodiment, the first region I includes the effective operating area for the subsequent resonator to implement the filtering function. The second region II is a non-operating area.

[0021] In this embodiment, in the step of forming the piezoelectric stacked structure 107, the piezoelectric stacked structure 107 includes a first electrode layer 104, a piezoelectric layer 105 located on the first electrode layer 104, and a second electrode layer 106 located on the piezoelectric layer 105.

[0022] In this embodiment, the first electrode layer 104 is used to form the bottom electrode.

[0023] The material of the first electrode layer 104 is a conductive material or a semiconductor material. The conductive material can be a metallic material with conductive properties, such as one or more of Al, Cu, Pt, Au, Ir, Os, Re, Pd, Rh, Ru, Mo, and W; the semiconductor material can be Si, Ge, SiGe, SiC, or SiGeC, etc.

[0024] In this embodiment, the process for forming the first electrode layer 104 includes physical vapor deposition (PVD).

[0025] The piezoelectric layer 105 is made of piezoelectric material. Piezoelectric material has a piezoelectric effect, which means that a voltage will appear between the two ends of a crystal material when it is subjected to pressure. By utilizing the piezoelectric effect of piezoelectric material, mechanical vibration (sound wave) and alternating current can be converted into each other, thereby realizing the conversion of sound energy and electrical energy.

[0026] The piezoelectric layer 105 can be made of piezoelectric materials with a wurtzite-type crystalline structure, such as ZnO, AlN, GaN, aluminum zirconate titanate, or lead titanate. In this embodiment, the piezoelectric layer 105 is made of AlN.

[0027] In this embodiment, the piezoelectric layer 105 can be formed by deposition processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0028] In this embodiment, the second electrode layer 106 is used to form the top electrode.

[0029] The material of the second electrode layer 106 is a conductive material or a semiconductor material. The conductive material can be a metallic material with conductive properties, such as one or more of Al, Cu, Pt, Au, Ir, Os, Re, Pd, Rh, Ru, Mo, and W; the semiconductor material can be Si, Ge, SiGe, SiC, or SiGeC, etc.

[0030] The process for forming the second electrode layer 106 includes physical vapor deposition.

[0031] The method for forming the resonator includes: providing a second substrate 200 before providing a piezoelectric stacked structure 107.

[0032] The second substrate 200 provides a process platform for forming the piezoelectric stack structure 107.

[0033] In this embodiment, the second substrate 200 can be any suitable semiconductor substrate, such as a bulk silicon substrate. It can also be at least one of the following materials: SiGe, SiGe, SiC, SiGeC, TnAs, GaAs, Inp, or other group III and group V compound semiconductors, including multilayer structures formed by these semiconductors, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeO1), and germanium on insulator (GeOI). Alternatively, it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0034] Accordingly, in the step of providing the piezoelectric stack structure 107, the piezoelectric stack structure 107 is formed on the second substrate 200.

[0035] Specifically, the surface of the first electrode layer 104 that contacts the second substrate 200 is the second surface 110. In this embodiment, the surface of the second electrode layer 106 that faces away from the first electrode layer 104 is the first surface 109.

[0036] It should be noted that the method of forming the resonator further includes: after forming the piezoelectric stack structure 107 on the second substrate 200, and before forming the first sacrificial layer on the piezoelectric stack structure 107 in the first region I, the method of forming the resonator further includes: patterning the second electrode layer 106 to expose the second electrode layer 106 from which portions of the second region II and the first region I have been removed.

[0037] When the resonator is working, the portion of the piezoelectric stack structure 107 with the three complete structures of the first electrode layer 104, the piezoelectric layer 105 and the second electrode layer 106 is used as the functional layer for effective resonance. Therefore, in this embodiment, the edge of the effective resonance region, that is, the effective working area, can be defined by graphical processing of the second electrode layer 106.

[0038] In this embodiment, a dry etching process is used to pattern the second electrode layer 106.

[0039] refer to Figure 3 and Figure 4 The method for forming the resonator further includes: forming a first sacrificial layer 111 (e.g., on the piezoelectric stacked structure 107 in the first region I) on the piezoelectric stacked structure 107. Figure 4 (As shown).

[0040] The first sacrificial layer 111 occupies space for the subsequent formation of the first cavity. In other words, the first cavity is formed at the location of the first sacrificial layer 111 by removing the first sacrificial layer 111.

[0041] Therefore, the material of the first sacrificial layer 111 is an easy-to-remove material, and the subsequent process of removing the first sacrificial layer 111 has little impact on the piezoelectric stack structure 107. In addition, the material of the first sacrificial layer 111 can ensure that the first sacrificial layer 111 has good coverage, which is beneficial to ensure that the piezoelectric stack structure 107 completely covers the first region I.

[0042] The materials of the first sacrificial layer 111 include PSG (phosphorus-doped silicon oxide), LTO (Li2TiO3, lithium titanate), BPSG (boron- and phosphorus-doped silicon oxide), Ge, photoresist, polycrystalline silicon, or amorphous carbon. In this embodiment, the material of the first sacrificial layer 111 is PSG.

[0043] Specifically, the steps for forming the first sacrificial layer 111 include:

[0044] like Figure 3 As shown, a first sacrificial material layer 112 is formed on the piezoelectric stack structure 107.

[0045] The first sacrificial material layer 112 is used to form the first sacrificial layer.

[0046] In this embodiment, the first sacrificial material layer 112 is formed using a chemical vapor deposition (CVD) process.

[0047] like Figure 4 As shown, the first sacrificial material layer 112 is graphically represented, and the first sacrificial material layer 112 located in the first region I is retained as the first sacrificial layer 111.

[0048] In this embodiment, a dry etching process, such as anisotropic dry etching process, is used to pattern the first sacrificial material layer 112.

[0049] refer to Figure 5 A first dielectric layer 108 is formed on the first surface 109 of the piezoelectric stacked structure 107 (e.g., ...). Figure 5 (As shown).

[0050] The first dielectric layer 108 and the first sacrificial layer 111 together prepare for the subsequent formation of the first cavity.

[0051] Specifically, in the step of forming the first dielectric layer 108, the first dielectric layer 108 is formed on the first sacrificial layer 111 and on the piezoelectric stack structure 107 exposed by the first sacrificial layer 111.

[0052] In this embodiment, the first dielectric layer 108 is an insulating material. Specifically, the material of the first dielectric layer 108 can be silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the first dielectric layer 108.

[0053] In this embodiment, the first dielectric layer 108 is formed on the first sacrificial layer 111 and the piezoelectric stack structure 107 exposed by the first sacrificial layer 111, which can achieve sealing of the first sacrificial layer 111.

[0054] In other embodiments, the material of the first dielectric layer may also be other organic materials with strong adhesion, such as die attach film (DAF).

[0055] In this embodiment, the process for forming the first dielectric layer 108 includes a spin coating process.

[0056] refer to Figure 6 and Figure 7A first substrate 100 is provided, the top of which has a top doped region.

[0057] In this embodiment, the first substrate 100 can be any suitable semiconductor substrate, such as a bulk silicon substrate. It can also be at least one of the following materials: SiGe, SiGe, SiC, SiGeC, TnAs, GaAs, Inp, or other group III and group V compound semiconductors, including multilayer structures formed by these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked on insulator (SSOI), silicon on insulator stacked on insulator (S-SiGeOI), silicon on insulator (SiGeO1), and germanium on insulator (GeOI). It can also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0058] The top doped region is used to prepare for the formation of a Schottky diode with the subsequently formed first and second plugs.

[0059] The top doped region 101 is intended to improve the conductivity of the first substrate 100, making it easier for the resonator to discharge static electricity.

[0060] In this embodiment, the top doped region 101 is doped with P-type ions, forming the P-type region of the resonator diode. In other embodiments, the top doped region may also be doped with N-type ions.

[0061] Specifically, the top doped region includes a well region 101. In this embodiment, the well region 101 is doped with P-type ions. Therefore, the well region 101 has the same type of doped ions as the subsequently formed second doped region, which helps to reduce the contact resistance between the well region 101 and the second doped region. In other embodiments, the well region may also be doped with N-type ions, serving as the N-type region of the resonator diode.

[0062] Specifically, P-type ions include one or more of B, Ga, and In.

[0063] In this embodiment, the well region 101 at the top of the first substrate 100 is formed using an ion implantation process. Ion implantation has the advantages of simple operation and low process cost.

[0064] like Figure 7 As shown, a first doped region 102 and a second doped region 103 are formed at the top of the well region 101, and the dopant ions in the first doped region 102 and the dopant ions in the second doped region 103 have different conductivity types.

[0065] A well region 101 is formed on top of the first substrate 100. The well region 101 is doped with P-type ions. The dopant ions in the first doped region 102 and the second doped region 103 have different conductivity types. When the resonator is working, the first doped region 102 and the second doped region 103 form a PN junction. Subsequently, a first plug connected to the first doped region 102 and a second plug connected to the second doped region 103 are formed. In reverse application, the first doped region 102 has a breakdown voltage to the second doped region 103. The first plug is used to lead the static current of the later stage to the first substrate 100. When the static current is large, it can break down the diode instantly and quickly release the static electricity of the later stage, making it difficult for static electricity to be applied to the resonator. The piezoelectric stack structure of the resonator is not easily broken down, which is beneficial to improving the electrical performance of the resonator.

[0066] In this embodiment, in the step of forming the first doped region 102 and the second doped region 103, the first doped region 102 is doped with N-type ions and the second doped region 103 is doped with P-type ions.

[0067] Specifically, the P-type ions include one or more of B, Ga, and In. The N-type ions include one or more of P, As, and Sb.

[0068] It should be noted that in the steps of forming the first doped region 102 and the second doped region 103, the spacing between the first doped region 102 and the second doped region 103 should not be too large or too small. If the spacing between the first doped region 102 and the second doped region 103 is too small, bridging will easily occur between them, leading to leakage current. This results in a lower breakdown voltage and poor electrostatic discharge withstand capability of the resonator during operation. If the spacing between the first doped region 102 and the second doped region 103 is too large, the conduction path for electrostatic discharge is longer, resulting in poor electrostatic discharge performance of the resonator. In this embodiment, the spacing between the first doped region 102 and the second doped region 103 is from 3 micrometers to 1000 micrometers.

[0069] The step of forming a first doped region 102 and a second doped region 103 spaced apart on the top of the well region 101 includes: forming a first shielding layer (not shown in the figure) covering the well region 101, the first shielding layer having a first groove (not shown in the figure) exposing a portion of the well region 101 of the second region; doping the well region 101 exposed by the first shielding layer with a first type of ion to form the first doped region 102.

[0070] In this embodiment, ion implantation is used to dope ions in the well region 101 exposed by the first shielding layer to form a first doped region 102. Ion implantation has the advantages of simple operation and low process cost.

[0071] The first masking layer serves as an etching mask for forming the first doped region 102, thereby reducing the probability of the top of the well region 101 being etched during the subsequent removal of the first masking layer.

[0072] In this embodiment, the material of the first shielding layer includes organic materials, such as BARC (bottom anti-reflective coating), ODL (organic dielectric layer), photoresist, DARC (dielectric anti-reflective coating), DUO (Deep UV Light Absorbing Oxide), or APF (Advanced Patterning Film).

[0073] In other embodiments, the first shielding layer may also be other materials that can act as a mask and are easy to remove, thereby reducing damage to the top of the trap region 101 when the first shielding layer is subsequently removed.

[0074] Specifically, the step of forming the first shielding layer includes: forming a first shielding material layer (not shown in the figure) covering the well region 101; patterning the first shielding material layer, with the remaining first shielding material layer serving as the first shielding layer, and forming the first groove in the first shielding layer.

[0075] In this embodiment, the first shielding material layer is formed by spin coating, and the surface flatness of the first shielding material layer is relatively high.

[0076] The method for forming the resonator further includes: after forming the first doped region 102, removing the first shielding layer. In this embodiment, an ashing process is used to remove the first shielding layer.

[0077] The method for forming the resonator further includes: after removing the first shielding layer, forming a second shielding layer covering the well region 101, the second shielding layer having a second groove exposing a portion of the well region in the second region; doping the well region 101 exposed by the second shielding layer with a second type of ion to form the second doped region 103.

[0078] In this embodiment, ions are doped into the well region 101 exposed by the second shielding layer using an ion implantation process to form a second doped region 103.

[0079] The method for forming the resonator further includes: after forming the second doped region 103, removing the second shielding layer. In this embodiment, an ashing process is used to remove the second shielding layer.

[0080] refer to Figure 8 The first dielectric layer 108 and the top of the first substrate 100 are bonded together.

[0081] The first dielectric layer 108 and the top of the first substrate 100 are bonded together to prepare for subsequent etching of the first dielectric layer 108 to form a first opening and a second opening that exposes the first substrate 100.

[0082] In this embodiment, the bonding is achieved by bonding, so that the first dielectric layer 108 forms Si-O covalent bonds with the well region 101, the first doped region 102 and the second doped region 103. The Si-O bond has a large bond energy, so that the first dielectric layer 108 is firmly bonded to the well region 101, the first doped region 102 and the second doped region 103.

[0083] Specifically, during the bonding process, the first dielectric layer 108 is pressed onto the well region 101, and the first dielectric layer 108 is heated to form Si-O covalent bonds between the first dielectric layer 108 and the well region 101, the first doped region 102, and the second doped region 103.

[0084] In this embodiment, in order to enable the first dielectric layer 108 to bond with the first substrate 100, it is also necessary to prevent excessive temperature from damaging the piezoelectric stack structure 107 or other film structures. In this embodiment, the bonding process temperature is 50°C to 300°C.

[0085] refer to Figure 9 The method for forming the resonator further includes: bonding the top of the first dielectric layer 108 and the first substrate 100 together, and then removing the second substrate 200.

[0086] After bonding the top of the first dielectric layer 108 and the first substrate 100 together, the second substrate 200 is removed to prepare for the formation of a second sacrificial layer on the second surface 110 of the piezoelectric stack structure 107.

[0087] In this embodiment, the step of removing the second substrate 200 includes: grinding the second substrate 200 to remove a portion of the thickness of the second substrate 200; and after grinding the second substrate 200, using a wet etching process to remove the remaining second substrate 200.

[0088] By grinding the second substrate 200, the thickness of the second substrate 200 is reduced, thereby reducing the difficulty of the subsequent wet etching process.

[0089] In this embodiment, the second substrate 200 is polished using a chemical mechanical planarization (CMP) process.

[0090] In this embodiment, the etching solution of the wet etching process includes TMAH (tetramethylammonium hydroxide) solution, etc.

[0091] It should be noted that after exposing the first electrode layer 104 of the piezoelectric stacked structure 107, the first electrode layer 104 is further patterned to remove parts of the first electrode layer 104 in the second region II and the first region I.

[0092] refer to Figure 10 The method for forming the resonator further includes: bonding the top of the first dielectric layer 108 and the first substrate 100 together, and then forming a second sacrificial layer 113 on the second surface 110 of the piezoelectric stack structure 107 in the first region I.

[0093] The second sacrificial layer 113 occupies space for the subsequent formation of the second cavity. In other words, the cavity is formed at the location of the second sacrificial layer 113 by removing the second sacrificial layer 113.

[0094] Therefore, the material of the second sacrificial layer 113 is an easy-to-remove material, and the subsequent process of removing the second sacrificial layer 113 has little impact on the piezoelectric stack structure 107. In addition, the material of the second sacrificial layer 113 can ensure that the second sacrificial layer 113 has good coverage, which is beneficial to ensure that the piezoelectric stack structure 107 completely covers the effective working area in the first region I.

[0095] The material of the second sacrificial layer 113 includes PSG (phosphorus-doped silicon oxide), LTO (Li2TiO3, lithium titanate), BPSG (boron- and phosphorus-doped silicon oxide), Ge, photoresist, polycrystalline silicon, or amorphous carbon. In this embodiment, the material of the second sacrificial layer 113 is PSG.

[0096] In this embodiment, the step of forming the second sacrificial layer 113 includes: forming a second sacrificial material layer (not shown in the figure) on the piezoelectric stack structure 107; after planarizing the second sacrificial material layer, patterning the second sacrificial material layer, and retaining the second sacrificial material layer that is effectively working in the first region I as the second sacrificial layer 113.

[0097] In this embodiment, the second sacrificial material layer is formed using a chemical vapor deposition (CVD) process.

[0098] In this embodiment, a dry etching process, such as an anisotropic dry etching process, is used to pattern the second sacrificial material layer and form the second sacrificial layer 113.

[0099] refer to Figure 11 After bonding the top of the first dielectric layer 108 and the first substrate 100 together, a second dielectric layer 114 is formed on the second surface 110 of the piezoelectric stack structure 107.

[0100] The second dielectric layer 114 and the second sacrificial layer 113 prepare for the subsequent formation of the second cavity.

[0101] Specifically, in the step of forming the second dielectric layer 114, the second dielectric layer 114 is formed on the second sacrificial layer 113 and on the piezoelectric stack structure 107 exposed by the second sacrificial layer 113.

[0102] In this embodiment, the second dielectric layer 114 is an insulating material. Specifically, the material of the second dielectric layer 114 can be silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the second dielectric layer 114.

[0103] In this embodiment, the second dielectric layer 114 is formed on the second sacrificial layer 113 and the piezoelectric stack structure 107 exposed by the second sacrificial layer 113, which can achieve sealing of the second sacrificial layer 113.

[0104] In other embodiments, the material of the second dielectric layer may also be other organic materials with strong adhesion, such as die attach film (DAF).

[0105] In this embodiment, the process for forming the second dielectric layer 114 includes a spin coating process.

[0106] refer to Figures 12 to 14 The first dielectric layer 108, the piezoelectric stack structure 107, and the second dielectric layer 114 of the second region II are etched to form a first opening 115 and a second opening 116 exposing the top doped region (e.g., Figure 13 (As shown).

[0107] The first opening 115 provides process space for the subsequent formation of the first plug, and the second opening 116 provides process space for the subsequent formation of the second plug.

[0108] Specifically, in the step of forming the first opening 115 and the second opening 116, the first opening 115 exposes the first doped region 102, and the second opening 116 exposes the second doped region 103.

[0109] A well region 101 is formed on top of the first substrate 100. A first doped region 102 and a second doped region 103, spaced apart, are formed on top of the well region 101. The dopant ions in the first doped region 102 and the second doped region 103 have different conductivity types. In the step of forming the first opening 115 and the second opening 116, the first opening 115 exposes the first doped region 102, and the second opening 116 exposes the second doped region 103. A PN junction is formed between the first doped region 102 and the second doped region 103. In reverse application, the first doped region 102 has a breakdown voltage over the second doped region 103. The first plug is used to draw the static current from the downstream section onto the first substrate 100. When the static current is large, it can instantly break down the diode, quickly releasing the static electricity from the downstream section, making it difficult for static electricity to be applied to the resonator. The piezoelectric stack structure of the resonator is not easily broken down by electrostatic discharge, which is beneficial to improving the electrical performance of the resonator.

[0110] In this embodiment, a dry etching process is used to etch the first dielectric layer 108, the piezoelectric stack structure 107, and the second dielectric layer 114 of the second region II, forming a first opening 115 exposing the well region 101 (e.g., ...). Figure 14 (as shown) and the second opening 116 (as shown) Figure 14 (As shown). Dry etching process has anisotropic etching characteristics and good control over the etching profile, which is beneficial for ensuring that the morphology of the first opening 115 and the second opening 116 meets the process requirements. Furthermore, by changing the etching gas, the first dielectric layer 108, the piezoelectric stack structure 107, and the second dielectric layer 114 can be etched in the same etching equipment, simplifying the process steps. During the formation of the first opening 115 and the second opening 116, the top of the first doped region 102 and the top of the second doped region 103 can be used as the etching stop position, which is beneficial for controlling the position of the bottom of the first opening 115 and the second opening 116.

[0111] Specifically, during the formation of the first opening 115, the first opening 115 penetrates the piezoelectric layer 105 and the second electrode 106 in the piezoelectric stack structure 107. During the formation of the second opening 116, the second opening 116 penetrates the first electrode 104 and the piezoelectric layer 105 in the piezoelectric stack structure 107.

[0112] It should be noted that the second plug formed in the second opening 116 is used for grounding, and the first plug formed in the first opening 115 is used for connecting the downstream circuit. The number of first openings 115 is greater than the number of second openings 116.

[0113] It should be noted that the method for forming the resonator further includes: after forming the second dielectric layer 114 and before forming the first opening 115 and the second opening 116, removing the first sacrificial layer 111 and the second sacrificial layer 113.

[0114] Removing the first sacrificial layer 111 and the second sacrificial layer 113 respectively forms the first cavity 119 (e.g. Figure 13 (as shown) and the second cavity 118 (as shown) Figure 13 (As shown).

[0115] By forming the first cavity 119 and the second cavity 118, the piezoelectric stack structure 107 is brought into contact with the air, causing sound waves to be reflected at the interface between the first cavity 119 and the second cavity 118 and the piezoelectric stack structure 107. This allows the resonator to vibrate normally during operation, thus enabling the resonator to function properly. Furthermore, the contact between the piezoelectric stack structure 107 and the air effectively reflects the leakage waves of the resonator back to the substrate surface from the interface between the air and the piezoelectric stack structure 107, thereby improving the conversion efficiency of electrical energy to mechanical energy, which in turn improves the quality factor (Q value).

[0116] The steps of removing the first sacrificial layer 111 and the second sacrificial layer 113 to form the first cavity 119 and the second cavity 118 include: etching the second dielectric layer 114, the second sacrificial layer 113 and the piezoelectric stack structure 107 of the first region I to form a first release hole 120 (not shown in the figure) exposing the first sacrificial layer 111; after forming the first release hole 120, removing the first sacrificial layer 111 and the second sacrificial layer 113.

[0117] The first release hole 120 is a process hole for removing the first sacrificial layer 111 and the second sacrificial layer 113.

[0118] In this embodiment, a wet etching process is used to remove the first sacrificial layer 111 and the second sacrificial layer 113. The etching solution for the wet etching process includes BOE (Buffered Oxide Etch) solution or HF solution. The BOE solution is composed of hydrofluoric acid and water, or a mixture of ammonium fluoride and water.

[0119] It should be noted that during the formation of the first release hole 120, the first release hole 120 penetrates the piezoelectric layer 105 and the second electrode 106 in the piezoelectric stack structure 107, or the first electrode 104 and the piezoelectric layer 105.

[0120] The first release hole 120 penetrates the piezoelectric layer 105 and the second electrode 106 in the piezoelectric stack structure 107, or the first electrode 104 and the piezoelectric layer 105. The first release hole 120 is located in the non-working area of ​​the first region I, so that the first release hole 120 can remove the first sacrificial layer 111 and the second sacrificial layer 113 without easily affecting the working performance of the resonator.

[0121] It should be noted that, in the step of forming the first release hole 120, the first dielectric layer 108 of the first region I is also etched to form a second release hole 122 that exposes the second sacrificial layer 113.

[0122] The second release hole 122 and the first release hole 120 are used together to remove the first sacrificial layer 111 and the second sacrificial layer 113, thereby improving the removal rate of the first sacrificial layer 111 and the second sacrificial layer 113.

[0123] It should be noted that the method for forming the resonator further includes: after forming the first release hole 120 and the second release hole 122, forming a passivation layer 121 on the second dielectric layer.

[0124] The passivation layer 121 is used to seal the second release hole 122 and the first release hole 120, thereby sealing the first cavity 119 and the second cavity 118. The passivation layer 121 also serves to protect the piezoelectric stack structure 107, thereby reducing the influence of external impurities, ionic charges and water vapor on the piezoelectric stack structure 107, and improving the performance and stability of the resonator.

[0125] The passivation layer 121 can be made of silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride oxynitride, silicon oxynitride, boron nitride, boron carbonitride, a low-k dielectric material, or polyimide. In this embodiment, the passivation layer 121 is made of silicon oxide.

[0126] In this embodiment, a deposition process, such as chemical vapor deposition, is used to form a passivation layer 121.

[0127] It should be noted that the method for forming the resonator further includes: after forming the first opening 116 and the second opening 117, before filling the first opening 116 and the second opening 117 with conductive material, forming an insulating layer 123 on the sidewalls of the first opening 116 and the second opening 117.

[0128] The insulating layer 123 is used to electrically isolate the subsequent formation of the first plug and the piezoelectric stack structure 107, and to electrically isolate the second plug from the piezoelectric stack structure 107.

[0129] In this embodiment, the material of the insulating layer 123 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0130] It should be noted that during the step of forming the insulating layer 123, the insulating layer 123 should not be too thick or too thin. If the insulating layer 123 is too thick, it will occupy too much space in the first opening 116 and the second opening 117, resulting in a smaller contact area between the first plug and the first doped region 102 subsequently formed in the first opening 116, leading to a larger contact resistance between the first plug and the first doped region 102. Similarly, the contact area between the second plug and the second doped region 103 subsequently formed in the second opening 117 will be smaller, leading to a larger contact resistance between the second plug and the second doped region 103. This results in a weak electrostatic discharge capability of the resonator and poor electrical performance of the resonator. If the insulating layer 123 is too thin, it will not effectively isolate the first plug and the piezoelectric stack structure 107, nor will it effectively isolate the second plug and the piezoelectric stack structure 107. This will lead to bridging between the first plug and the piezoelectric stack structure 107, and between the second plug and the piezoelectric stack structure 107, resulting in poor electrical performance of the resonator. In this embodiment, the thickness of the insulating layer 123 is 50 nanometers to 500 nanometers.

[0131] refer to Figure 15 Conductive material is filled into the first opening 116 and the second opening 117 to form the first plug 124 and the second plug 125, respectively.

[0132] The first plug 124 and the second plug 125 are made of metal, and the top doped region is made of an ion-doped semiconductor material. The first plug 124 and the top doped region, as well as the second plug 125 and the top doped region, all constitute a Schottky diode. When the Schottky diode is operating, the first plug is used to guide the static current from the downstream section to the top doped region. By breaking down the Schottky diode, the static electricity in the downstream section is released, making it difficult for static electricity to be applied to the resonator. The piezoelectric stacked structure of the resonator is not easily broken down by static electricity, which is beneficial to improving the electrical performance of the resonator.

[0133] Specifically, the first plug 124 is connected to the first doped region 102, and the second plug 125 is connected to the second doped region 103. A PN junction is formed between the second doped regions 103. In reverse application, the first doped region 102 has a breakdown voltage across the second doped region 103. The first plug 124 is used to draw the static current from the downstream section onto the first substrate 100. When the static current is large, it can instantly break down the diode, quickly releasing the static electricity from the downstream section, making it difficult for static electricity to be applied to the resonator. The piezoelectric stack structure of the resonator is less prone to breakdown, which is beneficial for improving the electrical performance of the resonator.

[0134] In this embodiment, the first plug 124 and the second plug 125 are made of the same material.

[0135] Specifically, the materials of the first plug 124 and the second plug 125 include one or more of Cu, Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the materials of the first plug 124 and the second plug 125 include Cu. Copper has low resistivity, which is beneficial for improving the signal delay of the later RC circuit and for reducing the resistance between the first plug 124 and the first doped region 102, as well as the resistance between the second plug 125 and the second doped region 103, thereby reducing power consumption. In other embodiments, the materials of the first plug and the second plug may also be tungsten or cobalt.

[0136] The steps of forming the first plug 124 and the second plug 125 include: forming a conductive material layer on the first opening 116, the second opening 117 and the passivation layer 121; removing the conductive material layer above the passivation layer, and the remaining conductive material layers located in the first opening 116 and the second opening 117 respectively serving as the first plug 124 and the second plug 125.

[0137] In this embodiment, the conductive material layer is formed using an electroplating (ECP) process.

[0138] Accordingly, the present invention also provides a resonator. (See reference) Figure 15 The diagram shows a structural schematic of an embodiment of the resonator of the present invention.

[0139] The resonator includes: a first substrate 100, the first substrate 100 including a first region I and a second region II surrounding the first region I, the top of the first substrate 100 having a top doped region (not shown); a first dielectric layer 108 located on the first substrate 100; a piezoelectric stack structure 107 located on the first dielectric layer 108; a second dielectric layer 114 located on the piezoelectric stack structure 107; a first plug 124 penetrating the second dielectric layer 114, the piezoelectric stack structure 107 and the first dielectric layer 108 in the second region II, and in contact with the first substrate 100; a second plug 125 penetrating the second dielectric layer 114, the piezoelectric stack structure 107 and the first dielectric layer 108 in the second region II, and in contact with the first substrate 100, the second plug 125 being spaced apart from the first plug 124.

[0140] In the resonator provided in this embodiment of the invention, the bottom ends of the first plug 124 and the second plug 125 are both in contact with the top doped region. The materials of the first plug 124 and the second plug 125 are metals, and the material of the top doped region is a semiconductor material. The first plug and the top doped region, as well as the second plug 125 and the top doped region, all constitute a Schottky diode. When the Schottky diode is working, the first plug 124 is used to lead the static current of the downstream section to the top doped region. By breaking down the Schottky diode, the static electricity of the downstream section is released, making it difficult for static electricity to be applied to the resonator. The piezoelectric stack structure 107 of the resonator is not easily broken down, which is beneficial to improving the electrical performance of the resonator.

[0141] Specifically, the top doped region includes a well region 101.

[0142] The well region 101 serves two purposes: firstly, to improve the conductivity of the first substrate 100, making it easier for the static electricity of the resonator to dissipate; and secondly, to form the P-type region of the resonator diode.

[0143] In this embodiment, the well region 101 is doped with P-type ions. Therefore, the well region 101 has the same type of doped ions as the subsequently formed second doped region, which helps to reduce the contact resistance between the well region 101 and the second doped region. In other embodiments, the well region may also be doped with N-type ions, serving as the N-type region of the resonator diode. Specifically, the P-type ions include one or more of B, Ga, and In.

[0144] The resonator further includes: a first doped region 102 located at the top of the well region 101; and a second doped region 103 located at the top of the well region 101, wherein the first doped region 102 and the second doped region 103 are spaced apart, and the dopant ions of the first doped region 102 and the dopant ions of the second doped region 103 have different conductivity types.

[0145] Correspondingly, the first plug 124 contacts the top of the first doped region 102; the second plug 125 contacts the top of the second doped region 103.

[0146] The well region 101 is doped with P-type ions. The doped ions in the first doped region 102 and the second doped region 103 have different conductivity types. When the resonator is working, the first doped region 102 and the second doped region 103 form a PN junction. The first plug 124 contacts the top of the first doped region 102, and the second plug 125 contacts the top of the second doped region 103. In reverse application, the first doped region 102 will have a breakdown voltage over the second doped region 103. The first plug 124 is used to lead the static current of the later stage to the first substrate 100. When the static current is large, it can break down the diode instantly and quickly release the static electricity of the later stage, making it difficult for static electricity to be applied to the resonator. The piezoelectric stack structure of the resonator is not easily broken down by static electricity, which is beneficial to improving the electrical performance of the resonator.

[0147] In this embodiment, in the step of forming the first doped region 102 and the second doped region 103, the first doped region 102 is doped with N-type ions and the second doped region 103 is doped with P-type ions.

[0148] Specifically, the P-type ions include one or more of B, Ga, and In. The N-type ions include one or more of P, As, and Sb.

[0149] It should be noted that in the steps of forming the first doped region 102 and the second doped region 103, the spacing between the first doped region 102 and the second doped region 103 should not be too large or too small. If the spacing between the first doped region 102 and the second doped region 103 is too small, bridging will easily occur between them, leading to leakage current. This results in a lower breakdown voltage and poor electrostatic discharge withstand capability of the resonator during operation. If the spacing between the first doped region 102 and the second doped region 103 is too large, the conduction path for electrostatic discharge is longer, resulting in poor electrostatic discharge performance of the resonator. In this embodiment, the spacing between the first doped region 102 and the second doped region 103 is from 3 micrometers to 1000 micrometers.

[0150] In this embodiment, the first plug 124 and the second plug 125 are made of the same material.

[0151] Specifically, the materials of the first plug 124 and the second plug 125 include one or more of Cu, Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the materials of the first plug 124 and the second plug 125 include Cu. Copper has low resistivity, which is beneficial for improving the signal delay of the later RC circuit and for reducing the resistance between the first plug 124 and the first doped region 102, as well as the resistance between the second plug 125 and the second doped region 103, thereby reducing power consumption. In other embodiments, the materials of the first plug and the second plug may also be tungsten or cobalt.

[0152] It should be noted that the second plug 125 is used for grounding, and the first plug 124 is used for connecting to the downstream circuit. The number of first plugs 124 is greater than the number of second plugs 125.

[0153] The resonator further includes: a first cavity 119 located between the top of the first dielectric layer 108 and the piezoelectric stack structure 107; and a second cavity 118 located between the bottom of the second dielectric layer 114 and the piezoelectric stack structure 107.

[0154] By forming the first cavity 119 and the second cavity 118, the piezoelectric stack structure 107 is brought into contact with the air, causing sound waves to be reflected at the interface between the first cavity 119 and the second cavity 118 and the piezoelectric stack structure 107. This allows the resonator to vibrate normally during operation, thus enabling the resonator to function properly. Furthermore, the contact between the piezoelectric stack structure 107 and the air effectively reflects the leakage waves of the resonator back to the substrate surface from the interface between the air and the piezoelectric stack structure 107, thereby improving the conversion efficiency of electrical energy to mechanical energy, which in turn improves the quality factor (Q value).

[0155] In this embodiment, the first dielectric layer 108 is used to electrically isolate the first plug 124 and the second plug 125. The material of the first dielectric layer 108 includes silicon oxide.

[0156] Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the first dielectric layer 108.

[0157] In this embodiment, the second dielectric layer 114 is used to electrically isolate the first plug 124 and the second plug 125. The material of the second dielectric layer 114 includes silicon oxide.

[0158] Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the second dielectric layer 114.

[0159] The resonator further includes: an insulating layer 123 located between the first plug 124 and the first dielectric layer 108, between the first plug 124 and the piezoelectric stack structure 107, between the first plug 124 and the second dielectric layer 114, between the second plug 125 and the first dielectric layer 108, between the second plug 125 and the piezoelectric stack structure 107, and between the second plug 125 and the second dielectric layer 114.

[0160] The insulating layer 123 is used to electrically isolate the first plug 124 from the piezoelectric stack structure 107 and the second plug 125 from the piezoelectric stack structure 107.

[0161] In this embodiment, the material of the insulating layer 123 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0162] It should be noted that the insulating layer 123 should not be too thick or too thin. If the insulating layer 123 is too thick, it will occupy too much space in the first opening 116 and the second opening 117, resulting in a smaller contact area between the first plug 124 and the first doped region 102, and a larger contact resistance between the first plug 124 and the first doped region 102. Consequently, the contact area between the second plug 125 formed subsequently in the second opening 117 and the second doped region 103 will be smaller, resulting in a larger contact resistance between the second plug 125 and the second doped region 103. This will weaken the electrostatic discharge capability of the resonator and lead to poor electrical performance of the resonator. If the insulating layer 123 is too thin, it will not effectively isolate the first plug 124 from the piezoelectric stack structure 107, nor will it effectively isolate the second plug 125 from the piezoelectric stack structure 107. This will lead to bridging between the first plug 124 and the piezoelectric stack structure 107, and between the second plug 125 and the piezoelectric stack structure 107, resulting in poor electrical performance of the resonator. In this embodiment, the thickness of the insulating layer 123 is between 50 nanometers and 500 nanometers.

[0163] The resonator further includes: a passivation layer 121 located on top of the second dielectric layer 114; the first plug 124 also penetrates the passivation layer 121; and the second plug 125 also penetrates the passivation layer 121.

[0164] The passivation layer 121 is used to seal the second release hole 122 and the first release hole 120, thereby sealing the first cavity 119 and the second cavity 118. The passivation layer 121 also serves to protect the piezoelectric stack structure 107, thereby reducing the influence of external impurities, ionic charges and water vapor on the piezoelectric stack structure 107, and improving the performance and stability of the resonator.

[0165] The passivation layer 121 can be made of silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride oxynitride, silicon oxynitride, boron nitride, boron carbonitride, a low-k dielectric material, or polyimide. In this embodiment, the passivation layer 121 is made of silicon oxide.

[0166] The resonator can be formed using the resonator forming method described in the foregoing embodiments, or it can be formed using other resonator forming methods. In this embodiment, a detailed description of the resonator can be found in the corresponding descriptions in the foregoing embodiments, and will not be repeated here.

[0167] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a resonator, characterized in that, include: A piezoelectric stack structure is provided, the piezoelectric stack structure including a first region and a second region surrounding the first region, the piezoelectric stack structure having a first surface and a second surface opposite to the first surface; A first dielectric layer is formed on the first surface of the piezoelectric stack structure; A first substrate is provided, the top of which has a top doped region; The top of the first dielectric layer and the first substrate are bonded together; After bonding the top of the first dielectric layer and the first substrate together, a second dielectric layer is formed on the second surface of the piezoelectric stack structure; The first dielectric layer, the piezoelectric stack structure, and the second dielectric layer in the second region are etched to form a first opening and a second opening that expose the top doped region. Conductive material is filled into the first opening and the second opening to form a first plug and a second plug, respectively.

2. The method for forming a resonator as described in claim 1, characterized in that, In the step of providing the first substrate, the top doped region includes a well region; The method for forming the resonator further includes: after providing the first substrate, before bonding the first dielectric layer and the top of the first substrate, A first doped region and a second doped region are formed at the top of the well region, with phase spacing, and the dopant ions in the first doped region and the dopant ions in the second doped region have different conductivity types. In the step of forming the first opening and the second opening, the first opening exposes the first doped region, and the second opening exposes the second doped region.

3. The method for forming a resonator as described in claim 1 or 2, characterized in that, The top doped region is doped with P-type or N-type ions.

4. The method for forming a resonator as described in claim 2, characterized in that, In the steps of forming the first doped region and the second doped region, the first doped region is doped with N-type ions and the second doped region is doped with P-type ions.

5. The method for forming a resonator as described in claim 2, characterized in that, In the step of forming the first doped region and the second doped region, the interval between the first doped region and the second doped region is 3 micrometers to 1000 micrometers.

6. The method for forming a resonator as described in claim 2, characterized in that, The step of forming a phase-spaced first doped region and a second doped region at the top of the well region includes: A first shielding layer is formed to cover the well region, the first shielding layer having a first groove that exposes a portion of the well region in the second region; The first doped region is formed by doping the well region exposed by the first shielding layer with a first type of ion; The method for forming the resonator further includes: after forming the first doped region, removing the first shielding layer; After removing the first shielding layer, a second shielding layer is formed to cover the well area, the second shielding layer having a second groove that exposes a portion of the well area; The second doped region is formed by doping the well region exposed by the second shielding layer with a second type of ion; The method for forming the resonator further includes: after forming the second doped region, removing the second shielding layer.

7. The method for forming a resonator as described in claim 6, characterized in that, Ions are doped into the well region exposed by the first shielding layer using an ion implantation process to form a first doped region; Ions are doped into the well region exposed by the second shielding layer using an ion implantation process to form a second doped region.

8. The method for forming a resonator as described in claim 1 or 2, characterized in that, The method for forming the resonator further includes: before forming the first dielectric layer on the piezoelectric stacked structure in the first region, forming a first sacrificial layer on the piezoelectric stacked structure in the first region; In the step of forming the first dielectric layer, the first dielectric layer is formed on the first sacrificial layer and on the piezoelectric stack structure exposed by the first sacrificial layer; The method for forming the resonator further includes: bonding the top of the first dielectric layer and the first substrate together, and then forming a second sacrificial layer on the second surface of the piezoelectric stack structure in the first region; The method for forming the resonator further includes: after forming the second dielectric layer and before forming the first opening and the second opening, removing the first sacrificial layer and the second sacrificial layer.

9. The method for forming a resonator as described in claim 8, characterized in that, The step of removing the first sacrificial layer and the second sacrificial layer includes: etching the second dielectric layer, the second sacrificial layer and the piezoelectric stack structure in the first region to form a first release hole exposing the first sacrificial layer; After the first release hole is formed, the first sacrificial layer and the second sacrificial layer are removed; In the step of forming the first release hole, the first dielectric layer in the first region is also etched to form a second release hole that exposes the second sacrificial layer.

10. The method for forming a resonator as described in claim 1, characterized in that, The method for forming the resonator further includes: after forming the first opening and the second opening, and before filling the first opening and the second opening with conductive material, forming an insulating layer on the sidewalls of the first opening and the second opening.

11. The method for forming a resonator as described in claim 10, characterized in that, The insulating layer is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

12. The method for forming a resonator as described in claim 1, characterized in that, The first dielectric layer, the piezoelectric stack structure, and the second dielectric layer in the second region are etched using a dry etching process to form a first opening and a second opening that expose the top doped region.

13. The method for forming a resonator as described in claim 1 or 2, characterized in that, The method for forming the resonator includes: Before providing the piezoelectric stacked structure, a second substrate is provided; In the step of providing the piezoelectric stack structure, the piezoelectric stack structure is formed on the second substrate; The method for forming the resonator further includes: bonding the top of the first dielectric layer and the first substrate together, and then removing the second substrate.

14. A resonator, characterized in that, include: A first substrate, the first substrate including a first region and a second region surrounding the first region, the top of the first substrate having a top doped region; A first dielectric layer is located on the first substrate; A piezoelectric stacked structure is located on the first dielectric layer; The second dielectric layer is located on the piezoelectric stack structure; The first plug penetrates the second dielectric layer, the piezoelectric stack structure, and the first dielectric layer in the second region, and is in contact with the first substrate; The second plug penetrates the second dielectric layer, the piezoelectric stack structure, and the first dielectric layer in the second region and is in contact with the first substrate. The second plug is spaced apart from the first plug.

15. The resonator as claimed in claim 14, characterized in that, The top doped region includes a well region; The resonator further includes: a first doped region located at the top of the well region; The second doped region is located at the top of the well region, and the first doped region and the second doped region are spaced apart. The dopant ions in the first doped region and the dopant ions in the second doped region have different conductivity types. The first plug is in contact with the top of the first doped region. The second plug is in contact with the top of the second doped region.

16. The resonator as claimed in claim 14 or 15, characterized in that, The top doped region is doped with P-type or N-type ions.

17. The resonator as claimed in claim 15, characterized in that, The first doped region is doped with N-type ions, and the second doped region is doped with P-type ions.

18. The resonator as claimed in claim 15, characterized in that, The spacing between the first doped region and the second doped region is 3 micrometers to 1000 micrometers.

19. The resonator as claimed in claim 14, characterized in that, The resonator further includes: a first cavity located between the top of the first dielectric layer and the piezoelectric stack structure; The second cavity is located between the bottom of the second dielectric layer and the piezoelectric stack structure.

20. The resonator as claimed in claim 14, characterized in that, The resonator further includes: an insulating layer located between the first plug and the first dielectric layer, between the first plug and the piezoelectric stack structure, between the first plug and the second dielectric layer, between the second plug and the first dielectric layer, between the second plug and the piezoelectric stack structure, and between the second plug and the second dielectric layer.

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