Multi-state RF pulses to control mask shape and break the selectivity vs. process margin tradeoff

Abstract

A method for etching a substrate in a plasma processing system, the method comprising: applying source RF power and bias RF power to an electrode, wherein the source RF power and the bias RF power are pulsed signals that together define a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state; wherein the first state is defined by the source RF power having a first source RF power level and the bias RF power having a first bias RF power level; wherein the second state is defined by the source RF power and the bias RF power having a power level of substantially zero; and wherein the third state is defined by the source RF power having a second source RF power level less than the first source RF power level and the bias RF power having a power level of substantially zero.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a multi-state RF pulse scheme for controlling mask shape and breaking the selectivity versus process margin trade-off. Background Art

[0002] Over the past decade, RF pulse technology has evolved from operating in a continuous wave (CW) mode to operating in a pulsed mode (switching, level to level) mode. Advances in dual-state RF pulses have enabled high aspect ratio etching by improving process margins and etch selectivity, profile bending, critical dimension (CD), and etch rate uniformity. In the current dual-state RF pulse nomenclature, "State 1" (or "S1") represents a high bias and source power state, for example, greater than 1 kW, with an ion energy greater than 3 keV, operating at a pressure less than 30 mTorr to obtain a narrow IADF. The other state in the pulse, called "State 0" (or "S0"), represents a deposition step with low bias and source power (for example, less than 1 kW, with an ion energy less than 100 eV). State 0 primarily provides passivation due to different mechanisms such as direct ion deposition and ion-activated neutral deposition. Typical pulse repetition rates for operating this dual-state RF pulse scheme are approximately 100 Hz to 2 kHz.

[0003] As device dimensions continue to shrink further and as pitch dimensions decrease further (e.g., currently from 100nm to less than about 60nm), it is difficult to break the etch selectivity vs. process margin tradeoff with current pulsed technology. Current technology solutions strive to balance good high aspect ratio etching while maintaining sufficient process margin (e.g., under-etching, under-opening, capping).

[0004] It is against this background that embodiments of the present disclosure emerge. Summary of the Invention

[0005] Embodiments of the present disclosure include methods and systems for a multi-state RF pulse scheme to control mask shape and break the selectivity versus process margin tradeoff.

[0006] One of the main challenges in high aspect ratio (HAR) contact etching is maintaining sufficient process margin while attempting to selectively etch the stack compared to the mask (e.g., poly). Typically, process margin is related to the shape and magnitude of the necking, as this establishes a limiting aspect ratio during the HAR process. However, embodiments of the present disclosure provide a method to control the mask (neck) shape and improve the selectivity vs. process margin tradeoff.

[0007] According to embodiments of the present disclosure, a multi-state RF pulse with an intermediate state based on a source-only power scheme helps control the mask shape (neck trimming) without causing undesirable mask faceting. Combining this source-only power pulse scheme with conventional two-state switching pulses significantly improves the margin-selectivity tradeoff to take advantage of the HAR process improvement knob.

[0008] In some embodiments, a method for performing an etching process on a substrate in a plasma processing system is provided, the method comprising: applying source RF power to an electrode of the plasma processing system; and applying bias RF power to the electrode; wherein the source RF power and the bias RF power are pulsed signals that together define a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state; wherein the first state is defined by the source RF power having a first source RF power level and the bias RF power having a first bias RF power level; wherein the second state is defined by the source RF power having a power level of substantially zero and the bias RF power having a power level of substantially zero; wherein the third state is defined by the source RF power having a second source RF power level less than the first source RF power level and the bias RF power having a power level of substantially zero.

[0009] In some embodiments, the first state is configured to enable etching of features on the substrate surface.

[0010] In some embodiments, the second state is configured to effect passivation of features on the substrate surface.

[0011] In some embodiments, the third state is configured to effectuate removal of material forming a neck in the feature.

[0012] In some embodiments, the bias RF power has a frequency less than about 10 MHz.

[0013] In some embodiments, the source RF power has a frequency greater than about 20 MHz.

[0014] In some embodiments, the duration of the third state is approximately one to five times the duration of the first state.

[0015] In some embodiments, the duration of the second state is approximately equal to the duration of the first state.

[0016] In some embodiments, the first source RF power level is approximately in the range of 1 to 6 kW; wherein the first bias RF power level is approximately in the range of 5 to 20 kW.

[0017] In some embodiments, the second source RF power level is approximately in the range of 100 W to 6 kW.

[0018] In some embodiments, within each cycle, the third state immediately follows the second state.

[0019] In some embodiments, within each cycle, the second state immediately follows the third state.

[0020] In some embodiments, a controller device is provided that is configured to cause a plasma processing system to perform an etching process on a substrate in the plasma processing system, the method comprising the following operations: applying source RF power to an electrode of the plasma processing system; and applying bias RF power to the electrode; wherein the source RF power and the bias RF power are pulsed signals that together define a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state; wherein the first state is defined by the source RF power having a first source RF power level and the bias RF power having a first bias RF power level; wherein the second state is defined by the source RF power having a substantially zero power level and the bias RF power having a substantially zero power level; and wherein the third state is defined by the source RF power having a second source RF power level less than the first source RF power level and the bias RF power having a substantially zero power level.

[0021] It should be understood that the foregoing represents a summary of certain non-limiting embodiments of the present disclosure. Additional implementations will be apparent to those skilled in the art, given the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A A cross-sectional perspective view of a typical DRAM device 100 is conceptually shown in accordance with an embodiment of the present disclosure.

[0023] Figure 1B A cross-sectional perspective view of a high aspect ratio etched feature is conceptually shown in accordance with an embodiment of the present disclosure.

[0024] Figure 2A is a graph of RF power versus time for a single pulsed RF cycle for an etching process according to an embodiment of the present disclosure.

[0025] Figure 2B and 2C Cross-sectional views of etched features according to the S1 and S0 states of the above-described two-stage pulse process are conceptually shown.

[0026] Figure 3 Conceptually illustrates the trade-offs in current RF pulse technology.

[0027] Figure 4A 、 4B4C conceptually illustrate RF power versus time for a multi-state pulsed RF cycle according to an embodiment of the present disclosure.

[0028] Figure 4D 、 4E 4F conceptually illustrate a cross-section of an etched feature showing the effect of each state of the multi-state pulsed RF cycling described herein.

[0029] Figure 5 Conceptually illustrated is the changing length of state S2 over time during etching of a feature according to an embodiment of the present disclosure.

[0030] Figure 6A 、 6B 6C show graphs of RF power versus time showing multi-state RF pulse cycles according to an embodiment of the present disclosure.

[0031] Figure 6D 、 6E and 6F conceptually illustrate a cross section of an etched feature, which illustrates the Figure 6A 、 6B and the effects of states S1, S2, and S0 of the embodiment of 6C.

[0032] Figure 7 Conceptually illustrated is the expansion of the process window by using the multi-state RF pulsing scheme described herein.

[0033] Figure 8 An exemplary ICP deposition system according to an embodiment of the present disclosure is shown.

[0034] Figure 9 A control module for controlling the above-mentioned system according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to avoid unnecessarily obscuring the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific exemplary embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

[0036] Currently, the state-of-the-art dielectric etch processes rely on implementing one or two RF schemes supported by on / off or secondary RF pulses to combine the advantages of high vertical etch rate and sufficient sidewall passivation. However, according to embodiments of the present disclosure, additional schemes are identified that can independently recover or add more margin in the process. An embodiment is provided based on this scheme, thereby combining a suitable intermediate state based on implementing a multi-state RF pulse scheme, which overcomes the basic process development limitations and obstacles in existing etching technology. The intermediate state is based on preferential trimming of the mask neck polymer at a low ion energy state to promote a more aggressive high energy state (on / high state) and a more polymeric passivating state (off / low state). Introducing this low ion energy state with source power only helps to control the neck / mask shape. Combining this approach with an on / off pulse rather than a secondary pulse drives more polymer deposition on the top of the mask, thereby passivating the top of the mask and controlling the mask etch rate. This method fundamentally enables breaking the trade-off between mask neck / process margin and selectivity.

[0037] Figure 1A A cross-sectional perspective view of a typical DRAM device 100 according to an embodiment of the present disclosure is conceptually shown. A typical DRAM device may be composed of a stack that is 1 to 1.5 microns high, and the fabrication of such a DRAM device includes the creation of a capacitor 102, which requires a capacitor etch process. Capacitor etch is an example of a dielectric etch process that requires proper etching of very high aspect ratio features (conceptually shown at reference numeral 104; e.g., on the order of 60 to 100 to 1 depending on the node). In addition, the pitch dimensions are also scaling smaller and smaller, and as the aspect ratio becomes higher and higher, the tolerance for defects in the etching process becomes smaller and smaller. For capacitor etching, for example, but not limited to, the pitch dimension can be less than 50 nm. It should be understood that while embodiments of the present disclosure are described with reference to capacitor etching, the principles of the present disclosure can be applied to any high aspect ratio dielectric etch (e.g., 3D NAND, e.g., memory hole etching) in any applicable device environment.

[0038] Figure 1B A cross-sectional perspective view of a high aspect ratio etched feature according to an embodiment of the present disclosure is conceptually illustrated. Several problems that may arise in high aspect ratio etches, such as in the context of DRAM capacitor manufacturing as described above, are further conceptually illustrated. These problems may include: bowing of the feature, where a portion of the etch profile becomes reentrant; twisting of the feature, where the etch direction deviates laterally from a straight vertical direction; critical dimension variations from top to bottom, such as a feature that is wider at the top than at the bottom; incomplete etching, where a feature is not fully etched to its desired endpoint; and insufficient selectivity to the hard mask, where the hard mask is etched, which can cause it to become faceted and exacerbate the bowing problem.

[0039] Therefore, in high aspect ratio etching, it is desirable to achieve profile control to achieve straight profile etching without bowing with minimized distortion and minimized aspect ratio dependent etching (ARDE). It is desirable to have selectivity to the hard mask to avoid incomplete etching (under-etching). In addition, uniformity across the wafer is sought, as well as maintaining the integrity of the underlying layer.

[0040] Figure 2A is a graph of RF power versus time for a single pulsed RF cycle for an etching process according to an embodiment of the present disclosure. The bias RF power and source RF power are shown as a function of time during a single pulsed RF cycle. With current RF pulse technology, a dual-state pulse scheme using secondary or on-off pulses is employed. In this dual-state pulse scheme, State 1 (S1) is a high ion energy generation state where the source RF and bias RF are in a high power state, while State 0 (S0) is a low ion energy generation state where the source RF and bias RF are in a low power or completely off state. The function of S1 is to etch dielectric materials because S1 produces high energy ions that are used to activate the surface and etch the film. Whereas the primary role of S0 is passivation because S0 is primarily neutral driven, thereby driving passivation in the etched features, although there can still be some low energy to maintain etching.

[0041] Figure 2B and 2C Conceptually, a cross-sectional view of an etched feature according to the S1 and S0 states of the two-stage pulse process described above is shown. As shown, S1 primarily enables etching of high-aspect-ratio features, but can also result in sputtering of the mask and the formation of a "neck" profile. S0 primarily enables passivation, thereby protecting the mask through direct ion deposition and ion-assisted neutral deposition.

[0042] So, with two-level (L2L) pulsed RF, S1 provides high aspect ratio etching but also sputters and forms a neck; S0 provides ion-assisted neutral deposition. However, both result in some degree of necking, and as one moves to higher AR and smaller pitches, opening the neck becomes difficult. For L2L, the tightest critical dimension occurs at the neck, and this tends to limit etching as the feature size or pitch size becomes very small. For example, the neck AR can be almost twice the feature AR. This also limits the types of chemistries one can apply and the amount of excitation that can be applied to the structure to etch, so this acts as a limiter in high aspect ratio etching.

[0043] Figure 3Conceptually illustrates the tradeoffs in current RF pulse technology. For example, in dielectric high aspect ratio contact etching (e.g., in DRAM & 3D NAND), there are some limitations and constraints when using current two-stage RF pulse schemes. With current two-stage pulses, for State 1, a high power bias (e.g., 400kHz frequency) would be desirable, but is not practically available due to hole blocking at high ratios of 400kHz:60MHz. And chemical adjustments to compensate can result in excessive bending. For State 0, low power is used to maintain mask selectivity and bending. Higher power can improve blocking but will compromise mask selectivity. Given these limitations, it is difficult to break the tradeoff in two-state pulses.

[0044] Therefore, current technology has encountered limitations in terms of scalability. As the stack becomes taller, the aspect ratio increases, and the deeper the features, the etch rate decreases as a function of aspect ratio dependent etching (ARDE). Therefore, in order to maintain profiles with deeper aspect ratios, the typical trade-off is between the stack etch rate and the ARDE. For tighter and tighter pitches, in order to prevent bowing, high ion energies for mask faceting are used. That is, S1 is operated to produce a high ion energy state and it causes mask faceting. On the other hand, in order to reduce the cost of smaller pitch sizes, manufacturers want to reduce the amount of mask material. Given the mask and the stack below, as the industry moves to smaller and smaller pitches, cost reductions are sought by using less mask material. Therefore, the selectivity of the mask is important. But to improve selectivity at high aspect ratios, the price is clogging. The holes clog each other, which can cause device failure.

[0045] Therefore, under current RF pulsing schemes, these trade-offs are seen and it is difficult to break the trade-off to improve the profile in any one direction.

[0046] However, according to embodiments of the present disclosure, a multi-state RF pulse scheme is introduced, where the intermediate states are based on a source-only power scheme. This multi-state RF pulse scheme significantly improves the margin-selectivity trade-off to enable improved etching of high aspect ratio features with suitable profiles and mask selectivity.

[0047] Figure 4A 、 4B 4C conceptually illustrate RF power versus time for a multi-state pulsed RF cycle according to an embodiment of the present disclosure. Figure 4A Both the bias RF power and the source RF power are shown. For greater clarity, Figure 4B Only the bias RF power is shown over time, and Figure 4C Only the source RF power is shown as a function of time. Figure 4D 、 4E4F conceptually illustrate a cross section of an etched feature showing the effect of each state of the multi-state pulsed RF cycle described herein. The pulsed RF cycle can be characterized as a three-level pulsed RF employing three different RF states. As shown in the illustrated embodiment, S1 is configured to provide high source power and high bias power. Figure 4D As shown, this produces a high aspect ratio (HAR) etch, but also produces sputtering of the mask to form the neck. S0 is configured as an off state, where no source or bias power is applied. Figure 4E As shown, SO drives more neutral deposition on top, thereby protecting the mask. In some embodiments, SO is configured to provide direct ion deposition and ion-assisted neutral deposition.

[0048] The intermediate state S2 (State2) is configured as a source-only power state (e.g., 60 MHz, high frequency) using low source power and zero bias power. Figure 4F As shown, S2 helps to induce dissociation and open the neck by etching any formed neck. Therefore, state S2 is configured to open the neck.

[0049] Therefore, according to embodiments of the present disclosure, S1 uses high-energy ions, which form a neck, but S2 opens the neck, while S0 provides a large amount of passivation. The resulting feature has an open neck and, due to the increased passivation, more mask. This resolves the neck vs. selectivity tradeoff.

[0050] In contrast, in a two-stage RF pulse scheme running only S1 and S0, there is a lot of passivation, but also a neck, which can cause blockage. However, by using a three-stage RF pulse scheme with S1, S0, and S2, this provides an open neck and passivation, breaking the trade-off between selectivity and cap margin. Broadly speaking, state S0 provides selectivity, while state S2 improves cap margin.

[0051] Generally speaking, in some embodiments, the bias power is at a frequency of less than about 10 MHz. In some embodiments, the bias power is at a frequency of about 400 kHz.

[0052] In some embodiments, the source power is at a frequency greater than about 10 MHz. In some embodiments, the source power is at a frequency greater than about 20 MHz. In some embodiments, the source power is at a frequency of about 60 MHz.

[0053] In some embodiments, the bias and source frequency are applied to the chuck using different generators.

[0054] It should be understood that in various embodiments, the specific parameters of bias and source power may vary in each state.

[0055] In some embodiments, the S1 bias power is in the range of approximately 5 to 20 kW. In some embodiments, the S1 source power is in the range of approximately 1 to 6 kW. In some embodiments, either or both the S1 bias power and the S1 source power can vary over time, for example depending on the elapsed time of etching within the feature, the current depth of the feature, or the current aspect ratio of the feature. In some embodiments, the S1 bias power and / or the S1 source power are configured to increase as the elapsed etch time, depth, or aspect ratio increases.

[0056] Generally speaking, the SO state is envisioned to be an off state in which both the bias power and the source power are at substantially zero or near zero levels.

[0057] In some embodiments, the S2 bias power is substantially zero or near zero. In some embodiments, the S2 source power is in the range of approximately 100 W to 6 kW. In some embodiments, the S2 source power can vary over time, for example depending on the elapsed time of etching within the feature, the current depth of the feature, or the current aspect ratio of the feature. In some embodiments, the S2 source power is configured to increase as the elapsed etch time, depth, or aspect ratio increases.

[0058] It should be understood that the relative durations of S1, S0, and S2 can also be configured to provide a suitable etch profile and etch rate according to embodiments of the present disclosure. In some embodiments, the ratio of the duration of S2 to S1 is in the range of about one to one (1:1) to five to one (5:1).

[0059] In some embodiments, the ratio of the duration of SO to S1 is approximately one to one (1:1).In some embodiments, this ratio can vary.

[0060] It should be understood that the relative duration of the various states can depend on the pitch, the depth of the etch, and the parameters to be controlled. For example, for a relatively shallow AR etch, S2 does not need to be very long to open the neck because AR does not play a significant role at the beginning of the etch. However, as the etch deepens and higher AR etches are required, S2 plays an important role in opening the neck to achieve higher aspect ratio etches.

[0061] Figure 5The length of state S2 is conceptually illustrated as it changes over time during the etching of a feature according to an embodiment of the present disclosure. In the illustrated graph 500, the duration of S2 is shown as a function of etch depth / time / aspect ratio. As indicated, the duration of S2 increases with increasing current etch depth within the feature, etch time for the feature, or current aspect ratio of the feature. By way of example and not limitation, when a feature has a relatively shallow depth and therefore a low aspect ratio (as conceptually shown at reference numeral 502), as may occur earlier in the etching of the feature, the source RF power profile may appear as shown in graph 504, where the duration of S2 is relatively short. In contrast, when a feature has a relatively deep depth and therefore a high aspect ratio (as conceptually shown at reference numeral 506), as may occur later in the etching of the feature, the source RF power profile may appear as shown in graph 504, where the duration of S2 is relatively long.

[0062] Therefore, the higher the aspect ratio, the longer the S2 duration, as the neck opening step becomes more critical to maintaining the etch profile. The durations of S1, S0, and S1 are all variable, and S2 can also depend on S1 and S0. The source RF power is configured to remove the neck and then perform passivation.

[0063] In the above embodiment, the various states have been run in the order S1-S0-S2 (and repeated). Broadly speaking, this provides etching (provided by S1), then passivation (provided by S0), then neck opening (provided by S2).

[0064] However, in other embodiments, S2 may occur between S1 and S0, such that the sequence of states is S1-S2-S0 (and repeats.) This provides etching (provided by S1), followed by neck opening (provided by S2), and then passivation (provided by S0).

[0065] Figure 6A 、 6B 6C show graphs of RF power versus time showing multi-state RF pulse cycles according to an embodiment of the present disclosure. Figure 6A Both the bias RF power and the source RF power are shown as a function of time. For greater clarity, Figure 6B Only the time-varying bias RF power is shown, while Figure 6COnly the source RF power is shown over time. In the embodiment shown, the states are sequentially executed from S1 to S2 to S0. As in the previously described embodiments, S1 is a high ion energy state employing high bias power and high source power. S2 is a source power-only state employing substantially zero bias power and low source power. S0 is an off state employing substantially zero bias power and substantially zero source power.

[0066] Figure 6D 、 6E and 6F conceptually illustrate a cross section of an etched feature, which illustrates the Figure 6A 、 6B and the effects of states S1, S2, and S0 of the embodiment of 6C. Figure 6D As shown, state S1 generates high ion energy to enable etching of high aspect ratio features, but also produces sputtering of the mask and causes neck formation in the features. Figure 6E As shown, state S2 produces medium-low ion energy with an open neck. Figure 6F As shown, state S0 protects the mask by enabling direct ion deposition and ion-assisted neutral deposition.

[0067] Embodiments of the present disclosure are applicable to dielectric etching. In some embodiments, fluorine-based chemistries such as fluorocarbons, hydrofluorocarbons, etc. are employed.

[0068] When RF pulse schemes first began, they operated as on-off pulses (S1S0). However, this caused a lot of passivation, so the industry moved to two-stage pulses, where some power was put into S0. This, however, lost the benefit of increased selectivity, as putting in more power introduced ions that sputtered out the passivation. However, with the three-stage multi-state RF pulses presented here, a new source-only state is used that opens the neck while still using passivation. This breaks the traditional process trade-off between selectivity and neck.

[0069] Figure 7 The expansion of the process window by using the multi-state RF pulse scheme described herein is conceptually illustrated. In particular, there is a trade-off between unopened margin and bridging. The unopened state is shown at reference numeral 700, where the HAR etch fails due to neck buildup at the feature opening. However, the cost of the unopened state is bowing of the feature and can cause features to bridge to each other, creating open contacts that cause device failure. Therefore, there is a process window between the unopened and bridged states, but this process window becomes narrower with the reduction in CD / pitch size with each new / advanced technology node. Therefore, a key process goal is to achieve bow reduction without sacrificing unopened margin in order to expand high aspect ratio contact etch capabilities. Improvements to the unopened margin resulting from smaller neck / large capping margins are sought; and improvements to the bridging margin for bow reduction are also sought.

[0070] Graph 704 shows a defectivity versus post-etch inspection graph illustrating the process window under continuous wave (reference numeral 706), two-level (reference numeral 708), and the presently described three-level (reference numeral 710) RF pulsing schemes.

[0071] Starting with early continuous wave (CW) schemes, as pitch sizes decreased, the technology progressed to two-stage pulsing, where the pulses alternate between etching and passivation states, which improved the process window for high-aspect ratio etching. However, the technology has now reached a point where pitch size dictates how well one can etch high-aspect ratio features. As shown, the three-stage RF pulsing scheme introduced in this paper further broadens the process operating window, enabling etching without equipment failure. As can be seen, the process window is now wider, and defects can be controlled within this window.

[0072] As mentioned above, clogging occurs when there is too much polymer on the neck and the feature opening is blocked, or bridging occurs because the bend is so large that the hole bridge becomes one (resulting in an open contact). In continuous wave mode, a profile such as shown at reference mark 712 can be seen, which mainly blocks the neck. In secondary mode, a profile such as shown at reference mark 714 is provided, where there is a larger neck and a smaller bend, so the clogging is controlled, but the process window is very short. But with a tertiary pulse according to an embodiment of the present disclosure, a profile such as shown at reference mark 716 provides a wider open neck, and an even better process window. Faster etch rates and better selectivity are possible because the neck ARDE is alleviated.

[0073] Another benefit is the three-level RF pulse scheme that enables a wider range of chemistries. While it is generally difficult to introduce new chemistries as pitch dimensions get smaller, providing a wider process window opens up not only the RF scheme but also the chemistry scheme, enabling the application of a wider range of passivation chemistries for sidewall passivation.

[0074] Various embodiments described herein can be implemented in a plasma processing system. Figure 8An exemplary plasma processing system or apparatus may include a chamber 801 having a gas injector / showerhead / nozzle 803 for distributing gases (805, 807, 809) (e.g., reactants and purge gases) or other chemicals into the chamber 801; a chamber wall 811; and a chuck 813 for holding a substrate or wafer 815 to be processed, which may include electrostatic electrodes for clamping and releasing the wafer. The chuck 813 is heated for thermal control, thereby enabling the substrate 815 to be heated to a desired temperature. In some embodiments, the chuck 813 may be charged using an RF power supply 817 to provide a bias voltage according to embodiments of the present disclosure.

[0075] A source RF power supply 819 is configured to provide source RF power to electrodes in the chuck 813 to generate a plasma 825 in the processing volume above the substrate 815. In some embodiments, the chamber walls are heated to support thermal management and efficiency. A vacuum source 827 provides a vacuum to extract gases from the chamber 801. The system or apparatus may include a system controller 829 for controlling some or all operations of the chamber or apparatus, such as adjusting chamber pressure, inert gas flow, plasma source power, plasma source frequency, reactant gas flow, bias power, bias frequency, temperature, vacuum settings, and other processing conditions.

[0076] In some embodiments, a system / apparatus may include more than one chamber for processing a substrate.

[0077] Figure 9 A control module 900 for controlling the above-described system according to an embodiment of the present disclosure is shown. For example, the control module 900 may include a processor, a memory, and one or more interfaces. The control module 900 may be used to control devices in the system based in part on sensed values. For example, the control module 900 may control one or more of a valve 902, a filter heater 904, a pump 906, and other devices 908 based on sensed values and other control parameters. The control module 900 receives sensed values from, for example, a pressure gauge 910, a flow meter 912, a temperature sensor 914, and / or other sensors 916. The control module 900 may also be used to control process conditions during reactant delivery and plasma processing. The control module 900 will typically include one or more memory devices and one or more processors.

[0078] The control module 900 can control the activities of the reactant delivery system and the plasma processing apparatus. The control module 900 executes a computer program that includes an instruction set for controlling processing time, delivery system temperature, pressure differential across the filter, valve position, gas mixture, chamber pressure, chamber temperature, wafer temperature, RF power level, wafer ESC or susceptor position, and other parameters of a specific process. The control module 900 can also monitor the pressure differential and automatically switch the vapor reactant delivery from one or more paths to one or more other paths. In some embodiments, other computer programs stored on a memory device associated with the control module 900 can be used.

[0079] There will typically be a user interface associated with the control module 900. The user interface may include a display 918 (e.g., a display screen and / or graphical software display of device and / or process conditions), and a user input device 920, such as a pointing device, keyboard, touch screen, microphone, etc.

[0080] Computer programs for controlling reactant delivery, plasma treatment, and other processes in a process sequence can be written in any conventional computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by a processor to perform the tasks identified in the program.

[0081] Control module parameters relate to process conditions such as filter differential pressure, process gas composition and flow rate, temperature, pressure, plasma conditions such as RF power level and RF frequency, coolant gas pressure, and chamber wall temperature.

[0082] The system software can be designed or configured in many different ways. For example, various chamber component subroutines or controls can be written to control the operation of the chamber components required to perform the deposition processes of the present invention. Examples of programs or program portions used for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code.

[0083] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the disclosed embodiments. It should be noted that there are many alternative ways to implement the processes, systems, and devices of the embodiments of the present invention. Therefore, the embodiments of the present invention are to be considered as illustrative rather than restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. An etch process for etching features having a high aspect ratio on a substrate in a plasma processing system, the method comprising: applying source RF power to an electrode of the plasma processing system; as well as applying bias RF power to the electrode; wherein the source RF power and the bias RF power are pulsed signals that together define a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state; wherein said first state is defined by said source RF power having a first source RF power level and said bias RF power having a first bias RF power level; wherein said second state is defined by said source RF power having a substantially zero power level and said bias RF power having a substantially zero power level; wherein the third state is defined by the source RF power having a second source RF power level and the bias RF power having a substantially zero power level, wherein the second source RF power level is less than the first source RF power level; wherein the first state is configured to effectuate etching of a feature on a surface of the substrate; wherein the second state is configured to effect passivation of the feature on the surface of the substrate; as well as The third state is configured to effect removal of material forming a neck in the feature.

2. The method of claim 1 wherein the high aspect ratio of features etched on the substrate is defined as at least 60 to 1.

3. The method of claim 1, wherein the high aspect ratio of features etched on the substrate is defined as 100 to 1.

4. The method of claim 1 wherein the high aspect ratio of features etched on the substrate is defined as 60 to 1 to 100 to 1. The method of claim 1 , wherein the bias RF power has a frequency less than 10 MHz. The method of claim 1 , wherein the source RF power has a frequency greater than 20 MHz. The method according to claim 1 , wherein a duration of the third state is one to five times a duration of the first state. The method of claim 1 , wherein a duration of the second state is equal to a duration of the first state.

9. The method according to claim 1, wherein the first source RF power level is in the range of 1 to 6 kW; and The first bias RF power level is in the range of 5 to 20 kW.

10. The method of claim 1, wherein the second source RF power level is in the range of 100 W to 6 kW. The method of claim 1 , wherein within each cycle, the third state immediately follows the second state.

12. The method of claim 1, wherein in each cycle, the second state immediately follows the third state.

13. A controller apparatus configured to cause a plasma processing system to perform an etch process on a substrate in the plasma processing system to etch features having a high aspect ratio, the etch process comprising the following operations: applying source RF power to an electrode of the plasma processing system; as well as applying bias RF power to the electrode; wherein the source RF power and the bias RF power are pulsed signals that together define a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state; wherein said first state is defined by said source RF power having a first source RF power level and said bias RF power having a first bias RF power level; wherein said second state is defined by said source RF power having a substantially zero power level and said bias RF power having a substantially zero power level; wherein the third state is defined by the source RF power having a second source RF power level and the bias RF power having a substantially zero power level, wherein the second source RF power level is less than the first source RF power level; wherein the first state is configured to effectuate etching of a feature on a surface of the substrate; wherein the second state is configured to effect passivation of the feature on the surface of the substrate; as well as The third state is configured to effect removal of material forming a neck in the feature.

14. The controller device of claim 13, wherein the high aspect ratio of features etched on the substrate is defined as at least 60 to 1.

15. The controller device of claim 13, wherein the high aspect ratio of features etched on the substrate is defined as 100 to 1.

16. The controller device of claim 13, wherein the high aspect ratio of features etched on the substrate is defined as 60 to 1 to 100 to 1.

17. The controller device of claim 13, wherein the bias RF power has a frequency less than 10 MHz.

18. The controller device of claim 13, wherein the source RF power has a frequency greater than 20 MHz.

19. The controller device of claim 13, wherein a duration of the third state is one to five times a duration of the first state.

20. The controller device of claim 13, wherein a duration of the second state is equal to a duration of the first state.

21. The controller device according to claim 13, wherein the first source RF power level is in the range of 1 to 6 kW; and The first bias RF power level is in the range of 5 to 20 kW.

22. The controller device of claim 13, wherein the second source RF power level is in the range of 100 W to 6 kW.

23. The controller device of claim 13, wherein within each cycle, the third state immediately follows the second state.

24. The controller device of claim 13, wherein within each cycle, the second state immediately follows the third state.

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