Chip performance test fixture

Abstract

The present invention provides a chip performance test fixture, including an electric control board, a signal input terminal, a signal output terminal, and a plurality of test terminals. Among them, a signal test circuit is arranged on the electric control board, including a first parallel mounting position, a second parallel mounting position, a plurality of strobe mounting positions, a series mounting position, a first signal line, a plurality of second signal lines, and a third signal line. The first parallel mounting position, the second parallel mounting position, and the series mounting position are all used to access a connecting element; the lengths of the plurality of second signal lines are different, and the plurality of strobe mounting positions are used to select the second signal line through which the test signal passes when accessing a connecting element. The present invention realizes the simulation of the line path of chip signal transmission in an actual project, verifies its signal performance, reduces the chip selection error rate, shortens the R&D design cycle, and reduces the R&D cost.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic device testing, and in particular to a chip performance testing tool. Background Art

[0002] Existing chip manufacturers generally only provide chip-matching development boards for R&D personnel to perform simple signal tests on the chip's functions when selling. However, in actual applications, devices electrically connected to the chip's pins, circuit boards of different sizes, and different routing methods will affect the integrity of the chip's output signal. Therefore, simply using a development board cannot simulate the signal performance verification on an actual project. At the same time, when designing the PCB Layout (circuit wiring), you can only simply calculate the impedance on the chip's signal transmission path, and cannot determine its impact on the signal. If you test the board, you may need to modify and repeat the board multiple times to get a relatively satisfactory circuit wiring path, which results in a long design cycle for the entire circuit R&D and low R&D test efficiency. Summary of the invention

[0003] The main purpose of the present invention is to provide a chip performance test fixture, which aims to realize the chip signal performance verification in the simulation actual project, improve the R&D test efficiency of circuit board wiring, and shorten the R&D design cycle.

[0004] To this end, the present invention proposes a chip performance test fixture, which includes:

[0005] An electric control board, wherein a signal test circuit is provided on the electric control board;

[0006] A signal input terminal, which is arranged on the electronic control board and is used to connect to the pin of the chip and receive the test signal output by the chip;

[0007] A signal output terminal, the signal output terminal is arranged on the electric control board, and the signal output terminal is used to connect to the access interface;

[0008] A plurality of test terminals; the test terminals are used to access a test device, and the plurality of test terminals are electrically connected to the signal test circuit;

[0009] The signal test circuit includes a first parallel mounting position, a second parallel mounting position, a plurality of strobe mounting positions, a series mounting position, a first signal line, a plurality of second signal lines and a third signal line; a first end of the first signal line and a first end of the first parallel mounting position are respectively electrically connected to the signal input end, a second end of the first signal line is connected to the first ends of the plurality of strobe mounting positions, second ends of the plurality of strobe mounting positions are respectively connected to the first ends of the plurality of second signal lines in a one-to-one correspondence, second ends of the plurality of second signal lines are all connected to the first end of the series mounting position, a first end of the third signal line is connected to the second end of the series mounting position, a second end of the third signal line is connected to the signal output end, and a second end of the first parallel mounting position and a second end of the second parallel mounting position are both grounded;

[0010] Among them, the first parallel mounting position, the second parallel mounting position, and the series mounting position are all used to connect to the connecting element; the lengths of multiple second signal lines are different, and multiple selection mounting positions are used to select the second signal line through which the test signal passes when connecting to a connecting element.

[0011] Optionally, the plurality of test terminals include a first test terminal and a second test terminal, the first test terminal is electrically connected to the signal input terminal, and the second test terminal is connected to the signal output terminal.

[0012] Optionally, a differential signal test area is provided on the electric control board, and a plurality of completely identical signal test circuits are provided in the differential signal test area.

[0013] Optionally, the electric control board has a first wiring layer and a second wiring layer, a first high-speed signal test area is arranged on the first wiring layer of the electric control board, a grounding copper clad is arranged around the first high-speed signal test area of ​​the electric control board, and the signal test line is arranged in the first high-speed signal test area; a grounding copper clad is arranged on the second wiring layer of the electric control board relative to the first high-speed signal test area;

[0014] Wherein, the first signal line, the plurality of second signal lines and the third signal line in the signal test circuit in the first high-speed signal test area are all microstrip lines.

[0015] Optionally, the electric control board is a multi-layer board, and the electric control board also has an inter-board wiring layer;

[0016] A second high-speed signal test area is also provided on the first wiring layer of the electric control board, and the signal test circuit is provided in the second high-speed signal test area; a grounding copper is provided on the second wiring layer of the electric control board relative to the second high-speed signal test area;

[0017] Wherein, a grounding copper clad is provided in the second high-speed signal test area;

[0018] The first parallel mounting position, the second parallel mounting position, the series mounting position, and the plurality of strobe mounting positions in the signal test circuit in the second high-speed signal test area are all arranged on the first wiring layer of the electric control board;

[0019] The first signal line, the plurality of second signal lines and the third signal line in the signal test circuit in the second high-speed signal test area are all strip lines and are all arranged in the inter-board wiring layer.

[0020] Optionally, the first high-speed signal test area has a plurality of signal test circuits, and the plurality of signal test circuits in the first high-speed signal test area are completely identical;

[0021] The second high-speed signal test area has a plurality of signal test circuits, and the plurality of signal test circuits in the second high-speed signal test area are completely identical.

[0022] Optionally, the routing types of the first signal line, the second signal line and the third signal line are different.

[0023] Optionally, the first signal line, the second signal line and the third signal line have different line widths.

[0024] The present invention provides a chip performance test fixture, which includes an electric control board, a signal input terminal, a signal output terminal, and a plurality of test terminals. Among them, a signal test circuit is arranged on the electric control board, including a first parallel mounting position, a second parallel mounting position, a plurality of strobe mounting positions, a series mounting position, a first signal line, a plurality of second signal lines, and a third signal line. The signal input terminal is used to connect with the pin of the chip and access the test signal output by the chip, the signal output terminal is used to access the interface, the test terminal is used to access the test device, the first parallel mounting position, the second parallel mounting position, and the series mounting position are all used to access the connection element; the lengths of the plurality of second signal lines are different, and the plurality of strobe mounting positions are used to select the second signal line through which the test signal passes when accessing a connection element. In this way, the R&D test personnel can set different connection elements on the mounting position in the project development to estimate the signal performance of the signals output by different simulated chips in the actual project in advance, so as to provide a design reference for the drawing of the PCB Layout, thereby reducing the design risk in the actual project, reducing the number of repeated board making, and further improving the R&D test efficiency of the circuit board wiring, shortening the R&D design cycle, and reducing the R&D cost. At the same time, the performance of newly purchased chips can also be tested to reduce the error rate in chip selection. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0026] Figure 1 It is a structural schematic diagram of an embodiment of a chip performance test fixture of the present invention;

[0027] Figure 2 It is a structural schematic diagram of another embodiment of the chip performance test fixture of the present invention;

[0028] Figure 3 It is a structural schematic diagram of another embodiment of the chip performance test fixture of the present invention;

[0029] Figure 4 It is a structural schematic diagram of another embodiment of the chip performance test fixture of the present invention;

[0030] Figure 5 It is a structural schematic diagram of another embodiment of the chip performance test fixture of the present invention;

[0031] Figure 6 It is a structural schematic diagram of another embodiment of the chip performance test fixture of the present invention;

[0032] Figure 7 It is a structural schematic diagram of another embodiment of the chip performance test fixture of the present invention;

[0033] Figure 8 It is a structural schematic diagram of another embodiment of the chip performance test fixture of the present invention;

[0034] Fig. 9 The figure is a schematic diagram of a specific circuit structure of an embodiment of a chip performance test fixture of the present invention.

[0035] Description of Figure Numbers:

[0036] Label name Label name 10 Electric control panel 11 First parallel installation position 12 Second parallel installation position 13 Strobe mounting position 14 Tandem mounting position 15 First signal line 16 Second signal line 17 The third signal line 20 Signal input terminal 30 Signal output terminal 41 First test end 42 Second test end 40 Test terminal

[0037] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0040] Existing chip manufacturers generally only provide development boards that match the chips when selling them to R&D personnel to perform simple signal tests on the chip's functions. However, in actual applications, devices electrically connected to the chip's pins, circuit boards of different sizes, and different routing methods will affect the integrity of the chip's output signal. Therefore, simply using a development board cannot simulate the signal performance verification on an actual project. At the same time, when designing the PCB Layout (circuit wiring), you can only simply calculate the impedance on the chip's signal transmission path, but you cannot determine its impact on the signal. If you test the board, you may need to modify and test the board repeatedly many times to get a relatively satisfactory circuit wiring path, which results in a long design cycle for the entire circuit R&D and low R&D test efficiency.

[0041] To this end, the present invention proposes a chip performance test fixture. In one embodiment of the present invention, reference Figure 1 , chip performance test fixtures include:

[0042] An electric control board 10, on which a signal test circuit is provided;

[0043] A signal input terminal 20, which is disposed on the electric control board 10, and is used to connect to the pin of the chip and receive the test signal output by the chip;

[0044] A signal output terminal 30, which is disposed on the electric control board 10, and is used to connect to the access interface;

[0045] A plurality of test terminals 40; the test terminals 40 are used to access the test device, and the plurality of test terminals 40 are electrically connected to the signal test circuit;

[0046] The signal test circuit includes a first parallel mounting position 11, a second parallel mounting position 12, a plurality of strobe mounting positions 13, a series mounting position 14, a first signal line 15, a plurality of second signal lines 16 and a third signal line 17; a first end of the first signal line 15 and a first end of the first parallel mounting position 11 are electrically connected to the signal input terminal respectively, a second end of the first signal line 15 is connected to the first ends of the plurality of strobe mounting positions 13, second ends of the plurality of strobe mounting positions 13 are respectively connected to the first ends of the plurality of second signal lines 16 in a one-to-one correspondence, second ends of the plurality of second signal lines 16 are all connected to the first end of the series mounting position 14, a first end of the third signal line 17 is connected to the second end of the series mounting position 14, a second end of the third signal line 17 is connected to the signal output terminal 30, and a second end of the first parallel mounting position 11 and a second end of the second parallel mounting position 12 are both grounded;

[0047] Among them, the first parallel mounting position 11, the second parallel mounting position 12, and the series mounting position 14 are all used to connect to the connecting elements; the multiple second signal lines 16 have different lengths, and the multiple selection mounting positions 13 are used to select the second signal line 16 through which the test signal passes when connecting a connecting element.

[0048] In this embodiment, the electric control board 10 can be implemented by a circuit substrate made of materials such as a DBC board, a PCB board, a semi-fiberglass board, a fiberglass board, etc., and can also be implemented by any one of an aluminum substrate, an aluminum alloy substrate, a copper substrate or a copper alloy substrate.

[0049] In the present embodiment, optionally, the signal input terminal 20 can be a pad, and the R&D tester electrically connects the signal pin on the chip to the pad by means of a flying wire. It is understandable that the length of the flying wire can be selected to be as short and thick as possible to prevent the flying wire from affecting the signal output by the chip. In addition, the signal input terminal 20 can also be an interface, such as a VGA / HDMI / USB / LAN interface, so that the pin of the chip on the development board is connected to the interface on the corresponding electric control board 10 through a connecting wire. For example, the chip pin on the development board is connected to an interface on the development board. The R&D tester can connect the interface at one end of the connecting wire and the corresponding interface on the electric control board 10 at the other end to achieve electrical connection between the two. It is understandable that the R&D personnel will also calculate the parameters of the connecting wire, such as impedance, in the total impedance parameters.

[0050] In this embodiment, it is necessary to understand that in actual circuit design, the chip signal will be connected in series or in parallel with one or more connection elements on the transmission line to play a corresponding role, such as filtering, reducing signal oscillations, changing signal timing, protecting the chip signal output pins and other functions.

[0051] To this end, in this embodiment, the R&D test personnel can connect suitable connection elements, such as resistors, capacitors, inductors, diodes, TVS tubes, ESD diodes and other devices, to the first parallel mounting position 11, the second parallel mounting position 12, the multiple strobe mounting positions 13, and the series mounting position 14 according to the needs, so as to test the influence of different devices on the signal output by the chip. At the same time, it can be understood that the number of the first parallel mounting position 11, the second parallel mounting position 12, and the series mounting position 14 can be multiple, multiple first parallel mounting positions 11 are electrically connected to the first signal line 15, multiple second parallel mounting positions 12 are electrically connected to the third signal line 17, and multiple series mounting positions 12 are connected in series with each other. Similarly, the strobe mounting position electrically connected to each second signal line 16 can also be composed of multiple series mounting positions. In this way, it is possible to simultaneously connect multiple different types of devices to multiple parallel mounting positions, install different types of devices on multiple series mounting positions, and connect different types of devices to multiple series mounting positions in the strobe mounting position, so as to better meet the needs of actual testing.

[0052] Specifically, the R&D test personnel may only install conventional devices connected in parallel to the signal, such as diodes, TVS tubes or ESD diodes, capacitors, etc., on the first parallel mounting position 11, and enable the chip to start outputting a preset test signal.

[0053] In this embodiment, multiple test terminals 40 can be preset to be electrically connected to any position on the signal test circuit according to actual needs, so that after connecting to the test device, the signal at the electrical connection between the test terminal 40 and the signal test circuit can be tested.

[0054] Specifically, in this embodiment, the test end 40 includes a first test end 41 and a second test end 42 as an example. Figure 2 , the multiple test terminals 40 include a first test terminal 41 and a second test terminal 42, the first test terminal 41 is electrically connected to the signal input terminal, the second test terminal 42 is connected to the signal output terminal 30, the first test terminal 41 is used to access a test device such as an oscilloscope, and the R&D test personnel can read the signal of the first test terminal 41 through the oscilloscope. It can be understood that the connection point between the first test terminal 41 and the first signal line 15 is set at a position between the connection point between the first signal line 15 and the first end of the first parallel mounting position 11 and the second end of the first signal line 15. In this way, what the oscilloscope receives is the output signal of the chip output through the connecting element on the first parallel mounting position 11, and then compares it with the preset test signal, so as to judge the influence of the device on the first parallel mounting position 11 on the chip output signal, that is, the influence on the signal integrity, so as to select a parallel device with more suitable parameters or models.

[0055] It should be understood that, since the size of each PCB board is different, the integrity of the signal output by the chip will also be affected by the length of the path of its signal transmission during the PCB Layout process. To this end, in this embodiment, the R&D tester can also change the length of the second signal line 16 connected to the entire signal line by installing a connecting element on one of the multiple strobe installation positions 13, thereby changing the length of the signal transmission path.

[0056] In this embodiment, it should be understood that the plurality of second signal lines 16 may not only have different lengths, but also may have different routing shapes, such as different routing angles, serpentine lines, etc. The plurality of second signal lines 16 may be preset on the electric control board 10 by R&D personnel according to actual daily needs.

[0057] Specifically, the R&D test personnel can set the required connection elements on the first parallel mounting position 11, the series mounting position 14, and the second parallel mounting position 12 according to the requirements of the circuit design. Then, according to the line path in the drawn PCB Layout, select the appropriate second signal line 16, and set the connection element on the corresponding gate mounting position 13. At this time, the R&D test personnel control the chip to start outputting the preset test signal. The R&D test personnel will read the signal of the second test terminal 42 through the oscilloscope and compare it with the preset test signal or the target signal (it should be understood that in actual projects, sometimes it is necessary to process the signal output by the chip through the device on the line to obtain the target signal). If the error obtained by the comparison is greater than the acceptable error range, the R&D test personnel will remove the connection element on the original gate mounting position 13 and place it on another more suitable gate mounting position 13 corresponding to the second signal line 16 (it can be understood that because the PCB size is known, the total length of the signal line can only be selected within a certain range), and repeat the above test until the error obtained is within the acceptable error range. Then, the total length of the signal line and the device parameters of the electrical connection of the signal line are used as reference parameters for adjusting the line path in the PCB Layout being drawn. In this way, R&D testers can use the chip performance test fixture of the present invention to estimate the signal performance of the signals output by different chips in the actual project in advance during project development, so as to provide a design reference for the drawing of PCB Layout, thereby reducing the design risk in the actual project, reducing the number of repeated board tests, and further improving the R&D test efficiency of circuit board wiring, reducing the error rate of chip selection, shortening the R&D design cycle, and reducing R&D costs.

[0058] In this embodiment, the signal output terminal 30 can be an interface pad, and the R&D personnel can weld and connect the corresponding interface, such as VGA, HDMI, USB, LAN interface, etc., so as to test the influence of the output interface on the chip output signal. Optionally, multiple groups of signal test circuits can be set on the same electronic control board, and the interface types of the interface pads in each signal test circuit are inconsistent, so that the R&D personnel can weld and connect different types of interfaces, so as to test the influence of different output interfaces on the chip output signal.

[0059] Specifically, refer to Fig. 9 Taking the example of installing a diode D1 in the first parallel mounting position 11, installing a resistor R1 in one of the selection mounting positions 13, installing an inductor L1 in the series mounting position 14, installing a capacitor C1 in the second parallel mounting position 12, and connecting the signal output terminal 30 to the USB interface, the R&D personnel can connect an oscilloscope to the first test terminal 41 to determine the influence of the diode on the signal output by the chip under test, and select a signal transmission path of appropriate length according to actual needs, and simulate the impedance value of the signal transmission path by setting the corresponding parameters of resistance, capacitance and inductance, and finally determine the parameters of the current transmission path and the impedance of each device on the path and the influence on the output signal of the chip under test during the transmission to the USB interface by connecting an oscilloscope to the second test terminal 42.

[0060] In another embodiment, it is understandable that the chip performance test fixture of the present invention can also be used to test the EMC performance of the chip pin. After the R&D test personnel connect the signal input terminal 20 to the chip pin (without setting a connecting element on any installation position), they can connect the first test terminal 41 to the electrostatic gun, and then release static electricity to the chip pin through the electrostatic gun. Subsequently, the chip pin is controlled to output a preset test signal, and the actual output signal is collected at the first test terminal 41 through an oscilloscope, and compared with the preset test signal. If the error is within the preset error value, it means that the EMC performance of the chip pin meets the requirements and is not broken down by static electricity. If the error exceeds the preset error value, it means that the EMC performance of the chip pin does not meet the requirements. Among them, the static voltage output by the electrostatic gun can be changed according to the needs of the R&D personnel. In this way, the performance of the newly purchased chip can be tested in advance.

[0061] The present invention provides a chip performance test fixture, which includes an electric control board 10, a signal input terminal 20, a signal output terminal 30, and a plurality of test terminals 40. The electric control board 10 is provided with a signal test circuit, including a first parallel mounting position 11, a second parallel mounting position 12, a plurality of strobe mounting positions 13, a series mounting position 14, a first signal line 15, a plurality of second signal lines 16, and a third signal line 17. The signal input terminal 20 is used to connect to the pin of the chip and access the test signal output by the chip, the signal output terminal 30 is used to access the interface, the test terminal 40 is used to access the test device, the first parallel mounting position 11, the second parallel mounting position 12, and the series mounting position 14 are all used to access the connection element; the plurality of second signal lines 16 have different lengths, and the plurality of strobe mounting positions 13 are used to select the second signal line 16 through which the test signal passes when accessing a connection element. In this way, R&D testers can set different connection components at the installation position during project development to estimate the signal performance of signals output by different simulated chips in actual projects in advance, and provide design references for drawing PCB Layout, thereby reducing design risks in actual projects, reducing the number of repeated board making, and further improving the R&D test efficiency of circuit board wiring, shortening the R&D design cycle, and reducing R&D costs. At the same time, the performance of newly purchased chips can also be tested to reduce the error rate of chip selection.

[0062] It should be understood that the signals output by some chips are differential signals, that is, the chip needs to output differential signals from two signal pins at the same time.

[0063] For this purpose, refer to Figure 3 In one embodiment of the present invention, a differential signal test area is provided on the electric control board 10, and a plurality of completely identical signal test circuits are provided in the differential signal test area.

[0064] In this embodiment, the signal input terminals 20 of the two signal test circuits are used to be connected to the two differential pins of the chip respectively. R&D test personnel can select the connection elements to be set on the first parallel mounting position 11, the second parallel mounting position 12, the strobe mounting position 13 and the series mounting position 14 according to their needs, and connect the corresponding test equipment through the first test terminal 41 to test the integrity of the signal output by the chip.

[0065] Optionally, in this embodiment, the R&D test personnel may install the connecting element only on the first parallel mounting position 11, without installing any components on other mounting positions, and then use an oscilloscope to read the signal at the first test end 41 of the two groups of signal test circuits to compare with the theoretical signal, so as to determine the influence of the connecting element on the first parallel mounting position 11 on a group of differential signals output by the chip.

[0066] Optionally, in this embodiment, the R&D test personnel can also install connecting elements on different gate installation positions 13 so that the signal of the second test terminal 42 can be detected to determine the signal integrity of the differential signal output by the chip after being transmitted through the second signal line 16 of different lengths and shapes. It should be understood that, since the differential signal is used in this embodiment, the connecting elements on the installation positions of the two groups of signal test circuits need to be exactly the same and the selected gate installation positions 13 also need to be exactly the same. At the same time, since it is a differential signal, the signal output terminal 30 can be connected to the two differential ends of the same interface. The R&D personnel can read the signals at the second test terminals 42 of the two groups of signal test circuits through an oscilloscope to compare with the theoretical signal, so as to determine the impact on the integrity of the differential signal under the current analog circuit situation.

[0067] Through the above settings, it is possible to simulate the test of the impact of different routing methods electrically connected to the differential signal pins of the chip in actual applications, as well as different devices connected on the routing or different interfaces connected on the differential signal integrity, so as to provide a design reference for the drawing of PCB Layout, thereby reducing the design risk in actual projects, reducing the number of repeated board making, and further improving the R&D test efficiency of circuit board wiring, shortening the R&D design cycle, and reducing the chip selection error rate and R&D cost.

[0068] refer to Figure 4 and Figure 7 In one embodiment of the present invention, the electric control board 10 has a first wiring layer and a second wiring layer, a first high-speed signal test area is arranged on the first wiring layer of the electric control board 10, a grounding copper is arranged around the first high-speed signal test area of ​​the electric control board 10, and a signal test line is arranged in the first high-speed signal test area; a grounding copper is arranged on the second wiring layer of the electric control board 10 relative to the first high-speed signal test area;

[0069] The first signal line 15 , the plurality of second signal lines 16 and the third signal line 17 in the signal test circuit in the first high-speed signal test area are all microstrip lines.

[0070] It should be understood that the signals output by some chips are high-speed signals. In order to meet the transmission requirements of high-speed signals, the signal lines of high-speed signals are generally set to microstrip lines or strip states. In this embodiment, microstrip lines are taken as an example.

[0071] It can be understood that in this embodiment, in order to meet the routing requirements of the microstrip line, a first high-speed signal test area surrounded by ground copper can be designed on the first wiring layer of the electric control board 10, and at the same time, the second wiring layer of the electric control board 10 is covered with ground copper relative to the first high-speed signal test area. Specifically, refer to Figure 7And formula (1) (microstrip line impedance calculation formula), where W is the microstrip line width, T is the microstrip line thickness, H is the distance from the microstrip line to the second wiring layer, Z is the impedance, and Er is the dielectric constant of the PCB material.

[0072] Formula (1)Z={87 / [sqrt(Er+1.41)]}ln[5.98h / (0.8w+t)]

[0073] According to the above formula, the R&D personnel can set up multiple groups of signal test lines with different impedances in the first high-speed signal test area. In this way, the R&D personnel can configure the connection elements to access different strobe installation positions 13 according to the test method in the above embodiment, and realize the influence of the microstrip lines with different impedances and different lengths electrically connected to the signal pins of the chip on the signal integrity of the simulation test. In this way, there is no need to test the high-speed signal output by the chip by repeatedly beating the board. It is possible to directly perform a pre-simulation by using the chip performance test fixture in this embodiment, so as to find the wiring parameters that are more suitable for the current actual project requirements, and further improve the R&D test efficiency of the circuit board wiring. At the same time, it is also possible to perform performance testing on newly purchased chip samples under the conditions of different impedances and different lengths of routing.

[0074] Through the above tests, it is possible to simulate the impact of different impedances electrically connected to the signal pins of the chip in actual applications, microstrip lines of different lengths, and different devices electrically connected to the microstrip lines on signal integrity, so as to provide a design reference for the drawing of PCB Layout, thereby reducing the design risk in actual projects, reducing the number of repeated board making, and further improving the R&D test efficiency of circuit board wiring, shortening the R&D design cycle, and reducing the chip selection error rate and R&D costs.

[0075] Similarly, reference Figure 7 , taking the signal line as a strip line as an example for explanation, in one embodiment of the present invention, the electric control board 10 is a multi-layer board, and the electric control board 10 also has an inter-board wiring layer;

[0076] A second high-speed signal test area is also provided on the first wiring layer of the electric control board 10, and a signal test circuit is provided in the second high-speed signal test area; a grounding copper is provided on the second wiring layer of the electric control board 10 relative to the second high-speed signal test area;

[0077] Wherein, a grounding copper cladding is arranged in the second high-speed signal test area;

[0078] The first parallel mounting position 11, the second parallel mounting position 12, the series mounting position 14, and the plurality of strobe mounting positions 13 in the signal test circuit in the second high-speed signal test area are all arranged on the first wiring layer of the electric control board 10;

[0079] The first signal line 15 , the plurality of second signal lines 16 and the third signal line 17 in the signal test circuit in the second high-speed signal test area are all strip lines and are all arranged in the inter-board wiring layer.

[0080] In this embodiment, in order to meet the routing requirements of the strip line, the electric control board 10 needs to select a multi-layer board, such as a 4-layer board, a 6-layer board, etc. A grounding copper is laid in the second high-speed test area on the first wiring layer of the electric control board 10, and a grounding copper is laid in the second high-speed test area on the second wiring layer of the electric control board 10, and the first signal line 15, the plurality of second signal lines 16 and the third signal line 17 are all arranged in the middle of the circuit board. It can be understood that, referring to Figure 7 , W is the stripline width, T is the stripline thickness, H is the distance from the stripline to the first wiring layer or the second wiring layer, Er is the dielectric constant of the PCB material. R&D personnel can set multiple striplines with different impedances according to the following formula (2) (stripline impedance calculation formula), Z is the impedance, and Er is the dielectric constant of the PCB material.

[0081] Formula (2)Z=[60 / sqrt(Er)]ln{4H / [0.67π(0.8W+T)]}

[0082] In this embodiment, the R&D personnel can select different second signal lines 16 according to the needs of the actual project through the test method described in the above embodiment to change the impedance of the overall strip line, thereby realizing the influence of the strip line connected to the chip signal pin in the actual project on the integrity of the signal output by the chip under different impedances.

[0083] Through the above tests, it is possible to simulate the impact of different impedances electrically connected to the signal pins of the chip in actual applications, strip lines of different lengths, and different devices electrically connected to the strip lines on signal integrity, so as to provide a design reference for the drawing of PCB Layout, thereby reducing the design risk in actual projects, reducing the number of repeated board making, and further improving the R&D test efficiency of circuit board wiring, shortening the R&D design cycle, and reducing the chip selection error rate and R&D costs.

[0084] Optionally, refer to Figure 3 In another embodiment, the number of signal test lines in the first high-speed signal test area is multiple, and the signal test lines in the multiple first high-speed signal test areas are completely the same.

[0085] In this embodiment, the high-speed signal output by the signal pin of the chip can also be a differential signal. To this end, a plurality of identical test circuits are also provided on the electric control board 10. Among them, the R&D personnel will place a plurality of identical connection elements (such as 0 ohm resistors) in the series mounting position 14 and the same selection mounting position 13 in the two groups of signal test circuits, so that the total microstrip line impedance in the two groups of signal test circuits is the same. At this time, the two signal input terminals 20 are simultaneously connected to the differential signal output terminals 30 corresponding to the chip, and the differential signal output by the chip is connected, and then the same test method for the differential signal as in the above embodiment is adopted for testing. Thereby testing the influence of microstrip lines with different impedances on the integrity of the differential signal.

[0086] Optionally, in another embodiment, the second high-speed signal test area has a plurality of signal test lines, and the plurality of signal test lines in the second high-speed signal test area are completely the same.

[0087] It should be understood that, similar to the above-mentioned microstrip line, some high-speed signals are also differential signals, so two groups of completely identical signal test lines can be set in the second high-speed signal test area. At this time, the R&D personnel will place multiple identical connection elements (such as 0 ohm resistors) in the two groups of signal test lines in the series installation position 14 and the same selection installation position 13, so that the total strip line impedance in the two groups of signal test lines is the same. At this time, the two signal input terminals 20 are simultaneously connected to the differential signal output terminals 30 corresponding to the chip to access the differential signal output by the chip, and then the same test method for the differential signal in the above embodiment is adopted for testing. In this way, the influence of strip lines with different impedances on the integrity of the differential signal is tested.

[0088] refer to Figure 5 , the routing types of the first signal line 15 , the second signal line 16 and the third signal line 17 are different.

[0089] It is important to understand that in actual applications, due to the size limitations of the circuit board or the size limitations of the device, some lines may not be able to maintain the same routing type when routing. For example, in existing PCB Layout designs, for high-speed signals, R&D personnel generally choose to use stripline routing to transmit high-speed signals. However, in actual projects, the signal lines connected to the chip signal pins may not all be striplines due to the influence of PCB size and device size. Some of them may be microstrip lines, and the microstrip lines and striplines are connected through vias.

[0090] In the present embodiment, a plurality of signal test circuits are also provided on the circuit board, and the routing types of the various signal lines in each signal test circuit are different. It is understandable that the type of routing can be set by the research and development personnel according to the needs of the actual project to set a combination of multiple groups of different routing types. The research and development personnel can adjust the impedance of the entire routing by setting different components on the gating installation position 13 or the series installation position 14, such as resistors, inductors, capacitors, etc., so that it is the same as the total impedance theoretical calculation value of the routing planned in the actual project, that is, the total impedance theoretical calculation value of the routing planned during circuit wiring is the same. Subsequently, the integrity of the signal output by the chip is tested by the test method in the above embodiment, thereby simulating the influence of the signal line connected to the chip signal pin on the integrity of the signal output by the chip under different routing types in the actual project.

[0091] Through the above settings, it is possible to simulate the impact of signal lines connected to chip signal pins on the integrity of chip output signals under different routing types in actual projects, further improve the R&D test efficiency of circuit board wiring, shorten the R&D design cycle, and reduce chip selection error rate and R&D costs.

[0092] refer to Figure 6 , the line widths of the first signal line 15 , the second signal line 16 and the third signal line 17 are different.

[0093] It should be understood that in actual applications, due to the size limitations of the circuit board or the size limitations of the device, some lines cannot always maintain the same routing width when routing. For example, if the current board size is small and there are many devices around the chip, the signal line connected to the chip signal pin may need to pass through the gap between the peripheral devices, so the routing width will be relatively narrow, and the routing width will be expanded after passing through the peripheral devices, or the wiring in some areas of the circuit board is relatively concentrated, resulting in the routing width of the line passing through this area being relatively narrow.

[0094] In this embodiment, a plurality of signal test circuits are also provided on the circuit board, and the line widths of the signal lines in each signal test circuit are different, and the line width parameters can be set by the R&D personnel according to the conventional requirements of the actual project. The R&D personnel can test the integrity of the signal output by the chip through the test method in the above embodiment, thereby simulating the influence of the signal line connected to the chip signal pin on the integrity of the signal output by the chip under different routing widths in the actual project.

[0095] Through the above settings, it is possible to simulate the impact of signal lines connected to chip signal pins on signal integrity under different routing widths in actual projects, further improve the R&D test efficiency of circuit board wiring, shorten the R&D design cycle, and reduce the chip selection error rate and R&D costs.

[0096] The above are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A chip performance test fixture, characterized in that: The chip performance test fixture includes: An electric control board, wherein a signal test circuit is provided on the electric control board; A signal input terminal, which is arranged on the electronic control board and is used to connect to the pin of the chip and receive the test signal output by the chip; A signal output terminal, the signal output terminal is arranged on the electric control board, and the signal output terminal is used to connect to the access interface; A plurality of test terminals; the test terminals are used to access a test device, and the plurality of test terminals are electrically connected to the signal test circuit; The signal test circuit includes a first parallel mounting position, a second parallel mounting position, a plurality of strobe mounting positions, a series mounting position, a first signal line, a plurality of second signal lines and a third signal line; a first end of the first signal line and a first end of the first parallel mounting position are respectively electrically connected to the signal input end, a second end of the first signal line is connected to the first ends of the plurality of strobe mounting positions, second ends of the plurality of strobe mounting positions are respectively connected to the first ends of the plurality of second signal lines in a one-to-one correspondence, second ends of the plurality of second signal lines are all connected to the first end of the series mounting position, a first end of the third signal line is connected to the second end of the series mounting position, a second end of the third signal line is connected to the signal output end, and a second end of the first parallel mounting position and a second end of the second parallel mounting position are both grounded; Among them, the first parallel mounting position, the second parallel mounting position, and the series mounting position are all used to connect to the connecting element; the lengths of multiple second signal lines are different, and multiple selection mounting positions are used to select the second signal line through which the test signal passes when connecting to a connecting element.

2. The chip performance test fixture as claimed in claim 1, characterized in that: The plurality of test terminals include a first test terminal and a second test terminal, wherein the first test terminal is electrically connected to the signal input terminal, and the second test terminal is connected to the signal output terminal.

3. The chip performance test fixture as claimed in claim 2, characterized in that: The electric control board is provided with a differential signal test area, and a plurality of completely identical signal test circuits are provided in the differential signal test area.

4. The chip performance test fixture as claimed in claim 2, characterized in that: The electric control board comprises a first wiring layer and a second wiring layer, a first high-speed signal test area is arranged on the first wiring layer of the electric control board, a grounding copper is arranged around the first high-speed signal test area of ​​the electric control board, and the signal test circuit is arranged in the first high-speed signal test area; a grounding copper is arranged on the second wiring layer of the electric control board relative to the first high-speed signal test area; Wherein, the first signal line, the plurality of second signal lines and the third signal line in the signal test circuit in the first high-speed signal test area are all microstrip lines.

5. The chip performance test fixture as claimed in claim 4, characterized in that: The electric control board is a multi-layer board, and the electric control board also has an inter-board wiring layer; A second high-speed signal test area is also provided on the first wiring layer of the electric control board, and the signal test circuit is provided in the second high-speed signal test area; a grounding copper is provided on the second wiring layer of the electric control board relative to the second high-speed signal test area; Wherein, a grounding copper clad is provided in the second high-speed signal test area; The first parallel mounting position, the second parallel mounting position, the series mounting position, and the plurality of strobe mounting positions in the signal test circuit in the second high-speed signal test area are all arranged on the first wiring layer of the electric control board; The first signal line, the plurality of second signal lines and the third signal line in the signal test circuit in the second high-speed signal test area are all strip lines and are all arranged in the inter-board wiring layer.

6. The chip performance test fixture as claimed in claim 5, characterized in that: The first high-speed signal test area has a plurality of signal test circuits, and the plurality of signal test circuits in the first high-speed signal test area are completely identical; The second high-speed signal test area has a plurality of signal test circuits, and the plurality of signal test circuits in the second high-speed signal test area are completely identical.

7. The chip performance test fixture as claimed in claim 5, characterized in that: The first signal line, the second signal line and the third signal line have different routing types.

8. The chip performance test fixture as claimed in claim 1, characterized in that: The first signal line, the second signal line, and the third signal line have different line widths.

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