Semiconductor structure and its preparation method

Abstract

This disclosure provides a semiconductor structure and its fabrication method. The fabrication method utilizes a supplementary layer to fill the gaps between the mask layer and the capping layer, avoiding the formation of patterns corresponding to the gaps in the initial pattern. Therefore, after pattern transfer based on the initial pattern, it can avoid the formation of pseudo-capacitor holes in the substrate, preventing the edge pattern of the array region from deviating from the predetermined design, thereby improving the yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for preparing the same. Background Technology

[0002] In semiconductor structure manufacturing technology, photoresist and mask layers are usually used in combination with photolithography and etching processes to form the desired pattern. However, due to the limitations of photolithography, the desired pattern formed may deviate, affecting the yield of semiconductor structures.

[0003] Taking the manufacturing of Dynamic Random Access Memory (DRAM) as an example, in the process of forming capacitors in DRAM, during the pattern transfer process using Self-Aligned Double Patterning (SADP), due to the limitations of photolithography, dummy holes are generated in the corners of the array area. This causes the edge pattern of the array area to deviate from the predetermined design, affecting the performance of DRAM and thus affecting the yield of DRAM. Summary of the Invention

[0004] The technical problem to be solved by this disclosure is to provide a semiconductor structure and a method for fabricating the same, which can avoid the formation of pseudo-capacitor holes in the substrate.

[0005] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate being divided into an array region and a peripheral region, the substrate including a substrate and a first pattern layer disposed on the substrate, the first pattern layer including first sacrificial strips and first spacer strips spaced apart along a first direction; forming a second pattern layer on the first pattern layer, the second pattern layer including second sacrificial strips spaced apart along a second direction, the first direction and the second direction forming an acute angle; forming a capping layer, the capping layer covering the surface of the second sacrificial strips and the exposed surface of the first pattern layer; forming a mask layer, the mask layer covering the surface of the capping layer located in the peripheral region; forming a supplementary layer, at the boundary between the array region and the peripheral region, the supplementary layer filling the gap between the sidewall of the mask layer and the adjacent capping layer; using the mask layer as a mask, removing a portion of the capping layer, retaining the capping layer located on the sidewall of the second sacrificial strip, forming a second spacer strip; removing the second sacrificial strip, the mask layer, and the first sacrificial strip below the second sacrificial strip, forming an initial pattern defined by the first spacer strip and the second spacer strip in the array region; and transferring the initial pattern into the substrate to form a target pattern.

[0006] In some embodiments, the step of forming a supplementary layer further includes: forming a supplementary material layer that covers the surface of the cover layer and the mask layer; removing a portion of the supplementary material layer, leaving a supplementary material layer that fills the gaps between the side of the mask layer and the adjacent cover layer as the supplementary layer.

[0007] In some embodiments, the step of removing a portion of the supplementary material layer and the step of removing a portion of the cover layer are performed in the same etching step.

[0008] In some embodiments, the supplementary layer is made of the same material as the cover layer.

[0009] In some embodiments, the supplementary layer is formed using an atomic layer deposition process.

[0010] In some embodiments, during the step of forming the second spacer, at the boundary between the array region and the peripheral region, the covering layer of the sidewall of the second sacrificial strip and the supplementary layer together serve as the second spacer.

[0011] In some embodiments, the step of forming the mask layer further includes: forming a mask material layer that covers the overlay layer and fills the gaps between the second sacrificial strips; removing the mask material layer of the array region to form the mask layer.

[0012] In some embodiments, the substrate further includes an isolation layer disposed between the substrate and the first pattern layer, and the step of transferring the initial pattern into the substrate to form the target pattern further includes: using the first spacer and the second spacer as masks, transferring the initial pattern into the isolation layer to form an intermediate pattern; and using the isolation layer as a mask, transferring the intermediate pattern into the substrate.

[0013] In some embodiments, the substrate further includes a first anti-reflective layer disposed between the isolation layer and the first pattern layer, wherein the first anti-reflective layer is also patterned during the step of transferring the initial pattern into the isolation layer using the first spacer and the second spacer as masks to form an intermediate pattern.

[0014] In some embodiments, the method of forming the first patterned layer on the substrate includes the following steps: forming an initial sacrificial strip extending along the first direction on the substrate; forming a first spacer strip on the sidewall of the initial sacrificial strip; removing the initial sacrificial strip; and filling the spacers between the first spacers to form the first sacrificial strip.

[0015] In some embodiments, a second anti-reflective layer is further formed on the first pattern layer, the second pattern layer being formed on the second anti-reflective layer, and after removing the second sacrificial strip, the method further includes the step of removing the second anti-reflective layer below the second sacrificial strip.

[0016] In some embodiments, the angle between the first direction and the second direction is 20 degrees to 40 degrees.

[0017] In some embodiments, the boundary of the mask layer adjacent to the array region is parallel to the second direction.

[0018] In some embodiments, the step of forming the target pattern is followed by a step of removing the first spacer and the second spacer.

[0019] This disclosure also provides a semiconductor structure comprising: a substrate divided into an array region and a peripheral region, the substrate including a substrate, a first pattern layer disposed on the substrate, the first pattern layer including first sacrificial strips and first spacer strips spaced apart along a first direction; a second pattern layer disposed on the first pattern layer, the second pattern layer including second sacrificial strips spaced apart along a second direction, the first direction and the second direction forming an acute angle; a cover layer covering the surface of the second sacrificial strips and the exposed surface of the first pattern layer; a mask layer covering the surface of the cover layer located in the peripheral region; and a supplementary layer at the junction of the array region and the peripheral region, the supplementary layer filling the gap between the side of the mask layer and the adjacent cover layer.

[0020] In some embodiments, the material of the supplementary layer is the same as the material of the cover layer.

[0021] In some embodiments, the substrate further includes an isolation layer disposed between the substrate and the first patterned layer.

[0022] In some embodiments, the substrate further includes a first anti-reflective layer disposed between the isolation layer and the first patterned layer.

[0023] In some embodiments, a second anti-reflective layer is further provided between the first pattern layer and the second pattern layer, the cover layer covering the surface of the second sacrificial strip and the exposed surface of the second anti-reflective layer.

[0024] The above technical solution utilizes a supplementary layer to fill the gap between the mask layer and the cover layer, avoiding the formation of a pattern corresponding to the gap in the initial pattern. Therefore, after the pattern transfer is based on the initial pattern, it can avoid the formation of pseudo-capacitor holes in the substrate, prevent the edge pattern of the array region from deviating from the predetermined design, and thus improve the yield of the semiconductor structure.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1A This is a schematic cross-sectional view of the semiconductor structure corresponding to the main process for forming capacitor holes provided in the first embodiment of this disclosure;

[0028] Figure 1B This is a top view schematic diagram of the semiconductor structure after forming a capacitor hole according to the first embodiment of this disclosure;

[0029] Figure 2 This is a schematic diagram of the steps in the method for fabricating a semiconductor structure provided in the second embodiment of this disclosure;

[0030] Figures 3A to 3O This is a schematic diagram of the semiconductor structure formed by the main steps of the preparation method provided in the second embodiment of this disclosure. Detailed Implementation

[0031] The specific embodiments of the semiconductor structure and its fabrication method provided in this disclosure are described in detail below with reference to the accompanying drawings. The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the scope of this disclosure or its application or use. That is, those skilled in the art will understand that they merely illustrate exemplary methods that can be used in practice, and are not exhaustive. Furthermore, unless otherwise specifically stated, the relative arrangement of components and steps set forth in these embodiments does not limit the scope of this disclosure.

[0032] In the process of forming capacitors in dynamic random access memory, self-aligned double patterning (SADP) is used for pattern transfer to form capacitor holes. Figure 1A This is a schematic cross-sectional view of the semiconductor structure corresponding to the main process for forming capacitor holes provided in the first embodiment of this disclosure. Please refer to [link / reference]. Figure 1AThe semiconductor structure is divided into an array region AA and a peripheral region PA. The semiconductor structure includes a substrate 101, a first patterned layer 110 disposed on the substrate 101, a second patterned layer 120 disposed on the first patterned layer 110, a capping layer 130, and a mask layer 140. The first patterned layer 110 includes a first patterned layer D (e.g., along a first direction D). Figure 1B (As shown) First sacrificial strips 111 and first spacer strips 112 are arranged at intervals. The second pattern layer 120 includes first sacrificial strips 111 and first spacer strips 112 arranged along a second direction E (e.g., Figure 1B The second sacrificial strips 121 are spaced apart (as shown). The cover layer 130 covers the surface of the second sacrificial strips 121 and the exposed surface of the first pattern layer 110. The mask layer 140 covers the surface of the cover layer 130 located in the peripheral region PA.

[0033] Figure 1B This is a top view schematic diagram of the semiconductor structure after forming a capacitor hole according to the first embodiment of this disclosure. Please refer to [link / reference]. Figure 1B ,exist Figure 1A Based on the semiconductor structure shown, the pattern is transferred onto the substrate 101 to form a capacitor hole 102.

[0034] However, the inventors discovered that pseudo-capacitor holes 103 form at the edge of the array region. The presence of these pseudo-capacitor holes causes the edge pattern of the array region AA to deviate from the intended design, affecting the performance of the semiconductor structure. Through in-depth research, the inventors discovered that the cause of these pseudo-capacitor holes is that... Figure 1A As shown, according to the layout design, the mask layer 140 should be in contact with the adjacent cover layer 130. However, in the actual process, due to the limitations of the photolithography process, the mask layer 140 and the adjacent cover layer 130 are not in contact, but have a gap 141. In the subsequent pattern transfer process, the pattern at the gap 141 is also transferred, thereby forming a pseudo-capacitor hole 103 in the substrate 101.

[0035] To address the aforementioned technical problems, this disclosure also proposes a novel method for fabricating semiconductor structures, which can avoid the formation of pseudo-capacitor holes in the substrate, prevent the edge pattern of the array region from deviating from the predetermined design, and thereby improve the yield of semiconductor structures.

[0036] Figure 2 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor structure according to the second embodiment of this disclosure. Please refer to [link / reference]. Figure 2The preparation method includes the following steps: Step S20, providing a substrate, the substrate being divided into an array region and a peripheral region, the substrate including a substrate and a first pattern layer disposed on the substrate, the first pattern layer including first sacrificial strips and first spacer strips spaced apart along a first direction; Step S21, forming a second pattern layer on the first pattern layer, the second pattern layer including second sacrificial strips spaced apart along a second direction, the first direction and the second direction forming an acute angle; Step S22, forming a cover layer, the cover layer 3 covering the surface of the second sacrificial strips and the exposed surface of the first pattern layer; Step S23, forming a mask layer, the mask layer covering... Step S24: Cover the surface of the cover layer located in the peripheral region; Step S25: Form a supplementary layer at the junction of the array region and the peripheral region, the supplementary layer filling the gap between the side of the mask layer and the adjacent cover layer; Step S26: Using the mask layer as a mask, remove part of the cover layer, retaining the cover layer located on the sidewall of the second sacrificial strip, forming a second spacer strip; Step S27: Remove the second sacrificial strip, the mask layer, and the first sacrificial strip below the second sacrificial strip, forming an initial pattern defined by the first spacer strip and the second spacer strip in the array region; Step S28: Transfer the initial pattern to the substrate to form a target pattern.

[0037] Figures 3A to 3O This is a schematic diagram of the semiconductor structure formed by the main steps of the fabrication method provided in the second embodiment of this disclosure. It should be noted that this disclosure mainly describes the fabrication method at the junction of the array region AA and the peripheral region PA, and the corresponding figures only show the structural changes at the junction of the array region AA and the peripheral region PA, so as to facilitate those skilled in the art to understand the implementation of this solution.

[0038] Please refer to step S20. Figure 3D and Figure 3E ,in, Figure 3D This is a top view. Figure 3E For along Figure 3D A cross-sectional schematic diagram of the CC line is provided, and a substrate 300 is provided. The substrate 300 is divided into an array region AA and a peripheral region PA. The substrate 300 includes a substrate 301 and a first pattern layer 310 placed on the substrate 301. The first pattern layer 310 includes a first sacrificial strip 311 and a first spacer strip 312 arranged at intervals along a first direction D.

[0039] The array region AA is used to form a capacitor array, and the peripheral region PA can be formed with conductive structures such as transistors for electrical connection with conductive contact plugs formed in subsequent processes.

[0040] The substrate 301 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 301 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 301 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 301 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or pn junction diodes, may also be formed in the substrate 301. In this embodiment, the substrate 301 is a silicon substrate, which also includes other device structures, such as bit line structures and transistor structures, but these are not shown as they are not relevant to this invention.

[0041] This embodiment provides a method for forming the first pattern layer 310. The method includes the following steps:

[0042] Please see Figure 3A A direction D (e.g., ...) is formed on the substrate 301 along the first direction. Figure 3D (As shown) Extending initial sacrificial strips 302. The initial sacrificial strips 302 are arranged in parallel and spaced apart from each other.

[0043] An isolation layer 303 and a first anti-reflective layer 304 are also disposed on the substrate 301 as mask layers for subsequent processes. The material of the isolation layer 303 includes amorphous carbon (ACL) or polycrystalline silicon, and the material of the first anti-reflective layer 304 includes nitrides, such as silicon nitride or silicon oxynitride. In this embodiment, the isolation layer 303 is an amorphous carbon layer, and the first anti-reflective layer 304 is a silicon oxynitride layer. The initial sacrificial strip 302 is formed on the first anti-reflective layer 304. In other embodiments of this disclosure, other film layers besides the isolation layer 303 and the first anti-reflective layer 304 may also be disposed on the substrate 301. This embodiment only describes the isolation layer 303 and the first anti-reflective layer 304 as an example.

[0044] In this embodiment, the initial sacrificial strip 302 includes a spin-on hard mask (SOH) layer and a silicon oxynitride layer sequentially disposed thereon. In other embodiments of this disclosure, the initial sacrificial strip 302 may also include only the spin-on hard mask layer.

[0045] In this step, a spin-coated hard mask material layer and a silicon oxynitride material layer can be formed on the first anti-reflection layer 304; then the spin-coated hard mask material layer and the silicon oxynitride material layer are patterned to form an initial sacrificial strip 302 extending along the first direction.

[0046] Please see Figure 3B A first spacer 312 is formed on the sidewall of the initial sacrificial strip 302.

[0047] The material of the first spacer 312 includes oxides, such as silicon oxide. In this step, a first spacer layer may be formed first, covering the sidewalls and top surface of the initial sacrificial strip 302 and the surface of the first antireflective layer 304. The first spacer layer may be formed using an atomic layer deposition process to improve the film quality of the first spacer layer. Then, the first spacer layer on the top surface of the initial sacrificial strip 302 and the surface of the first antireflective layer 304 is removed using a dry etching process. The first spacer layer located on the sidewalls of the initial sacrificial strip 302 is retained as the first spacer 312.

[0048] Please see Figure 3C Remove the initial sacrificial bar 302.

[0049] In this embodiment, a dry etching process is used to remove the initial sacrificial strip 302. During the etching process, the surface of the first anti-reflective layer 304 not covered by the initial sacrificial strip 302 and the first spacer strip 312 is also etched, so that the surface of the first anti-reflective layer 304 in this area is lower than the surface of the first anti-reflective layer 304 covered by the first spacer strip 312.

[0050] Please continue reading. Figure 3D and Figure 3E A spacer is filled between the first spacers 312 to form a first sacrificial strip 311. The first sacrificial strip 311 and the first spacers 312 are alternately arranged and extend along the first direction D. In this embodiment, the top surface of the first sacrificial strip 311 is flush with the top surface of the first spacers 312. The first sacrificial strip 311 is a spin-on hard mask (SOH) layer.

[0051] In this embodiment, after forming the first pattern layer 310, a second anti-reflective layer 313 is also formed on the first pattern layer 310. The material of the second anti-reflective layer 313 includes nitrides, such as silicon nitride or silicon oxynitride. To clearly illustrate the solution of this disclosure, Figure 3D To remove the structure of the second anti-reflective layer 313, Figure 3E The second anti-reflective layer 313 was not removed.

[0052] Please refer to step S21. Figure 3F and Figure 3G ,in, Figure 3F This is a top view. Figure 3G For along Figure 3FA cross-sectional view of the CC line shows that a second pattern layer 320 is formed on the first pattern layer 310, and the second pattern layer 320 includes second sacrificial strips 321 spaced apart along the second direction E.

[0053] In this embodiment, the second pattern layer 320 is formed on the surface of the second antireflective layer 313. In this step, a sacrificial material layer can first be formed on the surface of the second antireflective layer 313, and then the sacrificial material layer can be patterned to form the second sacrificial strip 321. In this embodiment, the second sacrificial strip 321 includes a spin-on hard mask (SOH) layer and a silicon oxynitride layer sequentially disposed thereon. In other embodiments of this disclosure, the second sacrificial strip 321 may also include only the spin-on hard mask layer. Since the first spacer 312 is obscured by the second antireflective layer 313, in order to clearly show the solution of this disclosure, in Figure 3F The first spacer bar 312 is drawn with a dashed line.

[0054] The first direction D and the second direction E form an acute angle. For example, in some embodiments, the angle between the first direction D and the second direction E is 20 degrees to 40 degrees. The angle between the first direction D and the second direction E can be determined according to the layout design of the capacitor via.

[0055] Please refer to step S22 and Figure 3H A cover layer 330 is formed, which covers the surface of the second sacrificial strip 321 and the exposed surface of the first pattern layer 310.

[0056] In this embodiment, since a second anti-reflective layer 313 is formed on the surface of the first pattern layer 310, the capping layer 330 covers the sidewalls and top surface of the second sacrificial strip 321 and the surface of the second anti-reflective layer 313. The capping layer 330 includes an oxide layer, such as a silicon oxide layer. In this step, the capping layer 330 is formed using an atomic layer deposition process to improve the film quality of the capping layer 330.

[0057] Please refer to step S23 and Figure 3I A mask layer 340 is formed, which covers the surface of the cover layer 330 located in the peripheral region PA.

[0058] This embodiment provides a method for forming a mask layer 340. The method includes: forming a mask material layer that covers the cover layer 330 and fills the gaps between the second sacrificial strips 321; and removing the mask material layer from the array region AA to form the mask layer 340. In some embodiments, the mask material layer fills the gaps between the second sacrificial strips 321, and its top surface protrudes beyond the top surface of the cover layer 330 to ensure that the gaps between the second sacrificial strips 321 are filled by the mask material layer. The mask layer 340 includes a photoresist layer. In this embodiment, a spin-coating process can be used to spin-coat photoresist material to form the mask material layer.

[0059] In some embodiments, the boundary of the mask layer 340 adjacent to the array region AA is aligned with the second direction E (see [reference]). Figure 3F The mask layer 340 is parallel to the boundary of the array region AA, which is in the same direction as the second sacrificial layer. This can prevent the mask layer 340 from affecting the pattern transfer of the second pattern layer 320.

[0060] As described in the first embodiment, after performing step S23, due to the limitations of the photolithography process, there is a gap 341 between the side of the mask layer 340 and the adjacent cover layer 330.

[0061] Please refer to step S24 and Figure 3K A supplementary layer 350 is formed at the junction of the array region AA and the peripheral region PA, and the supplementary layer 350 fills the gap 341 between the side of the mask layer 340 and the adjacent cover layer 330.

[0062] This embodiment provides a method for forming the supplementary layer 350. The method includes the following steps;

[0063] Please see Figure 3J A supplementary material layer 351 is formed, which covers the surfaces of the cover layer 330 and the mask layer 340, and fills the gap 341 between the side of the mask layer 340 and the adjacent cover layer 330 (see [link]). Figure 3I In this step, the supplementary material layer can be formed using an atomic layer deposition process to improve the film quality of the subsequently formed supplementary layer 350.

[0064] Please continue reading. Figure 3K Part of the supplementary material layer is removed, leaving the supplementary material layer filling the gap 341 between the side of the mask layer 340 and the adjacent cover layer 330, as the supplementary layer 350. In this step, a dry etching process can be used to remove the supplementary material layer.

[0065] Please refer to step S25 and Figure 3L Using the mask layer 340 as a mask, a portion of the cover layer 330 is removed, while the cover layer 330 located on the sidewall of the second sacrificial strip 321 is retained, forming the second spacer strip 322.

[0066] In this step, the cover layer 330 on the top surface of the second sacrificial strip 321 and the surface of the second antireflective layer 313 is removed, but the cover layer 330 in the area shielded by the mask layer 340 and the sidewall of the second sacrificial strip 321 is not removed, and the supplementary layer 350 filling the gap 341 between the sidewall of the mask layer 340 and the adjacent cover layer 330 is also not removed. In the array region AA, the remaining cover layer 330 on the sidewall of the second sacrificial strip 321 serves as the second spacer 322. At the junction of the array region AA and the peripheral region PA, the remaining cover layer 330 on the sidewall of the second sacrificial strip 321 and the supplementary layer 350 together serve as the second spacer 322.

[0067] In some embodiments of this disclosure, the step of removing part of the supplementary material layer and the step of removing part of the cover layer 330 are performed in the same etching step, thereby avoiding additional processing steps, simplifying semiconductor process steps, saving costs, and improving production efficiency.

[0068] In the actual process, while removing the cover layer 330, the mask layer 340 and the supplementary layer 350 on the side of the mask layer 340 are also thinned at the same time. However, it is understood that the supplementary layer 350 at the gap 341 between the side of the mask layer 340 and the cover layer 330 is still retained.

[0069] Please refer to step S26 and Figure 3M Remove the second sacrificial strip 321, the mask layer 340, and the first sacrificial strip 311, and form an initial pattern defined by the first spacer strip 312 and the second spacer strip 322 in the array region AA.

[0070] After performing this step, in the array region AA, the cover layer 330 located on the sidewall of the second sacrificial strip 321 is retained; at the junction of the array region AA and the peripheral region PA, the mask layer 340 and the supplementary layer 350 are retained, that is, the second spacer strip 322 is retained; and in the peripheral region PA, the cover layer 330 of the area covered by the mask layer 340 is retained.

[0071] In this step, a wet etching process is used to remove the second sacrificial strip 321 and the mask layer 340. After removing the second sacrificial strip 321, the second anti-reflective layer 313 beneath the second sacrificial strip 321 is exposed. The method then further includes removing the second anti-reflective layer 313 that is not obscured by the second spacer strip 322, exposing the first sacrificial strip 311. After the first sacrificial strip 311 is exposed, a wet etching process is used to remove the first sacrificial strip 311 again, exposing the first anti-reflective layer 304.

[0072] When performing a wet etching process, an etching solution with a low etching rate for the capping layer 330 and the supplementary layer 350 can be selected for etching to avoid damage to the capping layer 330 and the supplementary layer 350, which would affect the execution of subsequent processes. In some embodiments of this disclosure, the supplementary layer 350 is made of the same material as the capping layer 330. Therefore, when removing the second sacrificial strip 321 and the mask layer 340, the damage to the capping layer 330 or the supplementary layer 350 caused by the different etching rates of the etching solution to the capping layer 330 and the supplementary layer 350 can be avoided.

[0073] Please refer to step S27 and Figure 3N The initial pattern is transferred to the substrate 301 to form the target pattern.

[0074] In this step, the first spacer 312 and the second spacer 322 are used as masks, and the substrate 301 is etched using a dry etching process to transfer the initial pattern into the substrate 301 to form a target pattern. The target pattern includes capacitor holes 304, and the capacitor holes 304 are arranged in an array.

[0075] In this embodiment, since the isolation layer 303 is disposed on the substrate 301, the initial pattern is first transferred to the isolation layer 303 to form an intermediate pattern; then, using the isolation layer 303 as a mask, the intermediate pattern is transferred to the substrate 301 to form the target pattern. In some embodiments, a first anti-reflective layer 304 is also disposed on the surface of the isolation layer 303. In the step of forming the intermediate pattern, the first anti-reflective layer 304 is also patterned, and in the step of forming the target pattern, the first anti-reflective layer 304 can also serve as a mask.

[0076] Please see Figure 3O The method further includes removing the first spacer 312 and the second spacer 322 after forming the target pattern. In this embodiment, after removing the first spacer 312 and the second spacer 322, the isolation layer 303 and the first anti-reflective layer 304 are also removed.

[0077] The preparation method of this embodiment utilizes a supplementary layer 350 to fill the gap 341 between the mask layer 340 and the cover layer 330, avoiding the formation of a pattern corresponding to the gap 341 in the initial pattern. Therefore, after the pattern transfer based on the initial pattern, it is possible to avoid the formation of pseudo-capacitor holes in the substrate 301, prevent the edge pattern of the array region AA from deviating from the predetermined design, and thereby improve the yield of the semiconductor structure.

[0078] This disclosure also provides a semiconductor structure formed using the above-described preparation method. Please refer to [link / reference]. Figure 3K The semiconductor structure includes a substrate 300, a second pattern layer 320, a capping layer 330, a mask layer 340, and a supplementary layer 350.

[0079] The substrate 300 is divided into an array region AA and a peripheral region PA. The array region AA is used to form a capacitor array, and the peripheral region PA may have conductive structures such as transistors for electrical connection with subsequent conductive contact plugs.

[0080] The substrate 300 includes a substrate 301 and a first pattern layer 310 disposed on the substrate 301.

[0081] The substrate 301 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 301 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 301 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 301 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or pn junction diodes, may also be formed in the substrate 301. In this embodiment, the substrate 301 is a silicon substrate, which also includes other device structures, such as bit line structures and transistor structures, but these are not shown as they are not relevant to this disclosure.

[0082] The first pattern layer 310 includes a first patterned layer along the first direction D (see [reference]). Figure 3D A first sacrificial strip 311 and a first spacer strip 312 are arranged at intervals. The first sacrificial strip 311 and the first spacer strip 312 are alternately arranged and extend along the first direction D. In this embodiment, the top surface of the first sacrificial strip 311 is flush with the top surface of the first spacer strip 312. The first sacrificial strip 311 is a spin-on hard mask (SOH) layer. The material of the first spacer strip 312 includes oxides, such as silicon oxide.

[0083] In this embodiment, the substrate 300 further includes an isolation layer 303 and a first anti-reflective layer 304. The isolation layer 303 is disposed on the substrate 301, the first anti-reflective layer 304 is disposed on the isolation layer 303, and the first pattern layer 310 is disposed on the first anti-reflective layer 304. In other embodiments of this disclosure, other film layers besides the isolation layer 303 and the first anti-reflective layer 304 may be disposed on the substrate 301. This embodiment only describes the disposal of the isolation layer 303 and the first anti-reflective layer 304 as an example.

[0084] The second pattern layer 320 is disposed on the first pattern layer 310. The second pattern layer 320 includes a second patterning layer along the second direction E (see [reference]). Figure 3F A second sacrificial strip 321 is spaced apart. In this embodiment, the second sacrificial strip 321 includes a spin-on hard mask (SOH) layer and a silicon oxynitride layer sequentially disposed. In other embodiments of this disclosure, the second sacrificial strip 321 may also include only the spin-on hard mask layer. The first direction and the second direction form an acute angle. For example, in some embodiments, the angle between the first direction and the second direction is 20 degrees to 40 degrees. The angle between the first direction and the second direction can be determined according to the layout design of the capacitor vias.

[0085] In this embodiment, the semiconductor structure further includes a second anti-reflection layer 313, which is disposed on the first pattern layer 310, and the second pattern layer 320 is disposed on the second anti-reflection layer 313.

[0086] The cover layer 330 covers the surface of the second sacrificial strip 321 and the exposed surface of the first pattern layer 310, that is, the cover layer 330 covers the top surface and sidewalls of the second sacrificial strip 321 and the exposed top surface of the first pattern layer 310. In this embodiment, since the surface of the first pattern layer 310 is provided with a second anti-reflective layer 313, the cover layer 330 does not cover the top surface of the first pattern layer 310, but covers the exposed top surface of the second anti-reflective layer 313. In other embodiments of this disclosure, if the second anti-reflective layer 313 is not present, the cover layer 330 covers the exposed top surface of the first pattern layer 310. In this embodiment, the cover layer 330 is an oxide layer, which is formed by atomic deposition, resulting in a high-quality film.

[0087] The mask layer 340 covers the surface of the cover layer 330 located in the peripheral region PA. A gap 341 exists between the side of the mask layer 340 and its adjacent cover layer 330 (see [link]). Figure 3IThat is, the side of the mask layer 340 does not fully contact the adjacent cover layer 330. In some embodiments, the boundary of the array region AA adjacent to the mask layer 340 is perpendicular to the second direction E (see [reference]). Figure 3F Parallelism, meaning that the boundary of the mask layer 340 adjacent to the array region AA is parallel to the direction of extension of the second sacrificial layer, can prevent the mask layer 340 from affecting the pattern transfer of the second pattern layer 320 in subsequent process steps.

[0088] The supplementary layer 350 is disposed at the junction of the array region AA and the peripheral region PA, and the supplementary layer 350 fills the gap 341 between the side of the mask layer 340 and the adjacent cover layer 330 (see [link]). Figure 3I The supplementary layer 350 is in contact with the mask layer 340 and the cover layer 330 on opposite sides, and covers the cover layer 330 below the gap 341. The supplementary layer 350 can be prepared using atomic layer deposition, resulting in a high-quality film.

[0089] In some embodiments, the material of the supplementary layer 350 is the same as that of the cover layer 330. In the subsequent etching process based on the semiconductor structure, the situation where the cover layer 330 or the supplementary layer 350 is damaged due to the different etching rates of the etching solution on the cover layer 330 and the supplementary layer 350 can be avoided.

[0090] The semiconductor structure provided in this disclosure has a supplementary layer 350 filling the gap 341 between the side of the mask layer 340 and the adjacent cover layer 330. This prevents the pattern at the gap 341 from being transferred to the substrate 300 through the first pattern layer 310 and the second pattern layer 320 to form a pseudo-capacitor hole, and prevents the edge pattern of the array region AA from deviating from the predetermined design, thereby improving the yield of the semiconductor structure.

[0091] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, include: A substrate is provided, the substrate being divided into an array region and a peripheral region, the substrate including a substrate and a first pattern layer disposed on the substrate, the first pattern layer including first sacrificial strips and first spacer strips arranged at intervals along a first direction; A second pattern layer is formed on the first pattern layer, the second pattern layer including second sacrificial strips spaced apart along a second direction, the first direction and the second direction forming an acute angle; A cover layer is formed, which covers the surface of the second sacrificial strip and the exposed surface of the first pattern layer; A mask layer is formed, which covers the surface of the cover layer located in the peripheral region; A supplementary layer is formed at the boundary between the array region and the peripheral region, filling the gap between the side of the mask layer and the adjacent cover layer; Using the mask layer as a mask, part of the cover layer is removed, leaving the cover layer located on the sidewall of the second sacrificial strip to form a second spacer strip; Remove the second sacrificial strip, the mask layer, and the first sacrificial strip to form an initial pattern defined by the first spacer strip and the second spacer strip in the array region; The initial pattern is transferred into the substrate to form the target pattern.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The steps of forming the supplementary layer further include: A supplementary material layer is formed, which covers the surface of the cover layer and the mask layer; Remove part of the supplementary material layer, leaving the supplementary material layer that fills the gaps between the side of the mask layer and the adjacent cover layer, as the supplementary layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The step of removing part of the supplementary material layer and the step of removing part of the cover layer are performed in the same etching step.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The supplementary layer is made of the same material as the cover layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The supplementary layer is formed using an atomic layer deposition process.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the step of forming the second spacer, at the junction of the array region and the peripheral region, the covering layer of the sidewall of the second sacrificial strip and the supplementary layer together serve as the second spacer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming the mask layer further includes: A mask material layer is formed, which covers the cover layer and fills the gaps between the second sacrificial strips; Remove the mask material layer from the array region to form the mask layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate further includes an isolation layer disposed between the substrate and the first patterning layer, and the step of transferring the initial pattern into the substrate to form the target pattern further includes: Using the first and second spacers as masks, the initial pattern is transferred into the isolation layer to form an intermediate pattern; Using the isolation layer as a mask, the intermediate pattern is transferred into the substrate.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The substrate further includes a first anti-reflective layer disposed between the isolation layer and the first pattern layer. In the step of transferring the initial pattern into the isolation layer using the first spacer and the second spacer as masks to form an intermediate pattern, the first anti-reflective layer is also patterned.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method for forming the first patterned layer on the substrate includes the following steps: An initial sacrificial strip extending along the first direction is formed on the substrate; A first spacer is formed on the sidewall of the initial sacrificial strip; Remove the initial sacrifice bar; The spacers between the first spacers are filled with spacers to form the first sacrificial strips.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, A second anti-reflective layer is also formed on the first pattern layer. The second pattern layer is formed on the second anti-reflective layer. After removing the second sacrificial strip, the method further includes the step of removing the second anti-reflective layer below the second sacrificial strip.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, The angle between the first direction and the second direction is 20 degrees to 40 degrees.

13. The method for preparing a semiconductor structure according to claim 1, characterized in that, The boundary of the mask layer adjacent to the array region is parallel to the second direction.

14. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming the target pattern is followed by the step of removing the first spacer bar and the second spacer bar.

15. A semiconductor structure, characterized in that, include: A substrate, the substrate being divided into an array region and a peripheral region, the substrate including a substrate and a first pattern layer disposed on the substrate, the first pattern layer including first sacrificial strips and first spacer strips arranged at intervals along a first direction; A second pattern layer is placed on the first pattern layer. The second pattern layer includes second sacrificial strips spaced apart along a second direction. The first direction and the second direction form an acute angle. A cover layer that covers the surface of the second sacrificial strip and the exposed surface of the first pattern layer; A mask layer covers the surface of the cover layer located in the peripheral area; A supplementary layer, located at the boundary between the array region and the peripheral region, fills the gap between the side of the mask layer and the adjacent cover layer.

16. The semiconductor structure according to claim 15, characterized in that, The supplementary layer is made of the same material as the cover layer.

17. The semiconductor structure according to claim 15, characterized in that, The substrate further includes an isolation layer disposed between the substrate and the first patterned layer.

18. The semiconductor structure according to claim 17, characterized in that, The substrate further includes a first anti-reflective layer disposed between the isolation layer and the first pattern layer.

19. The semiconductor structure according to claim 15, characterized in that, A second anti-reflective layer is further provided between the first pattern layer and the second pattern layer, and the cover layer covers the surface of the second sacrificial strip and the exposed surface of the second anti-reflective layer.

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