Display substrate and display device

Abstract

The present invention provides a display substrate and a display device, which relate to the field of display technology and are used to reduce the power consumption of pixel circuits. The display substrate includes: a plurality of sub-pixels arranged on a substrate and a first scan line and a data line arranged on the substrate; the gate of the data writing transistor in the sub-pixel is coupled to the corresponding first scan line, the first electrode of the data writing transistor is coupled to the corresponding data line, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; the gate of the driving transistor is coupled to the first end of the first conductive connection portion; the second end of the first conductive connection portion is respectively coupled to the second electrode of the compensation transistor and the compensation pattern; the orthographic projection of the second electrode of the compensation transistor on the substrate at least partially overlaps with the orthographic projection of the corresponding first scan line on the substrate; the orthographic projection of the compensation pattern on the substrate at least partially overlaps with the orthographic projection of the corresponding first scan line on the substrate. The display substrate provided by the present invention is used for display.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] The low temperature polysilicon (LTPS) pixel circuit has a large leakage current, which is not conducive to maintaining the node voltage. Adding an oxide transistor (Oxide TFT) to the pixel circuit, combining the Oxide TFT with the LTPS TFT, forms a low temperature polycrystalline oxide (LTPO) pixel circuit. The LTPO pixel circuit can improve the leakage problem and help improve the stability of the pixel circuit. However, the LTPO pixel circuit still has the problem of high power consumption that needs to be solved. Summary of the invention

[0003] An object of the present invention is to provide a display substrate and a display device for reducing the power consumption of an LTPO pixel circuit.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display substrate, comprising: a substrate, a plurality of sub-pixels arranged on the substrate, and a plurality of first scan lines and a plurality of data lines arranged on the substrate; the sub-pixels include: a data writing transistor, a driving transistor, a compensation transistor, a first conductive connection portion and a compensation pattern;

[0006] The gate of the data writing transistor is coupled to the corresponding first scanning line, the first electrode of the data writing transistor is coupled to the corresponding data line, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor;

[0007] The gate of the driving transistor is coupled to the first end of the first conductive connection portion;

[0008] The second end of the first conductive connection portion is coupled to the second electrode of the compensation transistor and the compensation pattern respectively;

[0009] The orthographic projection of the second electrode of the compensation transistor on the substrate at least partially overlaps with the orthographic projection of the corresponding first scanning line on the substrate; the orthographic projection of the compensation pattern on the substrate at least partially overlaps with the orthographic projection of the corresponding first scanning line on the substrate.

[0010] Optionally, the compensation transistor includes a second active layer, and the second active layer includes at least a portion extending along the first direction;

[0011] The second end of the second active layer serves as the second electrode of the compensation transistor, and the orthographic projection of the second end of the second active layer on the substrate and the orthographic projection of the compensation pattern on the substrate are arranged along a second direction, and the second direction intersects with the first direction.

[0012] Optionally, the second end of the first conductive connection portion includes at least a portion extending along the second direction;

[0013] The orthographic projection of the second end of the first conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the second end of the second active layer on the substrate and the orthographic projection of the compensation pattern on the substrate.

[0014] Optionally, the display substrate further includes a plurality of second scan lines, and the gate of the compensation transistor is coupled to the corresponding second scan lines; the orthographic projection of the first conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the second scan line on the substrate.

[0015] Optionally, the second scanning line includes a first scanning layer and a second scanning layer which are stacked, and at least a portion of the first scanning layer is located between the substrate and the second scanning layer;

[0016] The second scanning layer includes a scanning main body and a scanning protrusion, the scanning main body extends along the second direction, and at least part of the orthographic projection of the scanning protrusion on the substrate is located between the orthographic projection of the scanning main body on the substrate and the orthographic projection of the compensation pattern on the substrate.

[0017] Optionally, the first scanning line includes a first scanning portion and a second scanning portion, and a minimum width of the first scanning portion along the first direction is greater than a minimum width of the second scanning portion;

[0018] The orthographic projection of the first scanning portion on the substrate at least partially overlaps with the orthographic projection of the second electrode of the compensation transistor on the substrate and the orthographic projection of the compensation pattern on the substrate.

[0019] Optionally, the display substrate includes a plurality of second initialization signal lines; the sub-pixel includes a second reset transistor and a light-emitting element;

[0020] The gate of the second reset transistor is coupled to the corresponding first scanning line, the first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and the second electrode of the second reset transistor is coupled to the light-emitting element; the orthographic projection of the second initialization signal line on the substrate overlaps with the orthographic projection of the second scanning part on the substrate.

[0021] Optionally, an orthographic projection of the second initialization signal line on the substrate does not overlap with an orthographic projection of the first scanning portion on the substrate.

[0022] Optionally, the second initialization signal line includes a first initial part, a second initial part and a third initial part; the second initial part is coupled to the first initial part and the third initial part respectively;

[0023] The first initial portion extends along a second direction, the third initial portion extends along the first direction, the second initial portion extends along a third direction, the second direction intersects the first direction, and the third direction intersects both the first direction and the second direction;

[0024] The orthographic projection of the second scanned portion on the substrate at least partially overlaps with the orthographic projection of the second initial portion on the substrate and the orthographic projection of the third initial portion on the substrate, respectively.

[0025] Optionally, the second reset transistor includes a seventh active layer, and the seventh active layer includes a first active portion, a second active portion, a third active portion and a fourth active portion coupled in sequence;

[0026] The first active portion extends along a second direction, the second active portion and the fourth active portion extend along a first direction, and the third active portion extends along a third direction; the second direction intersects the first direction, and the third direction intersects both the first direction and the second direction;

[0027] The first active portion is coupled to the light emitting element, and the fourth active portion forms a first electrode, a second electrode and a channel portion of the second reset transistor.

[0028] Optionally, the display substrate further includes a plurality of reset lines and a plurality of first initialization signal lines; the sub-pixel further includes a first reset transistor, a gate of the first reset transistor is coupled to the corresponding reset line, a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the second electrode of the compensation transistor;

[0029] The reset line comprises a first reset layer and a second reset layer which are stacked, wherein at least a portion of the first reset layer is located between the second reset layer and the substrate; and the second reset layer is in the shape of a long strip extending along a second direction.

[0030] Optionally, the first reset layer includes a first reset portion, a second reset portion, a third reset portion and a fourth reset portion coupled in sequence; the first reset portion, the second reset portion and the fourth reset portion all extend along the second direction, and the third reset portion extends along the third direction;

[0031] An orthographic projection of the third reset portion on the substrate at least partially overlaps with an orthographic projection of the third active portion on the substrate.

[0032] Optionally, an orthographic projection of the third resetting portion on the substrate at least partially overlaps with an orthographic projection of the second initial portion on the substrate.

[0033] Optionally, the first initialization signal line includes an initialization main portion and an initialization protrusion, the initialization main portion extends along the second direction, and at least a portion of the orthographic projection of the initialization protrusion on the substrate is located between the orthographic projection of the initialization main portion on the substrate and the orthographic projection of the compensation pattern on the substrate.

[0034] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present invention provides a display device, comprising the above-mentioned display substrate.

[0035] In the technical solution provided by the present invention, a compensation pattern is added, and the second end of the first conductive connection portion is respectively coupled to the second electrode of the compensation transistor and the compensation pattern; the orthographic projection of the second electrode of the compensation transistor on the substrate at least partially overlaps with the orthographic projection of the corresponding first scanning line on the substrate; the orthographic projection of the compensation pattern on the substrate at least partially overlaps with the orthographic projection of the corresponding first scanning line on the substrate. This arrangement enables the capacitor formed between the second electrode of the compensation transistor and the corresponding first scanning line to form a parallel capacitor structure together with the capacitor formed between the compensation pattern and the first scanning line, thereby improving ΔC, reducing the black state voltage, and reducing the power consumption of the sub-pixel driving circuit in the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0037] Figure 1A circuit diagram of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of the layout of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the layout of the poly active layer and the first gate metal layer in a plurality of sub-pixels distributed in an array provided by an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of the layout of the oxide active layer, the second gate metal layer and the third gate metal layer in a plurality of sub-pixels distributed in an array provided by an embodiment of the present invention;

[0041] Figure 5 For Figure 4 A schematic diagram of the layout of a first source / drain metal layer is added on the basis;

[0042] Figure 6 for Figure 3 Schematic diagram of the layout of the poly active layer;

[0043] Figure 7 for Figure 3 A schematic diagram of the layout of the first gate metal layer;

[0044] Figure 8 for Figure 5 A schematic diagram of the layout of the second gate metal layer;

[0045] Fig. 9 for Figure 5 Schematic diagram of the layout of the oxide active layer;

[0046] Fig.10 for Figure 5 Schematic diagram of the layout of the third gate metal layer;

[0047] Fig.11 for Figure 5 A schematic diagram of the layout of the first source and drain metal layer;

[0048] Fig.12 A schematic diagram of the layout of the second source-drain metal layer in a plurality of sub-pixels distributed in an array provided by an embodiment of the present invention;

[0049] Fig.13 A schematic diagram of various capacitance parameters for comparing the related art and the embodiments of the present invention;

[0050] Fig.14 The first schematic diagram is a comparison of data voltages corresponding to L255 and L0 of red, green and blue sub-pixels in the simulation of the related technology and the embodiment of the present invention under normal display brightness;

[0051] Fig.15 It is a first schematic diagram for comparing the data voltages corresponding to L255 and L0 of the red, green and blue sub-pixels in the simulation of the related technology and the embodiment of the present invention under high display brightness;

[0052] Fig.16 A schematic diagram of the relationship between the change in C1 and the change in ΔC provided in an embodiment of the present invention;

[0053] Fig.17 A schematic diagram showing the relationship between the change in C1 and the change in black state voltage corresponding to the red, green and blue color sub-pixels provided in an embodiment of the present invention;

[0054] Fig.18 A second schematic diagram for comparing the data voltages corresponding to L255 and L0 of the red, green and blue sub-pixels in the simulation of the related technology and the embodiment of the present invention under normal display brightness;

[0055] Fig.19 A second schematic diagram showing the comparison of data voltages corresponding to L255 and L0 of red, green and blue sub-pixels in the simulation of the related technology and the embodiment of the present invention under high display brightness;

[0056] Fig. 20 A schematic diagram of the layout of a poly active layer, a second gate metal layer, and a first source and drain metal layer in a plurality of sub-pixels distributed in an array provided by an embodiment of the present invention;

[0057] Fig.21 A schematic diagram of the layout of a first gate metal layer, a second gate metal layer, an oxide active layer, and a first source-drain metal layer in a plurality of sub-pixels distributed in an array provided by an embodiment of the present invention;

[0058] Fig. 22 A schematic diagram of the layout of a first source-drain metal layer and a second source-drain metal layer in a plurality of sub-pixels distributed in an array provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to further illustrate the display substrate and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0060] like Figures 1 to 3 As shown, the display substrate provided in an embodiment of the present invention includes a plurality of LTPO pixel circuits, and the LTPO pixel circuit includes: a driving transistor T3, a compensation transistor T2, a first reset transistor T1, a second reset transistor T7, a data writing transistor T4, a power control transistor T5, a light emitting control transistor T6 and a storage capacitor Cst.

[0061] The display substrate includes a power supply line 16 , a plurality of data lines 11 , a plurality of first scanning lines 10 , a plurality of second scanning lines 12 , a plurality of reset lines 14 , a plurality of light emitting control lines 17 , a plurality of first initialization signal lines 15 and a plurality of second initialization signal lines 13 .

[0062] The gate of the first reset transistor T1 is coupled to the corresponding reset line 14 , the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line 15 , and the second electrode of the first reset transistor T1 is coupled to the gate T3 - g of the driving transistor T3 .

[0063] The gate of the compensation transistor T2 is coupled to the corresponding second scan line 12 , the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3 , and the second electrode of the compensation transistor T2 is coupled to the gate T3 - g of the driving transistor T3 .

[0064] The gate of the data writing transistor T4 is coupled to the corresponding first scanning line 10 , the first electrode of the data line 11 is coupled to the corresponding data line 11 , and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3 .

[0065] The gate of the power control transistor T5 is coupled to the corresponding light emitting control line 17 , the first electrode of the power control transistor T5 is coupled to the power line 16 , and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3 .

[0066] The gate of the light emitting control transistor T6 is coupled to the corresponding light emitting control line 17, the first electrode of the light emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light emitting control transistor T6 is coupled to the anode of the corresponding light emitting element EL. The cathode of the light emitting element EL receives the negative power signal VSS.

[0067] The gate of the second reset transistor T7 is coupled to the corresponding light emitting control line 17 , the first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line 13 , and the second electrode of the second reset transistor T7 is coupled to the anode of the corresponding light emitting element EL.

[0068] The gate T3 - g of the driving transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power line 16 .

[0069] It should be noted that the node connected between the gate T3 - g of the driving transistor T3 and the second electrode of the compensation transistor T2 and the second electrode of the first reset transistor T1 is the N1 node.

[0070] Based on the problems existing in the background technology, it is found through research that in the LTPO pixel circuit, the black state voltage is related to △C, where △C=C1 / C2; C1 is the capacitance value formed between the N1 node and the first scan line 10. C2 is the capacitance value formed between the N1 node and the second scan line 12. The larger the △C ratio, the smaller the black state voltage, and the lower the power consumption of the LTPO pixel circuit.

[0071] The capacitance formed between the N1 node and the first scan line 10 refers to the capacitance formed between the IGZO (Indium Gallium Zinc Oxide) layer at the N1 node and the first scan line 10 .

[0072] The capacitance formed between the N1 node and the second scan line 12 refers to the capacitance formed between the source-drain metal layer at the N1 node and the second scan line 12 .

[0073] If you want to increase △C, you can consider increasing C1. For example, you can increase the overlapping area between the IGZO layer at the N1 node and the first scan line 10. To increase the overlapping area between the IGZO layer at the N1 node and the first scan line 10, it is necessary to increase the area of ​​the IGZO layer and / or the first scan line 10. However, since the LTPO pixel circuit includes more film layers, and in order to take into account the high-resolution requirements, the layout of the LTPO pixel circuit is more difficult, making the pixel pitch (PixelPitch) corresponding to the LTPO pixel circuit more difficult to compress. Therefore, the area value that can be increased by the IGZO layer and / or the first scan line 10 is limited, which makes the adjustment range of C1 limited and the improvement range of △C limited.

[0074] Based on the above problem, the present invention considers adding an additional capacitor in parallel with the capacitor formed between the N1 node and the first scan line 10 to increase ΔC.

[0075] See also Figures 1 to 5 , Figures 7 to 9 , Fig.11 , Fig.12 and Fig.21 , an embodiment of the present invention provides a display substrate, comprising: a substrate, a plurality of sub-pixels arranged on the substrate, and a plurality of first scanning lines 10 and a plurality of data lines 11 arranged on the substrate; the sub-pixels include: a data writing transistor T4, a driving transistor T3, a compensation transistor T2, a first conductive connection portion 31 and a compensation pattern 20;

[0076] The gate of the data writing transistor T4 is coupled to the corresponding first scanning line 10, the first electrode of the data writing transistor T4 is coupled to the corresponding data line 11, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3;

[0077] The gate T3-g of the driving transistor T3 is coupled to the first end of the first conductive connection portion 31;

[0078] The second end 310 of the first conductive connection portion 31 is coupled to the second electrode of the compensation transistor T2 and the compensation pattern 20 respectively;

[0079] The orthographic projection of the second electrode of the compensation transistor T2 on the substrate at least partially overlaps with the orthographic projection of the corresponding first scan line 10 on the substrate; the orthographic projection of the compensation pattern 20 on the substrate at least partially overlaps with the orthographic projection of the corresponding first scan line 10 on the substrate.

[0080] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light emitting element EL. The sub-pixel driving circuit is coupled to the light emitting element EL to provide a driving signal to the light emitting element EL. The sub-pixel driving circuit includes a plurality of transistors and a storage capacitor Cst.

[0081] Exemplarily, the sub-pixel driving circuit includes a driving transistor T3, a compensation transistor T2, a first reset transistor T1, a second reset transistor T7, a data writing transistor T4, a power control transistor T5 and a light emission control transistor T6. Figure 6 As shown, the third active layer 43 included in the driving transistor T3, the fourth active layer 44 included in the data writing transistor T4, the fifth active layer 45 included in the power control transistor T5, the sixth active layer 46 included in the light emission control transistor T6, and the seventh active layer 47 included in the second reset transistor T7 are illustrated. Fig. 9 As shown, a first active layer 41 included in the first reset transistor T1 and a second active layer 42 included in the compensation transistor T2 are illustrated.

[0082] Exemplarily, the driving transistor T3, the second reset transistor T7, the data writing transistor T4, the power control transistor T5 and the light emission control transistor T6 are all LTPS transistors. The compensation transistor T2 and the first reset transistor T1 are all oxide transistors.

[0083] Exemplarily, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a first direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. The plurality of columns of sub-pixel driving circuits are arranged along the second direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction.

[0084] Exemplarily, the first direction intersects with the second direction. Exemplarily, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0085] Exemplarily, the plurality of first scan lines 10 are arranged along the first direction, and each first scan line 10 includes at least a portion extending along the second direction. The plurality of first scan lines 10 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the first scan lines 10 are respectively coupled to the gates of the data writing transistors T4 in the corresponding row of sub-pixel driving circuits.

[0086] Exemplarily, the plurality of data lines 11 are arranged along the second direction, and each data line 11 includes at least a portion extending along the first direction. The plurality of data lines 11 correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and the data line 11 is coupled to the first electrode of each data writing transistor T4 in the corresponding column of sub-pixel driving circuits.

[0087] It should be noted that the signal line extends along the X direction means that the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending along other directions.

[0088] Exemplarily, the display substrate includes: a light-shielding layer, an isolation layer, a first buffer layer, a poly active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a second buffer layer, an oxide active layer (such as an IGZO layer), a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source-drain metal layer, a passivation layer, a first planarizing layer, a second source-drain metal layer, a second planarizing layer, an anode layer, a pixel defining layer, a spacer layer, a light-emitting functional layer, a cathode layer and an encapsulation layer, which are stacked on the substrate in a direction away from the substrate.

[0089] Exemplarily, the first scan line 10 is made of the first gate metal layer.

[0090] Exemplarily, the data line 11 is made of the second source-drain metal layer.

[0091] Exemplarily, the first conductive connection portion 31 is made of the first source-drain metal layer.

[0092] Exemplarily, the second electrode of the compensation transistor T2 is made of an IGZO layer.

[0093] Exemplarily, the compensation pattern 20 is made of a second gate metal layer.

[0094] Exemplarily, the orthographic projection of the second electrode of the compensation transistor T2 on the substrate at least partially overlaps with the orthographic projection of the corresponding first scan line 10 on the substrate, and a capacitance value C11 is formed between the second electrode of the compensation transistor T2 and the first scan line 10. The orthographic projection of the compensation pattern 20 on the substrate at least partially overlaps with the orthographic projection of the corresponding first scan line 10 on the substrate, and a capacitance value C12 is formed between the compensation pattern 20 and the first scan line 10. According to the principle of capacitors in parallel, the above C1=C11+C12, which increases the value of C1, thereby increasing ΔC.

[0095] According to the specific structure of the above-mentioned display substrate, it can be known that in the display substrate provided by the embodiment of the present invention, a compensation pattern 20 is added, and the second end 310 of the first conductive connection portion 31 is provided to be coupled to the second electrode of the compensation transistor T2 and the compensation pattern 20 respectively; the orthographic projection of the second electrode of the compensation transistor T2 on the substrate at least partially overlaps with the orthographic projection of the corresponding first scanning line 10 on the substrate; the orthographic projection of the compensation pattern 20 on the substrate at least partially overlaps with the orthographic projection of the corresponding first scanning line 10 on the substrate.

[0096] The above-mentioned setting method enables the capacitor formed between the second electrode of the compensation transistor T2 and the corresponding first scan line 10 to form a parallel capacitor structure together with the capacitor formed between the compensation pattern 20 and the first scan line 10, thereby improving ΔC, reducing the black state voltage, and reducing the power consumption of the sub-pixel driving circuit in the display substrate.

[0097] Moreover, since the dielectric constants of the first gate metal layer and the second gate metal layer are relatively large, C12 is relatively large, which is conducive to better improving ΔC, thereby further reducing the power consumption of the sub-pixel driving circuit in the display substrate.

[0098] In addition, when the data voltage on the data line jumps, crosstalk is generated on the potential of the adjacent N1 node. The smaller the black state voltage is, the smaller the Crosstalk is. Therefore, in the display substrate provided by the embodiment of the present invention, the black state voltage is reduced and the Crosstalk is alleviated.

[0099] In more detail, Fig.13 As shown, A represents a related technical solution, and B represents a technical solution provided by an embodiment of the present invention.

[0100] In the related technical solution, C1=7.398, C2=2.643, ΔC=2.8.

[0101] In the technical solution provided by the embodiment of the present invention, C1=24.856, C2=2.409, ΔC=10.32.

[0102] It can be seen that C1 in the solution provided by the embodiment of the present invention is 3.3 times of C1 in the related technical solution, and ΔC in the solution provided by the embodiment of the present invention is 3.6 times of ΔC in the related technical solution. Therefore, the solution provided by the embodiment of the present invention greatly increases C1, thereby increasing ΔC.

[0103] It is worth noting that the potentials of the above capacitance values ​​are all in fF.

[0104] like Fig.14 As shown, a simulation comparison of the L255 grayscale data voltage and a simulation comparison of the L0 grayscale data voltage under normal display brightness conditions are shown.

[0105] like Fig.15 As shown, a simulation comparison of the L255 grayscale data voltage and a simulation comparison of the L0 grayscale data voltage under high brightness (HBM) display conditions are shown.

[0106] It can be seen that under normal display brightness conditions and high brightness (HBM) display conditions, after increasing △C, the data voltage will decrease by about 2.2V-2.3V, especially the data voltage corresponding to L0, R / G / B is reduced by 2.3V. It should be noted that Fig.14 , Fig.15 , Fig.18 and Fig.19 The value in represents the data voltage in volts. Fig.14 , Fig.15 , Fig.18 and Fig.19 In the figure, Red represents the red sub-pixel, Green represents the green sub-pixel, and Blue represents the blue sub-pixel.

[0107] like Fig.16 As shown in the figure, in the technical solution provided by the embodiment of the present invention, C1 is reduced in proportion by 1.5f until C12 is 0, and the schematic diagram of the change of △C. Among them, C1 changes from 24.86f to 3.86f, and △C decreases from 10.32 to 0.88 accordingly. Compared with the related technical solutions, in the technical solution provided by the embodiment of the present invention, the adjustment range of C1 and △C is larger, which can meet different black state voltage requirements.

[0108] like Fig.17As shown, it is a schematic diagram of the corresponding relationship between C1 and the black state voltage in the technical solution provided by the embodiment of the present invention. It can be seen that the black state voltage range is 4.0V-7.0V, and the adjustment range is 3.0V. The appropriate Red / Green / Blue black state voltage is selected as 5.49V / 5.59V / 5.30V, and the corresponding C1 is 14.36f and △C is 5.96. In this case, under normal display brightness conditions and high brightness (HBM) display conditions, the simulation comparison of the data voltage at the L255 grayscale and the simulation comparison of the data voltage at the L0 grayscale are carried out between the related technology and the embodiment of the present invention.

[0109] like Fig.18 As shown, under normal display brightness conditions, a simulation comparison of the data voltage at the L255 grayscale and a simulation comparison of the data voltage at the L0 grayscale are shown between the related art and the embodiment of the present invention.

[0110] like Fig.19 As shown, under high brightness (HBM) display conditions, a simulation comparison of the data voltage at the L255 grayscale and a simulation comparison of the data voltage at the L0 grayscale are shown between the related art and the embodiment of the present invention.

[0111] It can be seen that under normal display brightness conditions and under high brightness (HBM) display conditions, after increasing △C, the data voltage will decrease by about 1V. The data voltage has a 30% gain under L255 grayscale and a 15% gain in black state voltage.

[0112] like Figure 5 , Fig. 9 and Fig.21 As shown, in some embodiments, the compensation transistor T2 includes a second active layer 42, and the second active layer 42 includes at least a portion extending along the first direction;

[0113] The second end of the second active layer 42 serves as the second electrode of the compensation transistor T2. The orthographic projection of the second end of the second active layer 42 on the substrate and the orthographic projection of the compensation pattern 20 on the substrate are arranged along a second direction, and the second direction intersects the first direction.

[0114] Exemplarily, the second active layer 42 is made of an IGZO layer. The second active layer 42 is used to form a channel portion of the compensation transistor T2, and a first electrode and a second electrode of the compensation transistor T2.

[0115] Exemplarily, the first end of the second active layer 42 serves as the first electrode of the compensation transistor T2 , and the second end of the second active layer 42 serves as the second electrode of the compensation transistor T2 .

[0116] Exemplarily, the orthographic projection of the second end of the second active layer 42 on the substrate is arranged not to overlap with the orthographic projection of the compensation pattern 20 on the substrate. This arrangement can avoid the formation of a new transistor between the second active layer 42 and the compensation pattern 20, thereby ensuring the stability of the sub-pixel driving circuit.

[0117] The above-mentioned setting of the orthographic projection of the second end of the second active layer 42 on the substrate is arranged along the second direction with the orthographic projection of the compensation pattern 20 on the substrate, and the first scanning line 10 includes at least a portion extending along the second direction, thereby reducing the difficulty of sub-pixel layout while ensuring the capacitor parallel structure.

[0118] like Figure 5 , Fig. 9 , Fig.11 , Fig. 20 and Fig.21 As shown, in some embodiments, the second end 310 of the first conductive connection portion 31 is provided to include at least a portion extending along the second direction; the orthographic projection of the second end 310 of the first conductive connection portion 31 on the substrate at least partially overlaps with the orthographic projection of the second end of the second active layer 42 on the substrate and the orthographic projection of the compensation pattern 20 on the substrate.

[0119] Exemplarily, the orthographic projection of the second end 310 of the first conductive connection portion 31 on the substrate has an overlapping area with the orthographic projection of the second end of the second active layer 42 on the substrate, and the second end 310 of the first conductive connection portion 31 is coupled to the second end of the second active layer 42 through a via located in the overlapping area.

[0120] Exemplarily, the orthographic projection of the second end 310 of the first conductive connection portion 31 on the substrate has an overlapping area with the orthographic projection of the compensation pattern 20 on the substrate, and the second end 310 of the first conductive connection portion 31 is coupled to the compensation pattern 20 through a via located in the overlapping area.

[0121] Exemplarily, the orthographic projection of the second end 310 of the first conductive connection portion 31 on the substrate is located inside the orthographic projection of the first scanning line 10 on the substrate.

[0122] The above configuration not only ensures that the second end 310 of the first conductive connection portion 31 can be coupled to the second end of the second active layer 42 and the compensation pattern 20 respectively, but also reduces the difficulty of sub-pixel layout.

[0123] like Figure 5 , Figure 8 and Fig.10As shown, in some embodiments, the display substrate further includes a plurality of second scan lines 12, and the gate of the compensation transistor T2 is coupled to the corresponding second scan lines 12; the orthographic projection of the first conductive connection portion 31 on the substrate at least partially overlaps with the orthographic projection of the second scan line 12 on the substrate.

[0124] Exemplarily, the gate of the compensation transistor T2 and the corresponding second scan line 12 form an integrated structure.

[0125] Exemplarily, the second scan line 12 includes at least a portion extending along the second direction.

[0126] Exemplarily, the plurality of second scan lines 12 are arranged along the first direction, the plurality of second scan lines 12 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the second scan lines 12 are respectively coupled to the gates of the compensation transistors T2 in a corresponding row of sub-pixel driving circuits.

[0127] Exemplarily, at least a portion of the orthographic projection of the second scan line 12 on the substrate is located between the orthographic projection of the first end of the first conductive connection portion 31 on the substrate and the orthographic projection of the second end 310 of the first conductive connection portion 31 on the substrate.

[0128] The orthographic projection of the first conductive connection portion 31 on the substrate at least partially overlaps with the orthographic projection of the second scanning line 12 on the substrate, so that a capacitor is formed between the first conductive connection portion 31 and the second scanning line 12 , and the capacitance of the capacitor is C2 mentioned above.

[0129] like Figure 5 , Figure 8 and Fig.10 As shown, in some embodiments, the second scanning line 12 includes a first scanning layer 120 and a second scanning layer 121 which are stacked, and at least a portion of the first scanning layer 120 is located between the substrate and the second scanning layer 121;

[0130] The second scanning layer 121 includes a scanning main body 1210 and a scanning protrusion 1211, the scanning main body 1210 extends along the second direction, and at least a part of the orthographic projection of the scanning protrusion 1211 on the substrate is located between the orthographic projection of the scanning main body 1210 on the substrate and the orthographic projection of the compensation pattern 20 on the substrate.

[0131] Exemplarily, the compensation transistor T2 is formed as a dual-gate transistor, a portion of the gate of which is made of the second gate metal layer, and another portion of the gate of which is made of the third gate metal layer.

[0132] Exemplarily, the first scanning layer 120 is made of a second gate metal layer, and the second scanning line layer 12 is made of a third gate metal layer.

[0133] Exemplarily, the first scanning layer 120 includes at least a portion extending along the second direction, and the second scanning layer 121 includes at least a portion extending along the second direction.

[0134] Exemplarily, the orthographic projection of the first conductive connection portion 31 on the substrate at least partially overlaps with the orthographic projection of the scanning body portion 1210 on the substrate and the orthographic projection of the scanning protrusion 1211 on the substrate.

[0135] The orthographic projection of the first conductive connection portion 31 on the substrate at least partially overlaps with the orthographic projection of the second scanning layer 121 on the substrate, so that a capacitor is formed between the first conductive connection portion 31 and the second scanning layer 121 , and the capacitance of the capacitor is the above-mentioned C2.

[0136] The above-mentioned arrangement of at least a portion of the orthographic projection of the scanning protrusion 1211 on the substrate is located between the orthographic projection of the scanning main body 1210 on the substrate and the orthographic projection of the compensation pattern 20 on the substrate, so that the second scanning line 12 and the compensation pattern 20 can be arranged more reasonably, effectively reducing the layout space occupied by sub-pixels.

[0137] like Figure 3 and Figure 7 As shown, in some embodiments, the first scanning line 10 is configured to include a first scanning portion 101 and a second scanning portion 102, and the minimum width of the first scanning portion 101 along the first direction is greater than the minimum width of the second scanning portion 102;

[0138] The orthographic projection of the first scanning portion 101 on the substrate at least partially overlaps with the orthographic projection of the second electrode of the compensation transistor T2 on the substrate and the orthographic projection of the compensation pattern 20 on the substrate.

[0139] Exemplarily, the first scanning part 101 and the second scanning part 102 are formed as an integrated structure.

[0140] Illustratively, in one scanning line, the first scanning part 101 and the second scanning part 102 are alternately arranged.

[0141] Exemplarily, along the first direction, the maximum width of the first scanning portion 101 is greater than the maximum width of the second scanning portion 102 .

[0142] Exemplarily, the orthographic projection of the first scanning portion 101 on the substrate at least partially overlaps with the orthographic projection of the second electrode of the compensation transistor T2 on the substrate, so that a capacitance value C11 is formed between the first scanning portion 101 and the second electrode of the compensation transistor T2. The orthographic projection of the first scanning portion 101 on the substrate at least partially overlaps with the orthographic projection of the compensation pattern 20 on the substrate, so that a capacitance value C12 is formed between the first scanning portion 101 and the compensation pattern 20.

[0143] The above configuration makes the minimum width of the first scanning portion 101 along the first direction greater than the minimum width of the second scanning portion 102, which is conducive to increasing the overlapping area between the orthographic projection of the first scanning portion 101 on the substrate and the orthographic projection of the second electrode of the compensation transistor T2 on the substrate, thereby facilitating the increase of the capacitance value C11. At the same time, it is conducive to increasing the overlapping area between the orthographic projection of the first scanning portion 101 on the substrate and the orthographic projection of the compensation pattern 20 on the substrate, thereby facilitating the increase of the capacitance value C12.

[0144] like Figure 1 , Figure 3 , Figure 5 , Figure 7 and Fig.11 As shown, in some embodiments, the display substrate includes a plurality of second initialization signal lines 13; the sub-pixel includes a second reset transistor T7 and a light emitting element EL;

[0145] The gate of the second reset transistor T7 is coupled to the corresponding first scanning line 10, the first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line 13, and the second electrode of the second reset transistor T7 is coupled to the light-emitting element EL; the orthographic projection of the second initialization signal line 13 on the substrate partially overlaps with the orthographic projection of the second scanning part 102 on the substrate.

[0146] Exemplarily, the plurality of second initialization signal lines 13 are arranged along the first direction. The second initialization signal line 13 includes at least a portion extending along the second direction.

[0147] Exemplarily, the plurality of second initialization signal lines 13 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the second initialization signal lines 13 are respectively coupled to the first electrodes of the second reset transistors T7 in a corresponding row of sub-pixel driving circuits.

[0148] Exemplarily, the first scan line 10 is respectively coupled to the gates of the second reset transistors T7 in a corresponding row of sub-pixel driving circuits.

[0149] Exemplarily, the gate of the second reset transistor T7 in the current sub-pixel driving circuit and the gate of the data writing transistor T4 in the sub-pixel driving circuit adjacent to the first direction are coupled to the same first scan line 10 .

[0150] Exemplarily, the second electrode of the second reset transistor T7 is coupled to the anode of the light emitting element EL.

[0151] Exemplarily, the second initialization signal line 13 is made of the first source-drain metal layer.

[0152] In the display substrate provided by the above embodiment, by setting the orthographic projection of the second initialization signal line 13 on the substrate to overlap with the orthographic projection of the second scanning part 102 on the substrate, it is possible to reduce the overlapping area between the orthographic projection of the second initialization signal line 13 on the substrate and the orthographic projection of the first scanning line 10 on the substrate while ensuring that the second initialization signal line 13 is coupled to the first electrode of the second reset transistor T7, thereby facilitating the reduction of the parasitic capacitance formed between the second initialization signal line 13 and the first scanning line 10, and effectively improving the working stability of the sub-pixel driving circuit.

[0153] like Figure 1 , Figure 3 , Figure 5 , Figure 7 and Fig.11 As shown, in some embodiments, the orthographic projection of the boundary of the second initialization signal line 13 on the substrate is set to partially overlap with the orthographic projection of the boundary of the first scanning portion 101 on the substrate.

[0154] In some embodiments, an orthographic projection of the second initialization signal line 13 on the substrate is set to not overlap with an orthographic projection of the first scanning part 101 on the substrate.

[0155] The above configuration can further reduce the parasitic capacitance formed between the second initialization signal line 13 and the first scanning line 10 , and effectively improve the working stability of the sub-pixel driving circuit.

[0156] like Figure 5 , Figure 7 , Fig.11 , Fig. 20 and Fig.21 As shown, in some embodiments, the second initialization signal line 13 is set to include a first initial portion 131, a second initial portion 132 and a third initial portion 133; the second initial portion 132 is coupled to the first initial portion 131 and the third initial portion 133 respectively;

[0157] The first initial portion 131 extends along a second direction, the third initial portion 133 extends along the first direction, the second initial portion 132 extends along a third direction, the second direction intersects the first direction, and the third direction intersects both the first direction and the second direction;

[0158] The orthographic projection of the second scanning portion 102 on the substrate at least partially overlaps with the orthographic projection of the second initial portion 132 on the substrate and the orthographic projection of the third initial portion 133 on the substrate.

[0159] Exemplarily, the second initialization signal line 13 includes a first initial portion 131 , a second initial portion 132 , a third initial portion 133 and a fourth initial portion 134 which are coupled in sequence.

[0160] Exemplarily, the first initial portion 131 , the second initial portion 132 , the third initial portion 133 and the fourth initial portion 134 are formed into an integral structure.

[0161] Exemplarily, the first initial portion 131 includes a strip pattern extending along the second direction, the third initial portion 133 includes a strip pattern extending along the first direction, the second initial portion 132 includes a strip pattern extending along the third direction, and the fourth initial portion 134 includes a strip pattern extending along the second direction.

[0162] Exemplarily, the orthographic projection of the first initial portion 131 on the substrate and the orthographic projection of the first scanning portion 101 on the substrate are arranged along the first direction.

[0163] Exemplarily, the orthographic projection of the first scanning portion 101 on the substrate and the orthographic projection of the fourth initial portion 134 on the substrate are arranged along the second direction.

[0164] Exemplarily, the orthographic projection of the second scanning portion 102 on the substrate and the orthographic projection of the fourth initial portion 134 on the substrate are arranged along the first direction.

[0165] Exemplarily, the orthographic projection of the second initialization signal line 13 on the substrate does not overlap with the orthographic projection of the compensation pattern 20 on the substrate.

[0166] Exemplarily, the orthographic projection of the compensation pattern 20 on the substrate and the orthographic projection of the third initial portion 133 on the substrate are arranged along the second direction.

[0167] The above arrangement is conducive to reducing the length of the first scanning portion 101 along the second direction, increasing the distance between the orthographic projection of the first scanning portion 101 on the substrate and the orthographic projection of the third initial portion 133 on the substrate, thereby effectively reducing the resistance of the first scanning line 10 and reducing the loading on the first scanning line 10. It has been verified that the resistance of the first scanning line 10 can be reduced by about 20%.

[0168] Moreover, the above arrangement is also beneficial to increasing the transmittance of the non-metallic layer of the display substrate.

[0169] In more detail, in the related art, the non-metal transmittance in the backplane section (BP section) is 13.17%. After the touch layer routing (TSP routing) is completed, the TSP section is entered, and the non-metal transmittance in the TSP section is 9.92%. In the display substrate provided in the above embodiment, the non-metal transmittance in the BP section is 13.30%, and the non-metal transmittance in the TSP section is 10.48%. In the display substrate provided in the above embodiment, the non-metal transmittance in the BP section has a benefit of 0.99%, and the non-metal transmittance in the TSP section has a benefit of 5.65%.

[0170] like Figure 2 , Figure 3 , Figure 6 As shown, in some embodiments, the second reset transistor T7 is provided to include a seventh active layer 47, and the seventh active layer 47 includes a first active portion 471, a second active portion 472, a third active portion 473 and a fourth active portion 474 coupled in sequence;

[0171] The first active portion 471 extends along the second direction, the second active portion 472 and the fourth active portion 474 extend along the first direction, and the third active portion 473 extends along the third direction; the second direction intersects the first direction, and the third direction intersects both the first direction and the second direction;

[0172] The first active portion 471 is coupled to the light emitting element EL, and the fourth active portion 474 forms a first electrode, a second electrode and a channel portion of the second reset transistor T7.

[0173] Exemplarily, the seventh active layer 47 is made of a poly active layer.

[0174] Exemplarily, the first active portion 471 includes a strip pattern extending along the second direction, the second active portion 472 and the fourth active portion 474 both include a strip pattern extending along the first direction, and the third active portion 473 includes a strip pattern extending along the third direction.

[0175] Exemplarily, the orthographic projection of the first active portion 471 on the substrate is located between the orthographic projection of the gate T3 - g of the driving transistor T3 on the substrate and the orthographic projection of the first initialization signal line 15 on the substrate.

[0176] Illustratively, an orthographic projection of the second active portion 472 on the substrate at least partially overlaps with an orthographic projection of the first initialization signal line 15 on the substrate.

[0177] Illustratively, an orthographic projection of the third active portion 473 on the substrate does not overlap with an orthographic projection of the second initialization signal line 13 on the substrate.

[0178] Illustratively, an orthographic projection of the fourth active portion 474 on the substrate at least partially overlaps with an orthographic projection of the second initialization signal line 13 on the substrate.

[0179] The above configuration method is conducive to simplifying the structure of sub-pixels, reducing the layout space occupied by sub-pixels, and reducing the difficulty of sub-pixel layout.

[0180] like Figure 4 , Figure 5 , Figures 8 to 10 As shown, in some embodiments, the display substrate is further provided with a plurality of reset lines 14 and a plurality of first initialization signal lines 15; the sub-pixel further includes a first reset transistor T1, a gate of the first reset transistor T1 is coupled to the corresponding reset line 14, a first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line 15, and a second electrode of the first reset transistor T1 is coupled to the second electrode of the compensation transistor T2;

[0181] The reset line 14 includes a first reset layer 141 and a second reset layer 142 which are stacked. At least a portion of the first reset layer 141 is located between the second reset layer 142 and the substrate. The second reset layer 142 is in a strip shape extending along the second direction.

[0182] Need to explain, Figure 8 The dots in the figure represent the positions where the via holes are formed in the display substrate.

[0183] Exemplarily, the plurality of first initialization signal lines 15 are arranged along the first direction, and the first initialization signal lines 15 include at least a portion extending along the second direction. The plurality of first initialization signal lines 15 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the first initialization signal lines 15 are respectively coupled to the first electrodes of the first reset transistors T1 in the corresponding row of sub-pixel driving circuits.

[0184] Exemplarily, the plurality of reset lines 14 are arranged along the second direction, and the reset lines 14 include at least a portion extending along the second direction. The plurality of reset lines 14 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the reset lines 14 are respectively coupled to the gates of the first reset transistors T1 in the corresponding row of sub-pixel driving circuits.

[0185] Exemplarily, the first transistor is an oxide transistor, an active layer of the first transistor is made of an IGZO layer, and the active layer of the first transistor includes at least a portion extending along the first direction.

[0186] Exemplarily, the first reset layer 141 is made of a second gate metal layer, and the second reset layer 142 is made of a third gate metal layer.

[0187] Illustratively, an orthographic projection of the first resetting layer 141 on the substrate at least partially overlaps with an orthographic projection of the second resetting layer 142 on the substrate.

[0188] Exemplarily, the first reset transistor T1 includes a dual-gate structure, and the first reset layer 141 and the second reset layer 142 can be multiplexed as a gate of the first reset transistor T1 .

[0189] Illustratively, an orthographic projection of the second reset layer 142 on the substrate at least partially overlaps with an orthographic projection of the third active portion 473 on the substrate.

[0190] Illustratively, an orthographic projection of the second reset layer 142 on the substrate at least partially overlaps with an orthographic projection of the second active portion 472 on the substrate.

[0191] Illustratively, an orthographic projection of the second reset layer 142 on the substrate does not overlap with an orthographic projection of the fourth active portion 474 on the substrate.

[0192] Exemplarily, the orthographic projection of the reset line 14 on the substrate is located between the orthographic projection of the first initialization signal line 15 on the substrate and the orthographic projection of the first scan line 10 on the substrate.

[0193] The reset line 14 includes a first reset layer 141 and a second reset layer 142 which are stacked, which effectively reduces the resistance of the reset line 14. The resistance of the reset line 14 can be reduced by about 10%.

[0194] The above configuration method is conducive to simplifying the structure of sub-pixels, reducing the layout space occupied by sub-pixels, and reducing the difficulty of sub-pixel layout.

[0195] like Figure 2 , Figure 4 , Figure 5 , Figure 6 , Figures 8 to 10 , Fig. 20 and Fig.21 As shown, in some embodiments, the first resetting layer 141 includes a first resetting portion 1411, a second resetting portion 1412, a third resetting portion 1413 and a fourth resetting portion 1414 coupled in sequence; the first resetting portion 1411, the second resetting portion 1412 and the fourth resetting portion 1414 all extend along the second direction, and the third resetting portion 1413 extends along the third direction;

[0196] An orthographic projection of the third resetting portion 1413 on the substrate at least partially overlaps with an orthographic projection of the third active portion 473 on the substrate.

[0197] Illustratively, the first reset portion 1411 , the second reset portion 1412 , the third reset portion 1413 and the fourth reset portion 1414 are formed into an integrated structure.

[0198] Exemplarily, the first restoring portion 1411 , the second restoring portion 1412 , and the fourth restoring portion 1414 all include a strip structure extending along the second direction, and the third restoring portion 1413 includes a strip structure extending along the third direction.

[0199] Exemplarily, the orthographic projection of the third reset portion 1413 on the substrate at least partially overlaps with the orthographic projection of the third active portion 473 on the substrate. The orthographic projection of the third active portion 473 on the substrate does not overlap with the orthographic projection of the second initial portion 132 on the substrate.

[0200] Illustratively, a portion of the orthographic projection of the third resetting portion 1413 on the substrate is located between the orthographic projection of the third active portion 473 on the substrate and the orthographic projection of the second initial portion 132 on the substrate.

[0201] The above configuration method is conducive to simplifying the structure of sub-pixels, reducing the layout space occupied by sub-pixels, and reducing the difficulty of sub-pixel layout.

[0202] The above configuration effectively compresses the layout space occupied by a single sub-pixel driving circuit in the first direction, and can compress the layout space in the first direction by 1 micrometer to 2 micrometers, including the endpoint values.

[0203] like Figure 2 , Figure 4 , Figure 5 , Figure 8 and Fig.11As shown, in some embodiments, the orthographic projection of the third resetting portion 1413 on the substrate at least partially overlaps with the orthographic projection of the second initial portion 132 on the substrate.

[0204] like Figure 4 , Figure 5 , Figure 6 and Figure 8 As shown, in some embodiments, the first initialization signal line 15 includes an initialization main body 150 and an initialization protrusion 151, the initialization main body 150 extends along the second direction, and at least a portion of the orthographic projection of the initialization protrusion 151 on the substrate is located between the orthographic projection of the initialization main body 150 on the substrate and the orthographic projection of the compensation pattern 20 on the substrate.

[0205] Exemplarily, the first initialization signal line 15 is made of the second gate metal layer.

[0206] Exemplarily, the initialization body 150 and the initialization protrusion 151 are formed as an integral structure.

[0207] Exemplarily, the initialization body 150 includes a strip-shaped pattern extending along the second direction.

[0208] Exemplarily, at least a portion of the orthographic projection of the initialization protrusion 151 on the substrate is located between the orthographic projection of the initialization body 150 on the substrate and the orthographic projection of the reset line 14 on the substrate.

[0209] Exemplarily, the orthographic projection of the first active layer 41 included in the first reset transistor T1 on the substrate at least partially overlaps with the orthographic projection of the initialization body 150 on the substrate. The first active layer 41 included in the first reset transistor T1 is used to form the first electrode, the second electrode and the channel portion of the first reset transistor T1.

[0210] Exemplarily, the active layer included in the first reset transistor T1 and the active layer included in the compensation transistor T2 form an integral structure. Exemplarily, the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2 form an integral structure.

[0211] Exemplarily, the sub-pixel further includes a second conductive connection portion 32, and the second conductive connection portion 32 is made of the first source-drain metal layer. The orthographic projection of the second conductive connection portion 32 on the substrate and the orthographic projection of the initialization protrusion 151 on the substrate have an overlapping area, and the second conductive connection portion 32 and the initialization protrusion 151 are coupled through a via located in the overlapping area. The orthographic projection of the second conductive connection portion 32 on the substrate and the orthographic projection of the first electrode of the first reset transistor T1 on the substrate have an overlapping area, and the second conductive connection portion 32 and the first electrode of the first reset transistor T1 are coupled through a via located in the overlapping area.

[0212] The above configuration method is conducive to simplifying the structure of sub-pixels, reducing the layout space occupied by sub-pixels, and reducing the difficulty of sub-pixel layout.

[0213] Need to explain, such as Figure 2 and Fig.11 As shown, Fig.11 Also illustrated are the third conductive connection portion 33, the fourth conductive connection portion 34, the fifth conductive connection portion 35, the sixth conductive connection portion 36 and the seventh conductive connection portion 37. The third conductive connection portion 33 is coupled to the first electrode of the compensation transistor T2 and the second electrode of the driving transistor T3 through vias, respectively. The fourth conductive connection portion 34 is coupled to the sixth conductive connection portion 36 through a via, the sixth conductive connection portion 36 is coupled to the anode of the light-emitting element through a via, and the fourth conductive connection portion 34 is also coupled to the second electrode of the light-emitting control transistor T6 and the second electrode of the second reset transistor T7 through a via. The fifth conductive connection portion 35 is coupled to the second electrode plate Cst2 of the storage capacitor Cst through a via, the fifth conductive connection portion 35 is coupled to the power line 16 through a via, and the fifth conductive connection portion 35 is coupled to the first electrode of the power control transistor T5 through a via. As shown in FIG. Fig. 20 and Fig. 22 As shown, the seventh conductive connection portion 37 is coupled to the first electrode of the data writing transistor T4 and the data line 11 through via holes respectively.

[0214] It is worth noting that Fig.11 The black vias in FIG. 1 are vias for coupling the first source-drain metal layer with the second source-drain metal layer.

[0215] like Figure 1 and Figure 3As shown, in some embodiments, the display substrate further includes a plurality of light-emitting control lines 17, the plurality of light-emitting control lines 17 are arranged along the first direction, and the light-emitting control lines 17 include at least a portion extending along the second direction. The plurality of light-emitting control lines 17 correspond one-to-one to the plurality of rows of sub-pixel driving circuits. The sub-pixel driving circuit further includes a power control transistor T5 and a light-emitting control transistor T6. The light-emitting control line 17 is respectively coupled to the gate of each power control transistor T5 in a corresponding row of sub-pixel driving circuits. The light-emitting control line 17 is respectively coupled to the gate of each light-emitting control transistor T6 in a corresponding row of sub-pixel driving circuits.

[0216] Exemplarily, the light emitting control line 17 is made of a first gate metal layer.

[0217] Exemplarily, at least a portion of the orthographic projection of the light emitting control line 17 on the substrate is located between the orthographic projection of the gate T3 - g of the driving transistor T3 on the substrate and the orthographic projection of the first active portion 471 on the substrate.

[0218] Exemplarily, the gate of the power control transistor T5 is coupled to the corresponding light emitting control line 17, the first electrode of the power control transistor T5 is coupled to the power line 16, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3. The gate of the light emitting control transistor T6 is coupled to the corresponding light emitting control line 17, the first electrode of the light emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light emitting control transistor T6 is coupled to the anode of the corresponding light emitting element EL.

[0219] An embodiment of the present invention further provides a display device, comprising the display substrate provided by the above embodiment.

[0220] In the display substrate provided by the above embodiment, a compensation pattern 20 is added, and the second end 310 of the first conductive connection portion 31 is provided to couple with the second electrode of the compensation transistor T2 and the compensation pattern 20 respectively; the orthographic projection of the second electrode of the compensation transistor T2 on the substrate overlaps with the orthographic projection of the corresponding first scanning line 10 on the substrate at least in part; the orthographic projection of the compensation pattern 20 on the substrate overlaps with the orthographic projection of the corresponding first scanning line 10 on the substrate at least in part. The above arrangement enables the capacitor formed between the second electrode of the compensation transistor T2 and the corresponding first scanning line 10 to form a parallel capacitor structure together with the capacitor formed between the compensation pattern 20 and the first scanning line 10, thereby improving ΔC, reducing the black state voltage, and reducing the power consumption of the sub-pixel driving circuit in the display substrate. Moreover, since the dielectric constants of the first gate metal layer and the second gate metal layer are relatively large, C12 is relatively large, which is conducive to better improving ΔC, thereby further reducing the power consumption of the sub-pixel driving circuit in the display substrate.

[0221] The display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0222] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0223] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0224] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0225] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0226] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0227] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0228] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0229] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: A substrate, a plurality of sub-pixels disposed on the substrate, and a plurality of first scan lines and a plurality of data lines disposed on the substrate; the sub-pixels include: a data writing transistor, a driving transistor, a compensation transistor, a first conductive connection portion and a compensation pattern; The gate of the data writing transistor is coupled to the corresponding first scanning line, the first electrode of the data writing transistor is coupled to the corresponding data line, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; The gate of the driving transistor is coupled to the first end of the first conductive connection portion; The second end of the first conductive connection portion is coupled to the second electrode of the compensation transistor and the compensation pattern respectively; The orthographic projection of the second electrode of the compensation transistor on the substrate at least partially overlaps with the orthographic projection of the corresponding first scanning line on the substrate; the orthographic projection of the compensation pattern on the substrate at least partially overlaps with the orthographic projection of the corresponding first scanning line on the substrate.

2. The display substrate according to claim 1, characterized in that: The compensation transistor includes a second active layer, the second active layer including at least a portion extending along a first direction; The second end of the second active layer serves as the second electrode of the compensation transistor, and the orthographic projection of the second end of the second active layer on the substrate and the orthographic projection of the compensation pattern on the substrate are arranged along a second direction, and the second direction intersects with the first direction.

3. The display substrate according to claim 2, characterized in that: The second end of the first conductive connection portion includes at least a portion extending along the second direction; The orthographic projection of the second end of the first conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the second end of the second active layer on the substrate and the orthographic projection of the compensation pattern on the substrate.

4. The display substrate according to claim 1, characterized in that: The display substrate further includes a plurality of second scan lines, and the gate of the compensation transistor is coupled to the corresponding second scan lines; the orthographic projection of the first conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the second scan line on the substrate.

5. The display substrate according to claim 4, characterized in that: The second scanning line includes a first scanning layer and a second scanning layer which are stacked, and at least a portion of the first scanning layer is located between the substrate and the second scanning layer; The second scanning layer includes a scanning main body and a scanning protrusion, the scanning main body extends along the second direction, and at least part of the orthographic projection of the scanning protrusion on the substrate is located between the orthographic projection of the scanning main body on the substrate and the orthographic projection of the compensation pattern on the substrate.

6. The display substrate according to claim 1, characterized in that: The first scanning line includes a first scanning portion and a second scanning portion, and a minimum width of the first scanning portion along the first direction is greater than a minimum width of the second scanning portion; The orthographic projection of the first scanning portion on the substrate at least partially overlaps with the orthographic projection of the second electrode of the compensation transistor on the substrate and the orthographic projection of the compensation pattern on the substrate.

7. The display substrate according to claim 6, characterized in that: The display substrate includes a plurality of second initialization signal lines; the sub-pixel includes a second reset transistor and a light emitting element; The gate of the second reset transistor is coupled to the corresponding first scan line, the first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and the second electrode of the second reset transistor is coupled to the light emitting element; An orthographic projection of the second initialization signal line on the substrate partially overlaps with an orthographic projection of the second scanning portion on the substrate.

8. The display substrate according to claim 7, characterized in that: An orthographic projection of the second initialization signal line on the substrate does not overlap with an orthographic projection of the first scanning portion on the substrate.

9. The display substrate according to claim 7, characterized in that: The second initialization signal line includes a first initial portion, a second initial portion and a third initial portion; the second initial portion is coupled to the first initial portion and the third initial portion respectively; The first initial portion extends along a second direction, the third initial portion extends along the first direction, the second initial portion extends along a third direction, the second direction intersects the first direction, and the third direction intersects both the first direction and the second direction; The orthographic projection of the second scanned portion on the substrate at least partially overlaps with the orthographic projection of the second initial portion on the substrate and the orthographic projection of the third initial portion on the substrate, respectively.

10. The display substrate according to claim 9, characterized in that: The second reset transistor includes a seventh active layer, the seventh active layer includes a first active portion, a second active portion, a third active portion and a fourth active portion coupled in sequence; The first active portion extends along a second direction, the second active portion and the fourth active portion extend along a first direction, and the third active portion extends along a third direction; the second direction intersects the first direction, and the third direction intersects both the first direction and the second direction; The first active portion is coupled to the light emitting element, and the fourth active portion forms a first electrode, a second electrode and a channel portion of the second reset transistor.

11. The display substrate according to claim 10, characterized in that: The display substrate further includes a plurality of reset lines and a plurality of first initialization signal lines; the sub-pixel further includes a first reset transistor, a gate of the first reset transistor is coupled to the corresponding reset line, a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the second electrode of the compensation transistor; The reset line comprises a first reset layer and a second reset layer which are stacked, wherein at least a portion of the first reset layer is located between the second reset layer and the substrate; and the second reset layer is in the shape of a long strip extending along a second direction.

12. The display substrate according to claim 11, characterized in that: The first reset layer includes a first reset portion, a second reset portion, a third reset portion and a fourth reset portion coupled in sequence; the first reset portion, the second reset portion and the fourth reset portion all extend along the second direction, and the third reset portion extends along the third direction; An orthographic projection of the third reset portion on the substrate at least partially overlaps with an orthographic projection of the third active portion on the substrate.

13. The display substrate according to claim 12, characterized in that: An orthographic projection of the third resetting portion on the substrate at least partially overlaps with an orthographic projection of the second initial portion on the substrate.

14. The display substrate according to claim 11, characterized in that: The first initialization signal line includes an initialization main portion and an initialization protrusion, the initialization main portion extends along the second direction, and at least a portion of the orthographic projection of the initialization protrusion on the substrate is located between the orthographic projection of the initialization main portion on the substrate and the orthographic projection of the compensation pattern on the substrate.

15. A display device, characterized in that: The invention comprises the display substrate according to any one of claims 1 to 14.

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