A method and system for correcting isolated through holes in a layout

Abstract

The present invention provides a method for correcting isolated through holes in a layout, comprising: obtaining layout information and determining a target through hole layer; obtaining a through hole peripheral area of ​​the through hole by performing regional expansion on the through holes in the target through hole layer, and judging for each through hole: whether there are other through holes in the through hole peripheral area; if not, judging that the through hole is an isolated through hole; determining a filling area; filling an auxiliary unit in the filling area to correct the isolated through hole. The correction method of the present invention corrects isolated through holes in combination with layout design rules during the layout design stage, and can perform real-time detection and modification of isolated through holes without affecting the original connection relationship of the circuit, which is beneficial to improving layout design, optimizing semiconductor process technology, and improving production efficiency and product yield. The present invention also provides a correction system for isolated through holes in a layout, which has corresponding advantages because it can detect and modify isolated through holes based on the correction method of the present invention.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor design and production, and in particular relates to a correction method for isolated through holes in a layout and a corresponding correction system. Background Art

[0002] In semiconductor manufacturing processes, such as back-end processes, in order to form metal interconnects, it is necessary to form through holes between two adjacent layers of metal wires to achieve metal interconnection. Figure 1 , the two adjacent layers of metal wires are the interconnection wires of the first interconnection wire layer A and the interconnection wires of the second interconnection wire layer B, and the interconnection wires are interconnected through through holes. As the circuit density increases and the key dimensions become smaller and smaller, the size of the wires, the wire spacing and the through holes are getting smaller and denser, even reaching below sub-micron. When the integrated circuit pattern on the mask is transferred to the photoresist layer on the wafer through exposure, it often deforms due to the optical proximity effect. Through holes of the same size in the sparse pattern area and the dense pattern area will produce different deformations after the pattern transfer, especially isolated through holes are prone to blind holes.

[0003] To address this problem, after the layout design is completed and before tape-out, the industry already has a method of using optical proximity correction (OPC) to correct the pattern on the mask. However, the optical proximity correction method is not suitable for real-time modification and detection during the layout design stage. Therefore, it is currently necessary to study a correction method for isolated vias in the layout and a corresponding system. During the layout design stage, isolated vias can be processed and the layout design can be improved without affecting the original connection relationship of the circuit, so as to further promote the in-depth development and widespread application of semiconductor design and production technology. Summary of the invention

[0004] The present invention is to solve all or part of the problems of the above-mentioned prior art. On one hand, the present invention provides a correction method for isolated vias in a layout, which is suitable for detecting and correcting isolated vias in the layout design stage without affecting the original connection relationship of the circuit. Another aspect of the present invention provides a correction system for isolated vias in a layout, which is used to execute the correction method of the present invention to detect and correct isolated vias in the layout design stage.

[0005] According to one aspect of the present invention, a method for correcting an isolated through hole in a layout is provided, comprising: step S1. acquiring layout information and determining a target through hole layer; step S2. obtaining a through hole peripheral area of ​​the through hole by performing regional expansion on the through hole of the target through hole layer; judging the through hole of the target through hole layer: whether there are other through holes of the target through hole layer in the through hole peripheral area of ​​the through hole; if not, judging the through hole as an isolated through hole, and recording the through hole peripheral area of ​​the isolated through hole as a first range; step S3. correcting the isolated through hole searched out in step S2: determining a filling area within the first range of the isolated through hole, and filling an auxiliary unit in the filling area to complete the correction; the auxiliary unit comprises: a through hole of the target through hole layer, and a first interconnection line unit in a first interconnection line layer and a second interconnection line unit in a second interconnection line layer respectively connected to the through hole; wherein the first interconnection line layer and the second interconnection line layer are upper and lower interconnection line layers respectively connected to the target through hole layer; and the filling area satisfies that filling the auxiliary unit therein does not affect the existing interconnections in the first interconnection line layer and the second interconnection line layer.

[0006] In the step S2, the through-hole peripheral area obtained after the through-hole in the target through-hole layer is expanded specifically refers to: a rectangular area formed by expanding the four sides of the through-hole after translating outwardly by a preset search distance.

[0007] The auxiliary unit adopts the auxiliary unit that occupies the smallest area under the condition of meeting the preset design rules.

[0008] The process of determining the filling area in step S3 includes: step S31. determining a fillable range; step S32. determining the filling area in the fillable range; the method of determining the fillable range is: expanding the interconnects in the first interconnect layer and the second interconnect layer by preset distances to form corresponding first interconnect ranges and second interconnect ranges; subtracting the overlapping areas with the first interconnect range and the second interconnect range from the first range to obtain a plurality of ranges, which are recorded as second ranges; subtracting the areas whose width in the vertical direction is less than V from the second range to obtain a plurality of ranges, which are recorded as third ranges; subtracting the areas whose width in the horizontal direction is less than L from the third range to obtain a plurality of ranges, which are the fillable ranges; wherein L refers to the maximum length of the auxiliary unit in the horizontal direction, and V refers to the maximum length of the auxiliary unit in the vertical direction.

[0009] The interconnection line is a rectangle, and the interconnection line is expanded by preset distances to form the corresponding first interconnection line range and second interconnection line range respectively in the following manner: a straight line where the long side of the interconnection line is located is moved by a distance TSmin toward the outside of the interconnection line along a direction perpendicular to the long side; a straight line where the short side of the interconnection line is located is moved by a distance TTmin toward the outside of the interconnection line along a direction perpendicular to the short side; wherein TSmin refers to the minimum distance from the end of the interconnection line to the side of the adjacent interconnection line in the preset design rule (the minimum value of tip to side); and TTmin refers to the minimum distance from the end of the interconnection line to the end of the adjacent interconnection line in the preset design rule (the minimum value of tip to tip).

[0010] In the step S31, in the same interconnection line layer, if there are overlapping parts between the ranges formed by the expansion of different interconnections at the preset distances, the ranges are merged into one interconnection line range. That is, one first interconnection line range or one second interconnection line range can be formed by merging several overlapping ranges.

[0011] The fillable range is in the form of a polygon, and the sides of the polygon are all horizontal or vertical sides.

[0012] The method for determining the filling area in step S32 is: randomly select a vertex of the fillable range; extend a horizontal side with a length equal to L and a vertical side with a length equal to V from the vertex into the fillable range; and determine the rectangular range formed by the horizontal side and the vertical side as the filling area.

[0013] There are several fillable ranges; in step S32, a filling area is determined in each fillable range; and an auxiliary unit is filled in a filling area to complete the correction.

[0014] On the other hand, the present invention also provides a correction system for isolated through holes in a layout, comprising a storage device and a processor; the storage device stores a plurality of instructions, and the instructions are suitable for the processor to load and execute the correction method for isolated through holes in a layout provided in one aspect of the present invention.

[0015] Compared with the prior art, the main beneficial effects of the present invention are:

[0016] 1. A method for correcting isolated through holes in a layout of the present invention can detect whether an isolated through hole exists by forming a peripheral area of ​​the through hole for searching and judging; by using auxiliary through hole units for filling, the distance between the isolated through hole and its nearest other through holes is shortened, thereby realizing correction of the isolated through hole in the layout design stage; and the present invention corrects the isolated through hole in the layout design stage in combination with the layout design rules, which can realize real-time modification and detection without affecting the original connection relationship of the circuit. It improves the defect of not being able to effectively detect and further correct isolated through holes in the layout design stage, which is conducive to improving layout design, optimizing semiconductor process technology, and improving production efficiency and product yield.

[0017] 2. A correction system for isolated through holes in a layout of the present invention has corresponding advantages because it can execute the correction method of the present invention; it has a simple structure, is easy to configure, and can automatically and efficiently realize the detection and correction of isolated through holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the interconnection between two adjacent layers of metal wires.

[0019] Figure 2 Schematic diagram of the correction method process of embodiment 1 of the present invention.

[0020] Figure 3 This is a schematic diagram of searching for isolated through holes according to the first embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of an auxiliary unit according to Embodiment 1 of the present invention.

[0022] Figure 5 Schematic diagram of the process of correcting isolated through holes according to the second embodiment of the present invention.

[0023] Figure 6(a) to Figure 6(f) It is a graphical schematic diagram of each process of correcting an isolated through hole in the second embodiment of the present invention. DETAILED DESCRIPTION

[0024] In the following embodiments, the operations of the embodiments are described in specific orders. The description of these orders is for better understanding of the details in the embodiments so as to fully understand the present invention. However, the description of these orders does not necessarily correspond to the methods of the present invention one by one, nor can it be used to limit the scope of the present invention.

[0025] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible operation processes of the methods according to the embodiments of the present invention, which can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or by a combination of dedicated hardware and manual operations.

[0026] Embodiment 1

[0027] In the first embodiment of the present invention, Figure 2 As shown in the figure, the correction method of isolated vias in the layout includes:

[0028] Step S1. Obtaining layout information and determining a target through-hole layer. In this embodiment, the layout information is obtained by reading a layout file.

[0029] Step S2. The preset search distance is recorded as D, and a corresponding through-hole peripheral area is formed for each through-hole in the target through-hole layer. For each through-hole in the target through-hole layer, it is judged whether there are other through-holes in the target through-hole layer in the through-hole peripheral area of ​​the through-hole; if not, the through-hole is judged to be an isolated through-hole, and the through-hole peripheral area of ​​the isolated through-hole is recorded as the first range 1. The search distance D can be set according to the specific layout design requirements or actual application conditions, and is not limited. Figure 3 As shown, the through-hole peripheral area is a rectangular area formed by expanding the through-hole by translating the four sides of the through-hole outward by D with the through-hole as the center.

[0030] Step S3. Correct the isolated through hole searched out in step S2: determine a filling area within the first range 1 of the isolated through hole, and fill the auxiliary unit in the filling area to complete the correction; the filling area satisfies that filling the auxiliary unit therein does not affect the interconnects in the first interconnect layer A and the second interconnect layer B. In this embodiment, the upper and lower interconnect layers connected to the target through hole layer are respectively recorded as the first interconnect layer A and the second interconnect layer B; Figure 4 As shown, the auxiliary unit includes: a through hole in the target through hole layer, a first interconnection line unit in the first interconnection line layer A and a second interconnection line unit in the second interconnection line layer B respectively connected to the through hole. In this embodiment, in each through hole peripheral area, it is searched whether there are other through holes in the target through hole layer except the through hole in the center of the through hole peripheral area; if there are no other through holes, that is, there is only one through hole in the center of the through hole peripheral area, then the through hole in the center of the through hole peripheral area is judged to be an isolated through hole. If there are other through holes, the central through hole in the through hole peripheral area is not an isolated through hole and no processing is required. Figure 3 The example has one isolated through hole. In some implementations, there are more than one through holes determined to be isolated through holes in step S2.

[0031] In this embodiment, the auxiliary unit adopts the auxiliary unit that occupies the smallest area under the condition of meeting the preset design rules. The basic requirement for designing auxiliary units is to ensure that the designed auxiliary unit is a geometric combination that occupies as small an area as possible, under the premise that the three layers of the first interconnection line layer A, the second interconnection line layer B and the through-hole layer are graphically related and do not violate any design rules. The design rules that need to be considered include the length, width, minimum spacing of the metal layer, the extension margin of the metal layer to the through-hole layer, etc. The relevant specific values ​​are determined by the specific design rules of each process in actual applications. Figure 4 As shown, L refers to the maximum length of the auxiliary unit in the horizontal direction, and V refers to the maximum length of the auxiliary unit in the vertical direction. In some implementations, the area occupied by the auxiliary unit is not the minimum, and L and V are set accordingly according to actual application and design, and are not limited. Figure 4 The auxiliary unit in the example is the simplest and smallest area-consuming implementation method of the auxiliary unit under the premise of meeting the process and design rules, but it is not the only way. The process of this embodiment stipulates that the extension directions of two adjacent interconnection lines can only be perpendicular to each other, so Figure 4 The first interconnection line unit and the second interconnection line unit in the exemplary auxiliary unit are perpendicular to each other. In some implementations, the possible process stipulates that the extension directions of two adjacent interconnection line layers can be parallel to each other, and even the interconnection lines in the interconnection line layer can be bent, which is not limited.

[0032] The correction method of this embodiment is implemented by the correction system of this embodiment. The exemplary correction system includes a storage device and a processor. The storage device stores a plurality of instructions, and the instructions are suitable for the processor to load and execute the correction method process to complete the detection correction of the isolated through hole.

[0033] Embodiment 2

[0034] like Figure 5 As shown, this embodiment is an example of the process of correcting isolated through holes. The process of determining the filling area in step S3 includes: step S31. determining the fillable range; step S32. determining the filling area in the fillable range. Figure 6(a) to Figure 6(e)In this embodiment, the method for determining the fillable range is: expand the interconnects in the first interconnect layer A and the second interconnect layer B by a preset distance to form the corresponding first interconnect range A1 and second interconnect range B1; subtract the overlapping areas of the first range 1, the first interconnect range A1 and the second interconnect range B1 from the first range 1, and record the obtained ranges as second ranges 2. Subtract the area whose width in the vertical direction is less than V from each second range 2, and record the obtained ranges as third ranges 3; subtract the area whose width in the horizontal direction is less than L from each third range 3, and record the obtained ranges as fillable ranges 4.

[0035] In the present embodiment, the interconnection line is a rectangle, and the interconnections in the first interconnection line layer A and the second interconnection line layer B are expanded by preset distances to form the corresponding first interconnection line range A1 and second interconnection line range B1. Specifically exemplified is: the straight line where the long side of the interconnection line is located is moved by a distance TSmin toward the outside of the interconnection line in a direction perpendicular to the long side; the straight line where the short side of the interconnection line is located is moved by a distance TTmin toward the outside of the interconnection line in a direction perpendicular to the short side; wherein TSmin refers to the minimum distance from the end of the interconnection line to the side of the adjacent interconnection line in the preset design rule (the minimum value of tip to side); and TTmin refers to the minimum distance from the end of the interconnection line to the end of the adjacent interconnection line in the preset design rule (the minimum value of tip to tip).

[0036] In this embodiment, in the same interconnection line layer (referring to the first interconnection line layer A or the second interconnection line layer B), if there is an overlap between the ranges formed by different interconnections expanding at the preset distances in this embodiment, the several ranges with overlapping parts are merged into one interconnection line range (referring to the first interconnection line range A1 or the second interconnection line range B1). The fillable range 4 in this embodiment is a polygon, not necessarily a rectangle, but the sides of the polygon are all horizontal or vertical sides.

[0037] As shown in FIG. 6(d) and FIG. 6(e), for each fillable range 4, a vertex of the fillable range 4 is selected; a horizontal side with a length equal to L and a vertical side with a length equal to V are respectively extended from the vertex into the fillable range; a rectangular range formed by the location of the vertex as a vertex angle and the horizontal side and the vertical side as the side is determined as a filling area 5. In this embodiment, there are multiple fillable ranges 4; in the example method, a filling area 5 is determined in each fillable range 4. In the example method of this embodiment, an auxiliary unit is filled in each filling area 5 to complete the correction of the isolated through hole. As shown in FIG. 6(f), the correction of the isolated through hole is achieved after the auxiliary unit is filled.

[0038] Some commonly used English nouns or letters used in the present invention for the sake of clarity are only used for exemplary references rather than restrictive interpretations or specific usages, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters. It should also be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0039] The above embodiments are only used to help understand the method and core idea of ​​the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for correcting isolated through holes in a layout, characterized in that: include: Step S1. Obtain layout information and determine the target through-hole layer; Step S2. by performing area expansion on the through hole of the target through hole layer, obtaining a through hole peripheral area of ​​the through hole; The through hole of the target through hole layer is judged: whether there are other through holes of the target through hole layer in the through hole peripheral area of ​​the through hole; if not, the through hole is judged to be an isolated through hole, and the through hole peripheral area of ​​the isolated through hole is recorded as a first range; Step S3. Correcting the isolated through hole searched out in step S2: determining a filling area within the first range of the isolated through hole, and filling the auxiliary unit in the filling area to complete the correction; The auxiliary unit comprises: a through hole of the target through hole layer, and a first interconnection line unit in a first interconnection line layer and a second interconnection line unit in a second interconnection line layer respectively connected to the through hole; wherein the first interconnection line layer and the second interconnection line layer are upper and lower interconnection line layers respectively connected to the target through hole layer; and the filling area satisfies that filling the auxiliary unit therein does not affect the interconnections in the first interconnection line layer and the second interconnection line layer; The process of determining the fill area includes: Step S31. Determine the fillable range; Step S32. Determine the filling area in the fillable range; The method for determining the fillable range is: the interconnects in the first interconnect layer and the second interconnect layer are expanded by preset distances to form corresponding first interconnect ranges and second interconnect ranges; several ranges obtained by subtracting the overlapping areas with the first interconnect range and the second interconnect range from the first range are recorded as second ranges; several ranges are obtained by subtracting the areas whose width in the vertical direction is less than V from the second range, which are recorded as third ranges; several ranges are obtained by subtracting the areas whose width in the horizontal direction is less than L from the third range, which are the fillable ranges; wherein L refers to the maximum length of the auxiliary unit in the horizontal direction, and V refers to the maximum length of the auxiliary unit in the vertical direction.

2. The method for correcting isolated vias in a layout according to claim 1, characterized in that: In the step S2, the through-hole peripheral area obtained after the through-hole in the target through-hole layer is expanded specifically refers to: a rectangular area formed by expanding the four sides of the through-hole after translating outwardly by a preset search distance.

3. The method for correcting isolated vias in a layout according to claim 1, characterized in that: The auxiliary unit adopts the auxiliary unit that occupies the smallest area under the condition of meeting the preset design rules.

4. The method for correcting isolated vias in a layout according to claim 1, characterized in that: The interconnection line is a rectangle, and the interconnection line is expanded by a preset distance to form a corresponding first interconnection line range and a second interconnection line range respectively by: moving a straight line where the long side of the interconnection line is located along a direction perpendicular to the long side by a distance TSmin toward the outside of the interconnection line; moving a straight line where the short side of the interconnection line is located along a direction perpendicular to the short side by a distance TTmin toward the outside of the interconnection line; The TSmin refers to the minimum distance from the end of the interconnection line to the edge of the adjacent interconnection line in the preset design rule; and the TTmin refers to the minimum distance from the end of the interconnection line to the end of the adjacent interconnection line in the preset design rule.

5. The method for correcting isolated vias in a layout according to claim 1, characterized in that: In the step S31, in the same interconnection line layer, if there are overlapping parts between the ranges formed by different interconnection lines expanding at the preset distances, the ranges are merged into one interconnection line range.

6. The method for correcting isolated vias in a layout according to claim 1, characterized in that: The fillable range is in the form of a polygon, and the sides of the polygon are all horizontal or vertical sides.

7. The method for correcting isolated vias in a layout according to claim 1, characterized in that: The method for determining the filling area in step S32 is: randomly select a vertex of the fillable range; extend a horizontal side with a length equal to L and a vertical side with a length equal to V from the vertex into the fillable range; and determine the rectangular range formed by the horizontal side and the vertical side as the filling area.

8. The method for correcting isolated vias in a layout according to claim 1, characterized in that: There are several fillable ranges; in step S32, a filling area is determined in each fillable range; and an auxiliary unit is filled in a filling area to complete the correction.

9. A correction system for isolated vias in a layout, characterized in that: It comprises a storage device and a processor; the storage device stores a plurality of instructions, and the instructions are suitable for being loaded by the processor and executed by the method for correcting isolated through holes in a layout as described in any one of claims 1-8.

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