Circuit layout detection method, device, equipment and medium

Abstract

The embodiments of the present application disclose a circuit layout detection method, device, equipment and medium for solving the problem of low efficiency of risk point detection in related technologies. In the embodiments of the present application, the distance between the same type of field oxygen is identified and analyzed. When the distance is small and different types of field oxygen are not injected, it is easy to cause parasitic transistors to be generated, resulting in reduced chip reliability. Therefore, the embodiments of the present application detect the distance between the same type of field oxygen and identify whether different types of field oxygen exist, thereby locating the risk points, automatically excluding risk-free places, and automatically detecting risk points for engineers to further verify, thereby improving detection efficiency.

Description

Technical Field

[0001] The present application relates to the field of circuit detection, and in particular to a circuit layout detection method, device, equipment and medium. Background Art

[0002] During chip use, there are risks of ESD (Electro-Static Discharge) and latchup, which seriously affect the reliability of the chip.

[0003] In order to improve the quality of chips, it is necessary to verify the electrical rules, process rules and discharge paths of the layout. In the related technology, the inspection method currently commonly used in the industry is to rely on the experience of engineers to visually check the layout to see if there are any risk points. However, the manual analysis method has two significant disadvantages. First, the judgment of hidden risks requires a certain experience basis, which places certain requirements on the experience of engineers. Second, with the increasing complexity of circuit design and the continuous increase in chip scale, the workload of manual analysis is very large, which can easily lead to omissions, thus laying the seeds of risk. Therefore, in the related technology, the detection method is not only inefficient, but also has low efficiency. Summary of the Invention

[0004] The purpose of this application is to provide a circuit layout detection method, device, equipment and medium to solve the problem of low efficiency in risk point detection in related technologies.

[0005] In a first aspect, the present application provides a circuit layout detection method, the method comprising:

[0006] Obtain target circuit layout;

[0007] Identifying the relative position relationship of a plurality of field oxides from the target circuit layout;

[0008] According to the relative position relationship, when it is identified that the distance between any two field oxygens of the same type is less than a preset distance and no heterotype field oxygen is injected between the two field oxygens of the same type, prompt information indicating that parasitic transistors exist between the two field oxygens of the same type is output.

[0009] In some embodiments, the method further comprises:

[0010] When the distance between the two field oxides of the same type is greater than or equal to the preset distance, it is determined that no parasitic transistor exists between the two field oxides of the same type.

[0011] In some embodiments, the method further comprises:

[0012] When the distance between the two field oxygens of the same type is less than the preset distance and a different type of field oxygen is implanted between the two field oxygens of the same type, it is determined that no parasitic transistor exists between the two field oxygens of the same type.

[0013] In some embodiments, before identifying the relative positional relationship of a plurality of field oxides from the target circuit layout, the method further includes:

[0014] Extracting a target field oxide layer to be detected from the target circuit layout;

[0015] The step of identifying the relative positional relationship of a plurality of field oxides from the target circuit layout includes:

[0016] The relative position relationship of a plurality of field oxygens is identified from the target field oxygen layer.

[0017] In some embodiments, extracting a target field oxide layer to be detected from the target circuit layout includes:

[0018] Extracting the following layers from the target circuit layout: a first layer NPOD obtained by performing a logical AND operation on all field oxygens and N-type implanted field oxygens, a second layer PPOD obtained by performing a logical AND operation on all field oxygens and P-type implanted field oxygens, a third layer OD_DMY obtained by subtracting all field oxygens from the device layer connected to all field oxygens OD_RAM ​​metals in the storage function area, a fourth layer OD_RAM ​​formed by all field oxygens contained in the RAM area with a storage function label, and a fifth layer NOD obtained by subtracting the N-well and the high-voltage well from the first layer;

[0019] The N-type field oxide layer NOD_CHECK is obtained by subtracting the OD_DMY from the NOD;

[0020] a sixth layer POD consisting of an intersection of a collection of the N-well and the high-voltage well and the PPOD;

[0021] A P-type field oxide layer POD_CHECK obtained by subtracting the OD_DMY from the POD;

[0022] Wherein, the target field oxide layer includes the NOD_CHECK and the POD_CHECK.

[0023] In some embodiments, different types of circuit layouts correspond to respective preset distances, and the preset distances corresponding to different types of current layouts are customizable.

[0024] In a second aspect, an embodiment of the present application further provides a circuit layout detection device, the device comprising:

[0025] An acquisition module, used to acquire a target circuit layout;

[0026] A position relationship determination module, configured to identify the relative position relationship of a plurality of field oxides from the target circuit layout;

[0027] The prompt module is used to output prompt information that parasitic transistors exist between any two field oxygens of the same type when it is identified that the distance between any two field oxygens of the same type is less than a preset distance and no heterotype field oxygen is injected between the two field oxygens of the same type according to the relative position relationship.

[0028] In some embodiments, the apparatus further comprises:

[0029] The exclusion module is configured to determine that no parasitic transistor exists between the two field oxides of the same type when the distance between the two field oxides of the same type is greater than or equal to the preset distance.

[0030] The exclusion module is further configured to determine that no parasitic transistor exists between the two field oxides of the same type when a distance between the two field oxides of the same type is less than a preset distance and a different type of field oxide is injected between the two field oxides of the same type.

[0031] In some embodiments, before identifying the relative positional relationship of a plurality of field oxides from the target circuit layout, the apparatus further comprises:

[0032] A target field oxide layer extraction module is used to extract a target field oxide layer to be detected from the target circuit layout;

[0033] The position relationship determination module is specifically configured to identify the relative position relationship of a plurality of field oxides in the target field oxide layer.

[0034] In some embodiments, the target field oxygen layer extraction module is specifically used to:

[0035] Extracting the following layers from the target circuit layout: a first layer NPOD obtained by performing a logical AND operation on all field oxygens and N-type implanted field oxygens, a second layer PPOD obtained by performing a logical AND operation on all field oxygens and P-type implanted field oxygens, a third layer OD_DMY obtained by subtracting all field oxygens from the device layer connected to all field oxygens OD_RAM ​​metals in the storage function area, a fourth layer OD_RAM ​​formed by all field oxygens contained in the RAM area with a storage function label, and a fifth layer NOD obtained by subtracting the N-well and the high-voltage well from the first layer;

[0036] The N-type field oxide layer NOD_CHECK is obtained by subtracting the OD_DMY from the NOD;

[0037] a sixth layer POD consisting of an intersection of a collection of the N-well and the high-voltage well and the PPOD;

[0038] A P-type field oxide layer POD_CHECK obtained by subtracting the OD_DMY from the POD;

[0039] Wherein, the target field oxide layer includes the NOD_CHECK and the POD_CHECK.

[0040] In some embodiments, different types of circuit layouts correspond to respective preset distances, and the preset distances corresponding to different types of current layouts are customizable.

[0041] In a third aspect, another embodiment of the present application further provides an electronic device comprising at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any circuit layout detection method provided in an embodiment of the present application.

[0042] In a fourth aspect, another embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores a computer program, and the computer program is used to enable a computer to execute any circuit layout detection method in the embodiments of the present application.

[0043] In the embodiments of this application, the distance between the same type of field oxygen is identified and analyzed. When the distance is small and different types of field oxygen are not injected, parasitic transistors are easily generated, which leads to reduced chip reliability. Therefore, the embodiments of this application detect the distance between the same type of field oxygen and identify whether different types of field oxygen are present, thereby locating risk points, automatically eliminating non-risk areas, and automatically detecting risk points for engineers to further verify, thereby improving detection efficiency.

[0044] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings introduced below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1a-Figure 1e is a schematic diagram of the relationship between devices according to one embodiment of the present application;

[0047] Figure 2 1 is a flow chart of a circuit layout detection method according to one embodiment of the present application;

[0048] Figure 3 This is a schematic diagram illustrating an interface according to an embodiment of the present application;

[0049] Figure 4 Schematic diagram of a circuit layout detection device according to one embodiment of the present application;

[0050] Figure 5 Schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to enable ordinary people in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0052] It should be noted that the terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with certain aspects of the present application as detailed in the appended claims.

[0053] The inventors' research has revealed that chips are often used in integrated circuits. Within integrated circuits, whether specifically designed or passively parasitic, if ESD or latch-up risks exist, a large number of PN junctions are unavoidable. These parasitic PN junctions can potentially lead to ESD and latch-up failures. To prevent unwanted parasitic transistor conduction, appropriate detection measures must be incorporated into the layout design. During the integrated circuit layout design process, to prevent internal failures caused by electrostatic discharge and latch-up, the layout must be verified for electrical rules, process rules, and discharge paths. Currently, the commonly used inspection method in the industry relies on engineers' experience to visually inspect the layout for risk points. Manual analysis methods, however, have two significant drawbacks. First, identifying hidden risks requires a certain level of experience, which places a high demand on engineers. Second, with the increasing complexity of circuit design and the continuous expansion of chip size, the workload for manual analysis is enormous, making it easy to miss errors, thus sowing the seeds of risk.

[0054] In view of this, in order to reduce the dependence of engineers in checking parasitic transistors, this application proposes a method for automatic detection of parasitic transistors. This method is simple and efficient, can automatically identify risk points and provide feedback to engineers for judgment, eliminate hidden dangers in the R&D stage, greatly improve R&D efficiency, and reduce the dependence of chip reliability on manual labor.

[0055] The inventive concept of this application is as follows: The inventors studied and analyzed the characteristics of circuits with parasitic transistors and found that when the distance between the same type of field oxides is small, or when the distance is close and different types of field oxides are not injected, parasitic transistors are likely to form, resulting in reduced chip reliability. Therefore, the embodiments of this application propose to detect the distance between the same type of field oxides and identify whether different types of field oxides are present, thereby locating risk points and providing further verification for engineers.

[0056] like Figure 1a The figure shows two devices placed close together. Because the two devices are so close and simply placed close together without any protective measures, the risk factor between the two devices is high, which can easily lead to reduced chip reliability.

[0057] like Figure 1b As shown, the difference between the two devices is Figure 1a Circuit diagram for long distances. When the two devices are far enough apart, the risk factor is low.

[0058] like Figure 1c As shown, relative to Figure 1a and Figure 1b For example, this diagram shows a guarding layer placed between two MOS (Metal-Oxide-Semiconductor) devices. Specifically, guarding is gradually inserted between the two devices, isolating the two OD layers of the same type, leaving an OD layer of the opposite type between them.

[0059] like Figure 1d The diagram below illustrates the principle of parasitic NPN between two ODs of the same type. Since the substrate of NMOS is PSUB (P-type substrate), the two N+ODs (i.e. Figure 1d There is a parasitic NPN in the N+ of the transistor. Due to the existence of the substrate resistance Rp, the parasitic NPN may be turned on (if it is PMOS here, a parasitic PNP is formed by two P+ and the substrate N+).

[0060] like Figure 1e The figure shows another principle diagram illustrating the existence of a parasitic NPN between two ODs of the same type. Figure 1e There is a parasitic NPN between two circuits with the same OD. The P-type guarding is grounded, and Rp is zero.

[0061] In summary, if the distance between two field oxygens of the same type is close or different types of field oxygen layers are not injected (hereinafter referred to as heterogeneous field oxygen), then the two field oxygens of the same type are risk points. Based on this, if Figure 2 FIG. 1 is a flow chart of a circuit layout detection method provided in an embodiment of the present application, and the method includes the following steps:

[0062] In step 201, a target circuit layout is obtained;

[0063] In step 202, the relative position relationship of multiple field oxides is identified from the target circuit layout;

[0064] In some embodiments, the target circuit layout can be pre-processed and simplified before identifying the relative positional relationships of multiple field oxides to improve detection efficiency. For example, a target field oxide layer to be detected can be first extracted from the target circuit layout; then, the relative positional relationships of multiple field oxides can be identified from the target field oxide layer. This method of determining the positional relationships of the target field oxide layer requires less information to be processed than processing the entire circuit layout, which can improve detection efficiency and accuracy.

[0065] In some embodiments, the target field oxide layer may be extracted based on the following method, which may be implemented as follows:

[0066] Step A1: Extracting the following layers from the target circuit layout: a first layer NPOD obtained by performing a logical AND operation on all field oxides and N-type implanted field oxides; a second layer PPOD obtained by performing a logical AND operation on all field oxides and P-type implanted field oxides; a third layer OD_DMY obtained by subtracting all field oxides from the device layer connected to the metal of all field oxides OD_RAM ​​in the memory function area; a fourth layer OD_RAM ​​formed by all field oxides contained in the RAM area with a memory function label; and a fifth layer NOD obtained by subtracting the N-well and the high-voltage well from the first layer.

[0067] Step A2: subtracting the OD_DMY from the NOD to obtain the N-type field oxide layer NOD_CHECK;

[0068] Step A3: forming a sixth layer POD consisting of an intersection of a collection of the N-well and the high-voltage well and the PPOD;

[0069] Step A4: obtaining a P-type field oxide layer POD_CHECK by subtracting the OD_DMY from the POD;

[0070] Wherein, the target field oxide layer includes the NOD_CHECK and the POD_CHECK.

[0071] In the embodiment of the present disclosure, by classifying and processing the elements in the corresponding circuit layout layer by layer, the target field oxide layer whose relative position relationship needs to be calculated can be extracted.

[0072] Of course, during implementation, the target field oxide layer can be extracted based on actual conditions, for example, based on the tool used to design the circuit layout and the layout analysis function it supports, which is applicable to the embodiments of the present application and is not limited in this application.

[0073] In some embodiments, the code for extracting the target field oxide layer may be as follows:

[0074] NPOD=OD AND NP / / All field oxides are logically ANDed with the N-type implanted field oxide to obtain the first layer NPOD;

[0075] PPOD=OD AND PP / / All field oxides and P-type implanted field oxides are logically ANDed to obtain the second layer PPOD

[0076] OD_DMY=(OD_RAM ​​NOT INTERACT CO) / / Extract the device layer that has metal connections with all field oxides in the storage function area, then subtract all field oxides to obtain the third layer OD_DMY. OD_RAM=OD INSIDERAM1 TDMY / / The fourth layer OD_RAM ​​is composed of all field oxides contained in the RAM area with storage function labels;

[0077] NOD=(NPOD NOT NWELL) NOT HVNW / / The fifth layer NOD is obtained by subtracting the N well and the high voltage well from the first layer;

[0078] NOD_CHECK=NOD NOT OD_DMY / / Subtract OD_DMY from NOD to get N-type field oxide layer NOD_CHECK

[0079] POD=PPOD AND (NWELL OR HVNW) / / The sixth layer POD is composed of the intersection of the N well and the high voltage well and the PPOD

[0080] POD_CHECK = POD NOT OD_DMY / / P-type field oxide layer POD_CHECK is obtained by subtracting the OD_DMY from the POD.

[0081] The target field oxide layer includes the NOD_CHECK and the POD_CHECK, thereby extracting the field oxide layer.

[0082] In short, we can run Boolean operations on the existing layers to get the layer we want: the diffusion layer we need to check. Therefore, the relative position relationship can be expressed as follows:

[0083]

[0084]

[0085] By assigning a specific value to X, it is possible to identify situations where the distance between two diffusions of the same type is less than X and there is no diffusion of a different type between them. This can be reported to the design engineer, replacing manual inspection, saving manpower, improving efficiency, and identifying paths where parasitic conduction may occur during the design phase, thereby improving chip yield and reducing reliability risks after tape-out. Therefore, in step 203, based on the relative positional relationship, when it is identified that the distance between any two field oxides of the same type is less than a preset distance and no field oxide of a different type has been injected between the two field oxides of the same type, a prompt indicating the presence of a parasitic transistor between the two field oxides of the same type can be output.

[0086] For example, Figure 3 The figure shows a schematic diagram of outputting prompt information. The prompt information can mark the location of the risk point in the circuit layout and indicate the presence of a potential parasitic transistor at that location, so that relevant personnel can further confirm it.

[0087] In another embodiment, the following two situations can be used to confirm that no parasitic transistors exist:

[0088] Case 1: When the distance between the two field oxides of the same type is greater than or equal to the preset distance, it is determined that no parasitic transistor exists between the two field oxides of the same type.

[0089] Case 2: When the distance between the two field oxides of the same type is less than the preset distance and a different type of field oxide is implanted between the two field oxides of the same type, it is determined that no parasitic transistor exists between the two field oxides of the same type.

[0090] Therefore, by automatically identifying the above two situations, circuit areas where no parasitic transistors exist can be excluded, that is, areas without risk points can be excluded, which can reduce the workload of staff and improve the efficiency of circuit layout detection.

[0091] In some embodiments, different circuit layouts may have different requirements for the preset distance. Therefore, in the embodiments of the present application, different types of circuit layouts correspond to their own preset distances during implementation, and the preset distances corresponding to different types of current layouts can be customized. In other words, during implementation, the preset distances used to detect whether the same type of field oxygen is a risk point can be customized and adjusted according to actual needs, making the detection method provided by this application applicable to different scenarios.

[0092] Based on the same inventive concept, a circuit layout detection device is proposed, such as Figure 4 As shown, the apparatus 400 includes:

[0093] An acquisition module 401 is used to acquire a target circuit layout;

[0094] A position relationship determination module 402 is used to identify the relative position relationship of multiple field oxides from the target circuit layout;

[0095] The prompt module 403 is configured to output a prompt message indicating that a parasitic transistor exists between any two same-type field oxides when it is identified that the distance between any two same-type field oxides is less than a preset distance and no hetero-type field oxide is injected between the two same-type field oxides according to the relative position relationship.

[0096] In some embodiments, the apparatus further comprises:

[0097] The exclusion module is configured to determine that no parasitic transistor exists between the two field oxides of the same type when the distance between the two field oxides of the same type is greater than or equal to the preset distance.

[0098] The exclusion module is further configured to determine that no parasitic transistor exists between the two field oxides of the same type when a distance between the two field oxides of the same type is less than a preset distance and a different type of field oxide is injected between the two field oxides of the same type.

[0099] In some embodiments, before identifying the relative positional relationship of a plurality of field oxides from the target circuit layout, the apparatus further comprises:

[0100] A target field oxide layer extraction module is used to extract a target field oxide layer to be detected from the target circuit layout;

[0101] The position relationship determination module is specifically configured to identify the relative position relationship of a plurality of field oxides in the target field oxide layer.

[0102] In some embodiments, the target field oxygen layer extraction module is specifically used to:

[0103] Extracting the following layers from the target circuit layout: a first layer NPOD obtained by performing a logical AND operation on all field oxygens and N-type implanted field oxygens, a second layer PPOD obtained by performing a logical AND operation on all field oxygens and P-type implanted field oxygens, a third layer OD_DMY obtained by subtracting all field oxygens from the device layer connected to all field oxygens OD_RAM ​​metals in the storage function area, a fourth layer OD_RAM ​​formed by all field oxygens contained in the RAM area with a storage function label, and a fifth layer NOD obtained by subtracting the N-well and the high-voltage well from the first layer;

[0104] The N-type field oxide layer NOD_CHECK is obtained by subtracting the OD_DMY from the NOD;

[0105] a sixth layer POD consisting of an intersection of a collection of the N-well and the high-voltage well and the PPOD;

[0106] A P-type field oxide layer POD_CHECK obtained by subtracting the OD_DMY from the POD;

[0107] Wherein, the target field oxide layer includes the NOD_CHECK and the POD_CHECK.

[0108] In some embodiments, different types of circuit layouts correspond to respective preset distances, and the preset distances corresponding to different types of current layouts are customizable.

[0109] The implementation and beneficial effects of each operation in the circuit layout detection device can be found in the description of the method above, which will not be repeated here.

[0110] After introducing the circuit layout detection method and apparatus according to an exemplary embodiment of the present application, an electronic device according to another exemplary embodiment of the present application will be introduced.

[0111] Those skilled in the art will appreciate that various aspects of the present application can be implemented as systems, methods, or program products. Therefore, various aspects of the present application can be specifically implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation that combines hardware and software aspects, which may be collectively referred to herein as a "circuit," "module," or "system."

[0112] In some possible implementations, an electronic device according to the present application may include at least one processor and at least one memory. The memory stores program code that, when executed by the processor, causes the processor to perform the steps of the image scaling method according to various exemplary embodiments of the present application described above. For example, the processor may perform steps such as those described in circuit layout detection.

[0113] Refer to the following Figure 5 The electronic device 130 according to this embodiment of the present application is described. Figure 5 The electronic device 130 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0114] like Figure 5 As shown, the electronic device 130 is a general electronic device. Components of the electronic device 130 may include, but are not limited to, the at least one processor 131, the at least one memory 132, and a bus 133 connecting different system components (including the memory 132 and the processor 131).

[0115] Bus 133 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a processor or local bus using any of a variety of bus architectures.

[0116] The memory 132 may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 1321 and / or a cache memory 1322 , and may further include a read-only memory (ROM) 1323 .

[0117] The memory 132 may also include a program / utility 1325 having a set (at least one) of program modules 1324, such program modules 1324 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0118] The electronic device 130 may also communicate with one or more external devices 134 (e.g., a keyboard, pointing device, etc.), one or more devices that enable a user to interact with the electronic device 130, and / or any device that enables the electronic device 130 to communicate with one or more other electronic devices (e.g., a router, a modem, etc.). Such communication may occur via an input / output (I / O) interface 135. Furthermore, the electronic device 130 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 136. As shown, the network adapter 136 communicates with other modules of the electronic device 130 via a bus 133. It should be understood that, although not shown, other hardware and / or software modules may be used in conjunction with the electronic device 130, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0119] In some possible implementations, various aspects of a circuit layout detection provided by the present application can also be implemented in the form of a program product, which includes program code. When the program product is run on a computer device, the program code is used to enable the computer device to execute the steps of a circuit layout detection method according to various exemplary embodiments of the present application described above in this specification.

[0120] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0121] The program product for circuit layout detection of the embodiment of the present application can be a portable compact disc read-only memory (CD-ROM) and include program code, and can be run on an electronic device. However, the program product of the present application is not limited thereto. In this document, a readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0122] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0123] Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0124] The program code for performing the operations of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user electronic device, partially on the user device, as a separate software package, partially on the user electronic device and partially on a remote electronic device, or entirely on the remote electronic device or server. In cases involving remote electronic devices, the remote electronic device can be connected to the user electronic device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external electronic device (for example, using an Internet service provider to connect through the Internet).

[0125] It should be noted that although several units or subunits of the device are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, depending on the embodiment of the application, the features and functions of two or more units described above can be embodied in a single unit. Conversely, the features and functions of a single unit described above can be further divided and embodied by multiple units.

[0126] Furthermore, although the operations of the method of the present application are described in a particular order in the accompanying drawings, this does not require or imply that the operations must be performed in this particular order, or that all illustrated operations must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0127] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0128] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable image scaling device to produce a machine, so that the instructions executed by the processor of the computer or other programmable image scaling device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0129] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable image scaling device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0130] These computer program instructions can also be loaded onto a computer or other programmable image scaling device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0131] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0132] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A circuit layout detection method, characterized in that: The method comprises: Obtain target circuit layout; Extracting the following layers from the target circuit layout: a first layer NPOD obtained by performing a logical AND operation on all field oxygens and N-type implanted field oxygens, a second layer PPOD obtained by performing a logical AND operation on all field oxygens and P-type implanted field oxygens, a third layer OD_DMY obtained by subtracting all field oxygens from the device layer connected to all field oxygens OD_RAM ​​metals in the storage function area, a fourth layer OD_RAM ​​formed by all field oxygens contained in the RAM area with a storage function label, and a fifth layer NOD obtained by subtracting the N-well and the high-voltage well from the first layer; The N-type field oxide layer NOD_CHECK is obtained by subtracting the OD_DMY from the NOD; a sixth layer POD consisting of an intersection of a collection of the N-well and the high-voltage well and the PPOD; A P-type field oxide layer POD_CHECK obtained by subtracting the OD_DMY from the POD; Wherein, the target field oxide layer includes the NOD_CHECK and the POD_CHECK; Identifying the relative position relationship of multiple field oxygens from the target field oxygen layer; According to the relative position relationship, when it is identified that the distance between any two field oxygens of the same type is less than a preset distance and no heterotype field oxygen is injected between the two field oxygens of the same type, prompt information indicating that parasitic transistors exist between the two field oxygens of the same type is output.

2. The method according to claim 1, characterized in that The method further comprises: When the distance between the two field oxides of the same type is greater than or equal to the preset distance, it is determined that no parasitic transistor exists between the two field oxides of the same type.

3. The method according to claim 1, characterized in that The method further comprises: When the distance between the two field oxygens of the same type is less than the preset distance and a different type of field oxygen is implanted between the two field oxygens of the same type, it is determined that no parasitic transistor exists between the two field oxygens of the same type.

4. The method according to claim 1, wherein Different types of circuit layouts correspond to their own preset distances, and the preset distances corresponding to different types of current layouts can be customized.

5. A circuit layout detection device, characterized in that: The device comprises: An acquisition module, used to acquire a target circuit layout; a positional relationship determination module, configured to extract the following layers from the target circuit layout: a first layer NPOD obtained by performing a logical AND operation on all field oxides and N-type implanted field oxides, a second layer PPOD obtained by performing a logical AND operation on all field oxides and P-type implanted field oxides, a third layer OD_DMY obtained by subtracting all field oxides from the device layer metal-connected to all field oxides OD_RAM ​​in the storage function area, a fourth layer OD_RAM ​​formed by all field oxides contained in the RAM area with a storage function label, and a fifth layer NOD obtained by subtracting the N-well and the high-voltage well from the first layer; The N-type field oxide layer NOD_CHECK is obtained by subtracting the OD_DMY from the NOD; a sixth layer POD consisting of an intersection of a collection of the N-well and the high-voltage well and the PPOD; A P-type field oxide layer POD_CHECK obtained by subtracting the OD_DMY from the POD; Wherein, the target field oxide layer includes the NOD_CHECK and the POD_CHECK; Identifying the relative position relationship of multiple field oxygens from the target field oxygen layer; The prompt module is used to output prompt information that parasitic transistors exist between any two field oxygens of the same type when it is identified that the distance between any two field oxygens of the same type is less than a preset distance and no heterotype field oxygen is injected between the two field oxygens of the same type according to the relative position relationship.

6. The device according to claim 5, characterized in that The device further comprises: an exclusion module, configured to determine that no parasitic transistor exists between the two field oxides of the same type when the distance between the two field oxides of the same type is greater than or equal to the preset distance; The exclusion module is further configured to determine that no parasitic transistor exists between the two field oxides of the same type when a distance between the two field oxides of the same type is less than a preset distance and a different type of field oxide is injected between the two field oxides of the same type.

7. An electronic device, characterized in that: The invention comprises at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 4.

8. A computer storage medium, characterized in that The computer storage medium stores a computer program, and the computer program is used to enable a computer to execute the method according to any one of claims 1 to 4.

Images