Semiconductor structure and method of forming the same

Abstract

The present application provides a semiconductor structure, comprising: a die pad; a semiconductor die on the die pad; a plurality of leads disposed around the die pad, each lead comprising an inner lead separate from the die pad and an outer lead connected to an end of the inner lead, the outer lead being further away from the die pad than the inner lead; a sealant covering the semiconductor die, the die pad and the leads, a lower end of the sealant having at least one opening, a lower surface of a wire bonding area of the inner lead of the lead being exposed by the corresponding opening and covered by a coating; and a second plating layer covering lower surfaces and sidewalls of the die pad and the outer lead of the lead. The present application aims to provide a semiconductor structure and a forming method thereof to improve the yield of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods for forming the same. Background Technology

[0002] The Quad Flat No Leads (QFN) package is a packaging technology that uses a lead frame and is close to a chip-size package (CSP). This package structure exposes the leads directly outside the molding compound, unlike the traditional Quad Flat Package (QFP) where the leads extend outward from the molding compound. This reduces the area occupied on the circuit board (PCB) and results in a thinner and smaller design. Summary of the Invention

[0003] In view of the problems existing in related technologies, the purpose of this invention is to provide a semiconductor structure and a method for forming the same, so as to at least improve the yield of the semiconductor structure.

[0004] To achieve the above objectives, the present invention provides a semiconductor structure comprising: a die pad; a semiconductor die located on the die pad; a plurality of pins disposed around the die pad, each pin including an internal pin separate from the die pad and an external pin connected to the end of the internal pin, the external pin being farther away from the die pad than the internal pin; a sealant covering the semiconductor die, the die pad, and the pins, the lower end of the sealant having at least one opening, the lower surface of the wire bonding area of ​​the internal pin of the pin being exposed through a corresponding opening and covered by a coating; and a plating layer covering the lower surface and sidewalls of the die pad and the external pin of the pin.

[0005] In some embodiments, the lower end of the wire bonding area of ​​the pin is an etched area.

[0006] In some embodiments, the coating is recessed upward relative to the lower surface of the sealant.

[0007] In some embodiments, the opening created by the sealant in the bottom view is a circular opening.

[0008] In some embodiments, the lower surface of the sealant is higher than the lower surface of the pin.

[0009] In some embodiments, the coating also contacts the lower surface of the sealant.

[0010] In some embodiments, it also includes: wires, wire bonding areas of internal pins of the semiconductor die that are electrically connected to the pins by the wires.

[0011] In some embodiments, the plating is electroplated tin.

[0012] In some embodiments, the outer wall of the second plating layer is coplanar with the outer wall of the pin.

[0013] In some embodiments, the coating includes a solder resist.

[0014] In some embodiments, the method includes: forming a first plating on the lower surface of a leadframe, the leadframe including a die pad, a plurality of pins surrounding the die pad, and a connecting dam connecting the die pad and the pins, each pin including an inner pin separate from the die pad and an outer pin connected to the end of the inner pin, the outer pin being farther away from the die pad than the inner pin; forming a sealant on the leadframe; removing the first plating on the lower surface of the connecting dam; removing the connecting dam to form an opening at the lower surface of the sealant; removing the remaining first plating; forming a coating in the opening; and forming a second plating on the outer pin of the pin and the lower surface of the die pad.

[0015] In some embodiments, a laser process is used to remove the first coating located on the lower surface of the connecting dam.

[0016] In some embodiments, an etching process is used to remove the connecting dam.

[0017] In some embodiments, a laser process is used to remove the remaining first coating on the lower surface of the connecting dam.

[0018] In some embodiments, the thickness of the inner pin is less than the thickness of the outer pin.

[0019] In some embodiments, after the connecting dam is removed, the die pad and pins are separated by a sealant.

[0020] In some embodiments, the semiconductor die is formed on a die pad and is covered with a sealant.

[0021] In some embodiments, the second coating contacts the sealant.

[0022] In some embodiments, after the second plating layer is formed, the pin and the second plating layer located on the lower surface of the pin are cut longitudinally.

[0023] In some embodiments, after the cutting is completed, the outer wall of the pin is flush with the outer wall of the second plating. Attached Figure Description

[0024] Figures 1A to 3 A schematic diagram of a prior art semiconductor structure is shown.

[0025] Figures 4 to 10 A schematic diagram of a semiconductor structure according to an embodiment of this application is shown. Detailed Implementation

[0026] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0027] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0028] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0029] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0030] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0031] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0032] See Figures 1A to 3 The cutting of QFN package structures can be divided into two processes: punching and sawing. For the sawing process, the longer the finger (the thinner portion within the external pin 202 that connects to the connecting dam 203) in the QFN, the better. This effectively reduces the length of the wire bond (which electrically connects the finger to the die). Figure 1B The length of the center lead 206 is reduced to lower process costs. Existing long fingers are formed by partial etching from the back side to prevent exposure during subsequent embedding within the packaging molding compound. However, a larger partial etching area means a thinner finger, increasing the likelihood of deformation and potentially posing structural risks. A connecting bar 203, connected to the die paddle 201, can be formed on the back side of the long finger during lead frame fabrication. This provides support for the long finger, enabling increased finger length and reducing wire bonding tolerances, thus improving wire bonding process performance. The connecting bar 203 is etched away after molding and forms solder resist between the external pin 202 and the die paddle 201.

[0033] Existing QFNs use a pre-plated frame (PPF) 210 to cover the bottom during fabrication for protection (acting as an etch stop layer to protect the external pins 202 and die pads 201 during subsequent etching of the connection dam). However, the existing technology suffers from incomplete PPF coverage, resulting in over-etching of the external pins 202 and die pads 201 not covered by PPF 210. The reason for this is, see [link to relevant documentation] Figure 2A The photomask 212 used when forming PPF 210 cannot precisely cover the edge (dashed line L) of the external pin 202. The photomask 212 may cover the body of the external pin 202, causing... Figure 2B The PPF 210 formed during the process (e.g., by electroplating) does not completely cover the external pin 202, such as Figure 3 The electron microscope image shows that after the subsequent etching process (in Figure 1B When the connecting dam 203 has been etched away, it will cause over-etching of the external pin 202.

[0034] The semiconductor structure and its formation method of this application will be described in detail below with reference to the accompanying drawings.

[0035] See Figure 4 A first plating layer 12 is formed on the lower surface of the lead frame 10. The lead frame 10 includes a die pad 100, a plurality of leads 102 located around the die pad 100, and a connecting dam 104 connecting the die pad 100 and the leads 102. Each lead 102 includes an inner lead 1020 separated from the die pad 100 and an outer lead 1022 connected to the end of the inner lead 1020. The outer lead 1022 is farther away from the die pad 100 than the inner lead 1020. A semiconductor die 14 and a sealant 16 covering the semiconductor die 14 are formed on the lead frame 10. The semiconductor die 14 is located on the die pad 100. In some embodiments, the semiconductor die 14 is electrically connected to the inner lead 1020 (wire bonding area) of the lead 12 via a lead wire, the cross-section of which is not shown. In some embodiments, the internal pin 1020 is formed to be thinner than the external pin 1022 by back-side etching. In some embodiments, a sealant 16 is also formed on the underside of the internal pin 1020. In some embodiments, the lead frame 10 is a single piece. In some embodiments, the material of the lead frame 10 includes Fe, Ni, Cu, or alloys thereof. Figure 4 The cross-section of the lead frame 10 shown is an axisymmetric shape. In some embodiments, the semiconductor die 14 may be a power die, etc. In some embodiments, the first plating layer 12 is electroplated tin. Since the first plating layer 12 of this application is formed by an electroplating process, the first plating layer 12 can cover all exposed surfaces of the pin 102, preventing the pin 102 from being exposed in subsequent (see...) Figure 6 The sealant 16 is damaged during the etching process. In some embodiments, the sealant 16 is an epoxy molding compound (EMC). Figure 4 Only the left and right pins 102 are shown in the image. In other views, multiple pins are connected by a connecting dam 104 and surround the die pad 100.

[0036] In this application, the sealant 16 is used to mold the lead frame 10 onto the release film, and the lead frame 10 is embedded in the release film, such that the bottom surface of the sealant 16 is higher than the bottom surface of the lead frame 10. Therefore, the inner sidewall of the outer pin 1022 of the lead 102 is exposed by the sealant 16, and then the subsequently formed first plating layer 12 covers the exposed inner sidewall and contacts the sealant 16 upwards. The surfaces of the pins 102 in this application are not exposed (this figure uses a single unit of lead frame 10 as an example; in actual production, multiple units of lead frames are connected, and in this case, the left and right outer sidewalls of the lead frame 10 in the figure are not exposed). The inner sidewall of the lead frame 10 in this application is also covered, so that the pins 102 are not damaged from the inner sidewall during subsequent etching.

[0037] Figures 5 to 9 by Figure 4 The left half of the structure is shown in the diagram. See also... Figure 5 Remove (e.g., by laser process) the first coating 12 located on the bottom surface of the connecting dam 104.

[0038] See Figure 6 The connection dam 104 is removed (e.g., by an etching process) to form an opening 30 on the lower surface of the sealant 16, exposing the upper half of the sealant 16. In some embodiments, the remaining first plating layer 12 serves as an etching stop layer to prevent damage to the outer pin 1022 of the pin 102 during the removal of the connection dam 104. In some embodiments, in a bottom view, the opening 30 in the sealant 16 is a circular, elliptical, or near-circular opening. After the connection dam 104 is removed, the die pad 100 and the inner pin 1022 of the pin 102 are separated by the sealant 16.

[0039] See Figure 7 ,exist Figure 6 After the steps shown, the first coating 12 may be damaged, so the remaining first coating 12 is removed (e.g., by laser process), and a second coating 60 is subsequently formed (see...). Figure 9 ).

[0040] See Figure 8 A coating 50 is formed in the opening 30, which prevents the internal pins 1020 from being exposed to the lower end of the die pad 100. In some embodiments, the coating 50 is a solder resist coating (SRC) / solder mask. The coating 50 is recessed upward relative to the lower surface of the sealant 16.

[0041] See Figure 9 A second plating layer 60 is formed on the lower surface of the outer pin 1022 of the pin 102. In some embodiments, the second plating layer 60 is electroplated tin, and the second plating layer 60 also covers the inner sidewall of the outer pin 1022 and contacts the sealant 16. Figures 4 to 9 The diagram shows the semiconductor structure of a single unit and its left half. In actual production, multiple... Figure 4 The structures shown are formed together and interconnected, in Figure 9 After the steps shown are completed, a monolithization process (e.g., dicing) is performed to form a monolithic semiconductor structure. Figure 9The left side of the structure is a cross-section, and the outer sidewall of the second plating layer 60 is coplanar with the outer sidewall of the sealant 16. In some embodiments, the semiconductor structure of this application can be connected to the circuit board (PCB) by forming solder balls on the second plating layer 60. Since the second plating layer 60 of this application covers the outer pin 1022 and the inner sidewall of the die pad 100, the contact area between the second plating layer 60 and the outer pin 1022 and the die pad 100 is increased, so as to have better bonding with the PCB.

[0042] Figure 10 A partial electron microscope image of the semiconductor structure of this application is shown, which shows that the coating 50 has been formed and the edges of the pins 102 of this application are intact and undamaged.

[0043] This application provides a leadframe packaging structure that primarily replaces the existing PPF layer with electroplated tin. In this application's packaging process, after molding with sealant 16 / molding compound, electroplated tin is formed on the exposed bottom surface of the leadframe 10. Since the electroplated tin can completely cover the pins 102 that do not require etching, there is no over-etching problem caused by incomplete coverage in traditional PPF packaging, effectively improving the defect rate from 100% to 0%. This application's embodiments also allow for the increase of internal pins 1020 of the pins 102 through the application of connection dams, thereby reducing the wire bonding length (less than 2.3 mm) and lowering process costs.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A first plating is formed on the lower surface of a lead frame, the lead frame including a die pad, a plurality of pins located around the die pad, and a connecting dam connecting the die pad and the pins, each pin including an inner pin separate from the die pad and an outer pin connected to the end of the inner pin, the outer pin being farther away from the die pad than the inner pin, the first plating covering the lower surface and sidewalls of the die pad and the outer pins, and a sealant being formed on the lead frame, wherein the first plating is formed after the sealant is formed on the lead frame; After the first coating is formed, the first coating located on the lower surface of the connecting dam is removed; After removing the first coating on the lower surface of the connecting dam, the connecting dam is removed to form an opening at the lower surface of the sealant; After the opening is formed, the remaining first coating is removed; After the remaining first coating is removed, a coating is formed in the opening; After the coating is formed, a second plating layer is formed on the outer pin of the pin and the lower surface of the die pad.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first coating on the lower surface of the connecting dam is removed using a laser process.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The connecting dam was removed using an etching process.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The remaining first coating on the lower surface of the connecting dam is removed using a laser process.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness of the inner pin of the pin is less than the thickness of the outer pin.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, After the connecting dam is removed, the core pad and the pin are separated by the sealant.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The semiconductor die is formed on the die pad and is covered by the sealant.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The second coating contacts the sealant.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, After the second plating layer is formed, the pin and the second plating layer located on the lower surface of the pin are cut longitudinally.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, After the cutting is completed, the outer wall of the pin is flush with the outer wall of the second plating layer.

Images