Level shifting circuit

Abstract

A level conversion circuit. The level conversion circuit comprises an input sub-circuit, an isolation sub-circuit and an output sub-circuit; wherein the input sub-circuit comprises a first NMOS tube, a second NMOS tube and an inverter; the output sub-circuit comprises a first PMOS tube and a second PMOS tube; the first NMOS tube and the second NMOS tube are connected with the isolation sub-circuit at the source and the drain; the isolation sub-circuit is connected with the drain of the first PMOS tube and the second PMOS tube; the threshold voltage of the first NMOS tube and the second NMOS tube is smaller than the threshold voltage of the first PMOS tube and the second PMOS tube; the isolation sub-circuit is used for connecting the input sub-circuit and the output sub-circuit and providing the corresponding drain voltage for the first NMOS tube and the second NMOS tube. The above scheme can improve the level conversion speed of the level conversion circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuit, in particular to a level conversion circuit. BACKGROUND

[0002] The semiconductor memory usually has a level conversion circuit for converting logic level into a required high voltage or low voltage.

[0003] In the existing level conversion circuit, the complementary metal oxide semiconductor (CMOS) tube used is a high-voltage CMOS tube. The so-called high-voltage CMOS tube is a CMOS tube that can be used to transmit high voltage, and the high voltage is at least greater than the input logic level value. The typical value (Vt) of the threshold voltage of the high-voltage CMOS tube is about 1.0V, and some can even be greater than 1.0V.

[0004] Since the saturation current value of the CMOS tube is inversely proportional to the threshold voltage of the MOS tube, the higher the threshold voltage of the CMOS tube, the smaller the saturation current value of the CMOS tube, and the smaller the current flowing through the CMOS tube during the level conversion, thereby resulting in a long flip time and slow level conversion speed of the existing level conversion circuit. SUMMARY

[0005] The technical problem solved by the present application is to improve the level conversion speed of the level conversion circuit.

[0006] To solve the above technical problem, the embodiment of the present application provides a level conversion circuit, which comprises: an input sub-circuit, an isolation sub-circuit and an output sub-circuit; wherein the input sub-circuit comprises: a first NMOS tube, a second NMOS tube and an inverter; the output sub-circuit comprises: a first PMOS tube and a second PMOS tube;

[0007] The gate of the first NMOS tube is connected with a logic signal output end and an input end of the inverter; the output end of the inverter is connected with the gate of the second NMOS tube; the source of the first NMOS tube and the second NMOS tube is grounded, and the drain is connected with the isolation sub-circuit; the isolation sub-circuit is connected with the drain of the first PMOS tube and the second PMOS tube; the gate of the first PMOS tube is connected with the drain of the second PMOS tube, and the gate of the second PMOS tube is connected with the drain of the first PMOS tube; the source of the first PMOS tube and the second PMOS tube is connected with a power voltage output end;

[0008] The threshold voltage of the first NMOS transistor and the second NMOS transistor is less than the threshold voltage of the first PMOS transistor and the second PMOS transistor; and the isolation sub-circuit is configured to connect the input sub-circuit and the output sub-circuit and provide a corresponding drain voltage for the first NMOS transistor and the second NMOS transistor.

[0009] Optionally, the isolation sub-circuit comprises a third NMOS transistor and a fourth NMOS transistor.

[0010] The gate of the third NMOS transistor and the fourth NMOS transistor is connected to a power voltage output terminal; the source of the third NMOS transistor is connected to the drain of the first NMOS transistor; the source of the fourth NMOS transistor is connected to the drain of the second NMOS transistor; the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor; and the drain of the fourth NMOS transistor is connected to the drain of the second PMOS transistor.

[0011] The threshold voltage of the third NMOS transistor and the fourth NMOS transistor is less than the threshold voltage of the first NMOS transistor and the second NMOS transistor.

[0012] Optionally, the typical value of the threshold voltage of the third NMOS transistor and the fourth NMOS transistor is greater than or equal to 0V and less than or equal to 0.2V.

[0013] Optionally, the level conversion circuit further comprises a fifth NMOS transistor, the fifth NMOS transistor is connected in parallel with the first PMOS transistor, and the gate of the fifth NMOS transistor is connected to the output terminal of the inverter.

[0014] Optionally, the level conversion circuit further comprises a sixth NMOS transistor, the sixth NMOS transistor is connected in parallel with the second PMOS transistor, and the gate of the sixth NMOS transistor is connected to the logic signal output terminal.

[0015] Optionally, the typical value of the threshold voltage of the fifth NMOS transistor and the sixth NMOS transistor is greater than or equal to 1V.

[0016] Optionally, the typical value of the threshold voltage of the first PMOS transistor and the second PMOS transistor is greater than or equal to 1.

[0017] Optionally, the typical value of the threshold voltage of the first NMOS transistor and the second NMOS transistor is greater than or equal to 0.7V and less than or equal to 0.8V.

[0018] Optionally, the inverter is composed of CMOS transistors.

[0019] Optionally, the typical value of the threshold voltage of the CMOS transistor in the inverter is greater than or equal to 0.7V and less than or equal to 0.8V.

[0020] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0021] With the above scheme, since one end of the isolation sub-circuit is connected with the drain of the first NMOS tube and the second NMOS tube, and the other end is connected with the drain of the first PMOS tube and the second PMOS tube, and the isolation sub-circuit can be connected with the input sub-circuit and the output sub-circuit, the isolation sub-circuit can convert the drain voltage of the first PMOS tube and the second PMOS tube into a drain voltage suitable for the first NMOS tube and the second NMOS tube, and when the threshold voltage of the first NMOS tube and the second NMOS tube is less than the threshold voltage of the first PMOS tube and the second PMOS tube, compared with the case that the threshold voltage of the first PMOS tube and the second PMOS tube is equal to the threshold voltage of the first NMOS tube and the second NMOS tube, the scheme of the present application can make the current flowing from the input sub-circuit to the output sub-circuit larger, thereby improving the level conversion speed.

[0022] Further, by arranging the fifth NMOS tube or the sixth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are both connected with the input sub-circuit, thereby further improving the speed of charging and discharging of the output end, and further improving the level conversion speed. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a structural schematic diagram of a level conversion circuit;

[0024] Figure 2 is a structural schematic diagram of a level conversion circuit in an embodiment of the present application;

[0025] Figure 3 is a structural schematic diagram of another level conversion circuit in an embodiment of the present application;

[0026] Figure 4 is Figure 1 is a comparison diagram of simulation results of level conversion speeds between the level conversion circuit in the prior art and the level conversion circuit in the present application. DETAILED DESCRIPTION

[0027] Figure 1 is a structural schematic diagram of a prior art level conversion circuit. Referring to Figure 1 , the circuit conversion circuit 10 can include an inverter 11, a first MOS tube P1, a second MOS tube P2, a third MOS tube N1 and a fourth MOS tube N2. Among them, the first MOS tube P1 and the second MOS tube P2 are PMOS tubes, and the third MOS tube N1 and the fourth MOS tube N2 are NMOS tubes.

[0028] The input end of the inverter 11 and the gate of the third MOS transistor N1 are connected with the logic signal output end IN. The drain of the third MOS transistor N1 is connected with the drain of the first MOS transistor P1. The gate of the fourth MOS transistor N2 is connected with the output end of the inverter 11. The source of the fourth MOS transistor N2 and the source of the third MOS transistor N1 are both connected to the ground VSS. The sources of the first MOS transistor P1 and the second MOS transistor P2 are both connected with the power voltage output end VDD. The gate of the first MOS transistor P1 is connected with the drain of the second MOS transistor P2 and the drain of the fourth MOS transistor N2. The gate of the second MOS transistor P2 is connected with the drain of the first MOS transistor P1.

[0029] When the voltage of the logic signal outputted by the logic signal output end IN is high, the third MOS transistor N1 is turned on, the fourth MOS transistor N2 is turned off, so that the gate voltage of the second MOS transistor P2 is low, and the second MOS transistor P2 is turned on, and the output end out outputs a voltage value close to the voltage outputted by the power voltage output end VDD, i.e. high.

[0030] When the voltage of the logic signal outputted by the logic signal output end IN is low, the third MOS transistor N1 is turned off, the fourth MOS transistor N2 is turned on, so that the gate voltage of the first MOS transistor P1 is low, and the first MOS transistor P1 is turned on, and at this time, the output end out outputs a low voltage value.

[0031] In the above-mentioned circuit conversion circuit 10, the first MOS transistor P1 and the second MOS transistor P2 are both directly connected with the power voltage output end VDD, so the first MOS transistor P1 and the second MOS transistor P2 need to be high-voltage transistors, so as to work normally under high-voltage conditions.

[0032] Since the third MOS transistor N1 is directly connected with the first MOS transistor P1, and the fourth MOS transistor N2 is directly connected with the second MOS transistor P2, so the third MOS transistor N1 and the fourth MOS transistor N2 also work under high-voltage conditions, and therefore the third MOS transistor N1 and the fourth MOS transistor N2 should also be high-voltage transistors.

[0033] In a specific implementation, the CMOS transistor can be adjusted by adjusting the thickness of the gate oxide layer inside the CMOS transistor and the process conditions, so as to make the CMOS transistor a high-voltage CMOS transistor. Generally, the threshold voltage of the high-voltage CMOS transistor is relatively high, and its typical value is about 1.0V, and in a severe case, it can reach more than 1.0V.

[0034] The saturation current value of the CMOS tube is inversely proportional to the threshold voltage of the CMOS tube, and because the threshold voltage of the high-voltage CMOS tube is high, the current flowing through the high-voltage CMOS tube is small in the level conversion process, thereby causing the level conversion circuit 10 to take a long time to charge the output end, so as to make the output end out reach the required conversion voltage, that is, the flip time of the level conversion circuit is long, and thus the level conversion speed is slow.

[0035] In order to solve the above problems, the embodiment of the present application provides a level conversion circuit, wherein an isolation sub-circuit is arranged in the level conversion circuit, one end of the isolation sub-circuit is connected with an input sub-circuit, the other end of the isolation sub-circuit is connected with an output sub-circuit, and the isolation sub-circuit can communicate the input sub-circuit and the output sub-circuit, so that the isolation sub-circuit can isolate the high voltage output by the power supply voltage output end, and the input sub-circuit can work at a lower voltage, so that the NMOS tube in the input sub-circuit can select the NMOS tube with a threshold voltage smaller than the threshold voltage of the PMOS tube in the output sub-circuit. The threshold voltage of the NMOS tube in the input sub-circuit is reduced, the current flowing through the NMOS tube in the input sub-circuit is increased, and then the current output by the output sub-circuit is increased, the charging speed of the input end is improved, and finally the level conversion speed is improved.

[0036] In order to make the above-mentioned purposes, characteristics and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0037] Reference Figure 2 The embodiment of the present application provides a level conversion circuit 20 for converting the voltage value of an input logic signal into a required voltage value. In the embodiment of the present application, the voltage value of the input logic signal is smaller than the converted voltage value, that is, the level conversion circuit 20 is used to convert a low-voltage logic signal into a high-voltage logic signal.

[0038] Specifically, the level conversion circuit 20 can include an input sub-circuit 21, an isolation sub-circuit 22 and an output sub-circuit 23.

[0039] The input sub-circuit 21 can include a first NMOS tube K1, a second NMOS tube K2 and an inverter 211. The output sub-circuit 23 can include a first PMOS tube M1 and a second PMOS tube M2.

[0040] The gate of the first NMOS transistor K1 is connected with the logic signal output terminal IN and the input terminal C of the inverter 211; the output terminal D of the inverter 211 is connected with the gate of the second NMOS transistor K2. The source of the first NMOS transistor K1 and the second NMOS transistor K2 is connected with the ground, and the drain is connected with the isolation sub-circuit 22. The isolation sub-circuit 22 is connected with the drain of the first PMOS transistor M1 and the second PMOS transistor M2. The gate of the first PMOS transistor M1 is connected with the drain of the second PMOS transistor M2, and the gate of the second PMOS transistor M2 is connected with the drain of the first PMOS transistor M1. The source of the first PMOS transistor M1 and the second PMOS transistor M2 is connected with the power voltage output terminal VDD.

[0041] The threshold voltage of the first NMOS transistor K1 and the second NMOS transistor K2 is less than the threshold voltage of the first PMOS transistor M1 and the second PMOS transistor M2. The isolation sub-circuit 22 is used to connect the input sub-circuit 21 and the output sub-circuit 23, and provide the appropriate drain voltage for the first NMOS transistor K1 and the second NMOS transistor K2.

[0042] Since the isolation sub-circuit 22 can connect the input sub-circuit 21 and the output sub-circuit 23, and can provide the appropriate drain voltage for the first NMOS transistor K1 and the second NMOS transistor K2, the level conversion circuit 20 can be enabled to perform level conversion. And since the threshold voltage of the first NMOS transistor K1 and the second NMOS transistor K2 is less than the threshold voltage of the first PMOS transistor M1 and the second PMOS transistor M2, the current value flowing through the input sub-circuit 21 is larger, so that the output terminal out can be quickly charged, and the voltage value of the output terminal out can reach the required conversion voltage as soon as possible, effectively improving the level conversion speed.

[0043] In a specific implementation, the voltage value output by the power voltage output terminal VDD is greater than 1.2V, which can be 3.3V, 5V or 10V, etc. The actual converted voltage value can be set according to the actual converted voltage value.

[0044] In a specific implementation, the threshold voltage of the first NMOS transistor K1 and the second NMOS transistor K2 is less than the threshold voltage of the first PMOS transistor M1 and the second PMOS transistor M2.

[0045] The threshold voltage of the first PMOS transistor M1 and the threshold voltage of the second PMOS transistor M2 can be the same or different. The threshold voltage of the first NMOS transistor K1 and the threshold voltage of the second NMOS transistor K2 can be the same or different, but as long as it is less than the threshold voltage of the first PMOS transistor M1 and the threshold voltage of the second PMOS transistor M2.

[0046] The threshold voltage of the first PMOS tube M1 and the second PMOS tube M2 is a high-voltage CMOS tube, and the typical value of the threshold voltage is about 1.0V, and can be greater than 1.0V. Correspondingly, the first NMOS tube K1 and the second NMOS tube K2 can be selected as a low-voltage CMOS tube, that is, a MOS tube capable of normal operation under a lower working voltage. The low voltage can be 0.8V or even lower. The typical value of the threshold voltage of the first NMOS tube K1 and the second NMOS tube K2 can be greater than or equal to 0.7V and less than or equal to 0.8V.

[0047] In a specific implementation, the MOS gate oxide layer thickness and the corresponding process conditions can be adjusted to form a low-voltage CMOS tube or a high-voltage CMOS tube.

[0048] In a specific implementation, the isolation sub-circuit 22 can be implemented in various circuit structures, and the specific implementation is not limited as long as the working voltage of the input sub-circuit 21 and the output sub-circuit 23 can be isolated.

[0049] In an embodiment of the present application, the isolation sub-circuit 22 can include a third NMOS tube K3 and a fourth NMOS tube K4. Wherein:

[0050] The gate of the third NMOS tube K3 and the fourth NMOS tube K4 is connected with the power supply voltage output end VDD. The source of the third NMOS tube K3 is connected with the drain of the first NMOS tube K1. The source of the fourth NMOS tube K4 is connected with the drain of the second NMOS tube K2. The drain of the third NMOS tube K3 is connected with the drain of the first PMOS tube M1. The drain of the fourth NMOS tube K4 is connected with the drain of the second PMOS tube M2. The threshold voltage of the third NMOS tube K3 and the fourth NMOS tube K4 is less than the threshold voltage of the first NMOS tube K1 and the second NMOS tube K2.

[0051] In an embodiment of the present application, the threshold voltage of the third NMOS tube K3 and the threshold voltage of the fourth NMOS tube K4 can be the same or different, as long as they are less than the threshold voltage of the first NMOS tube K1 and the threshold voltage of the second NMOS tube K2.

[0052] In a specific implementation, the third NMOS tube K3 and the fourth NMOS tube K4 can be intrinsic high-voltage CMOS tubes. The intrinsic high-voltage CMOS tube can normally work under high voltage, but its threshold voltage is very small, and the typical value of the threshold voltage is usually less than or equal to 0.2V and greater than or equal to 0V.

[0053] Due to the threshold voltage of the third NMOS transistor K3 and the fourth NMOS transistor K4, which is smaller than the threshold voltage of the first NMOS transistor K1 and the second NMOS transistor K2, the current flowing through the third NMOS transistor K3 and the fourth NMOS transistor K4 can be greater than the current flowing through the first NMOS transistor K1 and the second NMOS transistor K2. Therefore, after the logic signal is input into the input sub-circuit 21, the logic signal can be completely transmitted to the output sub-circuit 23 through the isolation sub-circuit 22, thereby improving the level conversion speed.

[0054] When the voltage of the logic signal output from the logic signal output terminal IN is at a high level, the first NMOS transistor K1 is turned on, and the second NMOS transistor K2 is turned off. Since the third NMOS transistor K3 is always in an on state, the gate voltage of the second PMOS transistor M2 can be at a low level, thereby making the second PMOS transistor M2 turned on, and the output terminal out outputs a voltage value close to the voltage output from the power supply voltage output terminal VDD, i.e., at a high level.

[0055] When the voltage of the logic signal output from the logic signal output terminal IN is at a low level, the first NMOS transistor K1 is turned off, and the second NMOS transistor K2 is turned on. Since the fourth NMOS transistor K4 is always in an on state, the output terminal out outputs a voltage value at a low level.

[0056] In another embodiment of the present application, referring to Figure 3 , the level conversion circuit 20 can further comprise a fifth NMOS transistor K5. The fifth NMOS transistor K5 is connected in parallel with the first PMOS transistor M1, and the gate of the fifth NMOS transistor K5 is connected with the output terminal D of the inverter 211.

[0057] When the voltage of the logic signal output from the logic signal output terminal IN is at a low level, the fifth NMOS transistor K5 is turned on. At the same time, the second NMOS transistor K2 is turned on, so that the output terminal out outputs a voltage value at a low level. At this time, the first PMOS transistor M1 is turned on, and the first PMOS transistor M1 and the fifth NMOS transistor K5 jointly charge the output terminal out, so that the output terminal out reaches the required conversion voltage more quickly.

[0058] In another embodiment of the present application, referring to Figure 3 , the level conversion circuit 20 can further comprise a sixth NMOS transistor K6. The sixth NMOS transistor K6 is connected in parallel with the second PMOS transistor M2, and the gate of the sixth NMOS transistor K6 is connected with the logic signal output terminal IN, i.e., connected with the input terminal C of the inverter 211.

[0059] When the voltage of the logic signal outputted from the logic signal input end IN is high, the sixth NMOS transistor K6 is turned on. At the same time, the first NMOS transistor K1 is turned on, so that the second PMOS transistor M2 is turned on. At this time, the voltage of the output end out is high. The second PMOS transistor M2 and the sixth NMOS transistor K6 jointly charge the output end out, so that the output end out reaches the required conversion voltage more quickly.

[0060] It can be understood that, in specific implementation, only the fifth NMOS transistor K5 can be arranged, only the sixth NMOS transistor K6 can be arranged, or the fifth NMOS transistor K5 and the sixth NMOS transistor K6 can be arranged simultaneously, which is not limited herein.

[0061] In specific implementation, the fifth NMOS transistor K5 and the sixth NMOS transistor K6 are also high-voltage CMOS transistors, i.e., MOS transistors capable of working normally under high voltage, and the typical value of the threshold voltage is greater than or equal to 1.0 V.

[0062] In specific implementation, the inverter 211 can be composed of CMOS transistors, and the CMOS transistors composing the inverter 211 can be low-voltage CMOS transistors, and the typical value of the threshold voltage is greater than or equal to 0.7 V and less than or equal to 0.8 V.

[0063] Figure 4 It is shown that: Figure 1 The level conversion speed of the level conversion circuit 10 is compared with the level conversion speed of the level conversion circuit 20 in the embodiment of the present application by a simulation result comparison diagram.

[0064] As Figure 4 shown, the curve 41 represents the voltage variation curve of the input logic signal. The curve 42 represents the voltage variation curve of the signal outputted from the output end out of the level conversion circuit 20. The curve 43 represents the voltage variation curve of the signal outputted from the output end out of the level conversion circuit 10.

[0065] At time t1, as shown by point a, the voltage value of the input logic signal reaches 0.6 V, which is about half of the high level (1.2 V). At time t2, as shown by point b, the voltage value of the signal outputted from the output end out of the level conversion circuit 20 reaches 0.9 V, which is about half of the high level (1.8 V). At time t3, as shown by point c, the voltage value of the signal outputted from the output end out of the level conversion circuit 20 reaches 0.9 V, which is about half of the high level (1.8 V).

[0066] (t2-t1) represents the level flipping duration of the level conversion circuit 20, and (t3-t1) represents the level flipping duration of the level conversion circuit 10. Apparently, the level flipping duration required by the level conversion circuit 20 in the embodiment of the present application is less than the level flipping duration required by the level conversion circuit 10.

[0067] From the above, the level conversion circuit 20 in the embodiment of the application, due to the setting of the isolation sub-circuit 22, makes the CMOS tube in the input sub-circuit 21 can use low-voltage CMOS tube, thereby can increase the current flowing through the CMOS tube in the input sub-circuit 21, effectively improves the level conversion speed.

[0068] Although the application is disclosed as above, the application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the application, therefore the protection scope of the application should be limited by the scope defined by the claims.

Claims

1. A level shifting circuit, characterized by, include: The circuit comprises an input sub-circuit, an isolation sub-circuit, and an output sub-circuit; wherein the input sub-circuit includes a first NMOS transistor, a second NMOS transistor, and an inverter; and the output sub-circuit includes a first PMOS transistor and a second PMOS transistor. The gate of the first NMOS transistor is connected to the logic signal output terminal and the input terminal of the inverter; the output terminal of the inverter is connected to the gate of the second NMOS transistor; the sources of the first and second NMOS transistors are grounded, and their drains are connected to the isolation sub-circuit; the isolation sub-circuit is connected to the drains of the first and second PMOS transistors; the gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor; the sources of the first and second PMOS transistors are connected to the power supply voltage output terminal. The threshold voltages of the first NMOS transistor and the second NMOS transistor are lower than the threshold voltages of the first PMOS transistor and the second PMOS transistor; the isolation sub-circuit is used to connect the input sub-circuit and the output sub-circuit, and to provide the first NMOS transistor and the second NMOS transistor with appropriate drain voltages; Wherein, the first PMOS transistor and the second PMOS transistor are both high-voltage transistors; the first NMOS transistor and the second NMOS transistor are both low-voltage transistors; The isolation sub-circuit includes a third NMOS transistor and a fourth NMOS transistor; wherein: the gates of both the third and fourth NMOS transistors are connected to the power supply voltage output terminal; the source of the third NMOS transistor is connected to the drain of the first NMOS transistor; the source of the fourth NMOS transistor is connected to the drain of the second NMOS transistor; the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor; the drain of the fourth NMOS transistor is connected to the drain of the second PMOS transistor; and the threshold voltages of the third and fourth NMOS transistors are lower than the threshold voltages of the first and second NMOS transistors. The third and fourth NMOS transistors are intrinsic high-voltage CMOS transistors.

2. The level shifting circuit of claim 1, wherein, The typical threshold voltage values ​​of the third and fourth NMOS transistors are greater than or equal to 0 V and less than or equal to 0.2 V.

3. The level shifting circuit of claim 1, wherein, Also includes: The fifth NMOS transistor is connected in parallel with the first PMOS transistor, and the gate of the fifth NMOS transistor is connected to the output terminal of the inverter.

4. The level shifting circuit of claim 3, wherein, Also includes: The sixth NMOS transistor is connected in parallel with the second PMOS transistor, and the gate of the sixth NMOS transistor is connected to the logic signal output terminal.

5. The level shifting circuit of claim 4, wherein, The typical threshold voltage values ​​of the fifth and sixth NMOS transistors are greater than or equal to 1V.

6. The level shifting circuit of claim 1, wherein, The typical threshold voltage values ​​of the first PMOS transistor and the second PMOS transistor are greater than or equal to 1V.

7. The level shifting circuit of claim 1, wherein, The typical threshold voltage values ​​of the first NMOS transistor and the second NMOS transistor are greater than or equal to 0.7V and less than or equal to 0.8V.

8. The level shifting circuit of claim 1, wherein, The inverter is composed of CMOS transistors.

9. The level shifting circuit of claim 8, wherein, The typical value of the threshold voltage of the CMOS tube in the inverter is greater than or equal to 0.7V and less than or equal to 0.8V.

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