Enhanced-mode GaN device based on p-InGaN / GaN superlattice structure and preparation method thereof

Abstract

The present invention discloses an enhanced-mode GaN device based on a p-InGaN / GaN superlattice structure and a method for preparing the same. The device comprises, from bottom to top, a substrate, a buffer layer, a first UID-GaN layer, and a barrier layer. The upper surfaces of the left and right sides of the barrier layer are provided with a source electrode and a drain electrode. The barrier layer between the source and drain electrodes is provided with a second UID-GaN layer, a p-InGaN / GaN superlattice layer, and a gate electrode. A passivation layer is provided on part of the upper surface of the first UID-GaN layer, the barrier layer, and the p-InGaN / GaN superlattice layer. Interconnect metal is provided on the source electrode, the drain electrode, and the gate electrode. The device structure provided by the present invention reduces the influence of impurity scattering on carrier mobility, improves hole mobility, increases hole concentration, and improves device threshold voltage, thereby improving device reliability and laying a solid foundation for the realization of high-performance GaN-based power electronic devices and integrated circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an enhanced GaN device based on a p-InGaN / GaN superlattice structure and a preparation method thereof. Background Art

[0002] With the advancement of semiconductor technology, wide-bandgap semiconductor materials, represented by gallium nitride (GaN), have found widespread application in applications ranging from aerospace power supplies to consumer electronics. While GaN's material and process costs are significantly higher than those of Si semiconductor devices, which have long been well-established in the industry, the high breakdown electric field, high output power density, and low switching power losses of GaN-based power electronic devices are unmatched by traditional Si-based devices. The vigorous development of wide-bandgap semiconductors, represented by GaN, will be key to overcoming the limitations of traditional semiconductors and improving chip breakdown voltage and power conversion efficiency. Gallium nitride high electron mobility transistors (HEMTs) show great promise in next-generation high-power, high-frequency switching applications.

[0003] In order to meet the fault safety requirements in practical applications, enhancement devices with normally-off function are crucial. Enhancement devices are turned off in the zero-bias state, that is, they do not require negative gate voltage drive in the non-working state. This can greatly reduce the additional power loss of the circuit, which is indispensable in high-speed switching circuits. At the same time, the use of enhancement devices can also simplify the design of the circuit. In order to realize enhancement-mode GaN devices, the industry has a variety of manufacturing methods, such as trench gate enhancement devices, fluorine ion implantation enhancement devices, common source and common gate enhancement devices, and p-GaN gate enhancement devices. Among these structures, p-GaN gate enhancement-mode HEMT has attracted much attention due to its good performance, reliability and manufacturing capabilities. Its conventional structure is as follows: Figure 1 shown.

[0004] However, there are still some problems in the current research on p-GaN gate enhancement mode devices that need further optimization, such as the low activation rate of p-type doping and the diffusion of Mg during high-temperature activation, which will lead to a low threshold voltage and cause reliability problems, hindering the further application of p-GaN gate enhancement mode devices. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides an enhanced GaN device based on a p-InGaN / GaN superlattice structure and a method for preparing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides an enhanced GaN device based on a p-InGaN / GaN superlattice structure, comprising, from bottom to top, a substrate, a buffer layer, a first UID-GaN layer, and a barrier layer, wherein a source electrode and a drain electrode are provided on the left and right upper surfaces of the barrier layer; wherein,

[0007] A second UID-GaN layer, a p-InGaN / GaN superlattice layer and a gate electrode are sequentially arranged upward on the barrier layer between the source electrode and the drain electrode;

[0008] A passivation layer is provided on a portion of the upper surface of the first UID-GaN layer, the barrier layer, and the p-InGaN / GaN superlattice layer;

[0009] Interconnection metal is provided on the source electrode, the drain electrode and the gate electrode.

[0010] In one embodiment of the present invention, the barrier layer is made of AlGaN with a thickness of 10-20 nm, wherein the Al content is 15%-25%.

[0011] In one embodiment of the present invention, the thickness of the second UID-GaN layer is 5-10 nm.

[0012] In one embodiment of the present invention, the p-InGaN / GaN superlattice layer includes a plurality of p-InGaN layers and p-GaN layers alternately arranged up and down; wherein,

[0013] The thickness of each p-InGaN layer is 1 to 2 nm, and the In composition is 5% to 10%;

[0014] The thickness of each p-GaN layer is 5 to 10 nm.

[0015] In one embodiment of the present invention, the thickness of the p-InGaN / GaN superlattice layer is 72-96 nm.

[0016] In one embodiment of the present invention, both the p-InGaN layer and the p-GaN layer are doped with Mg, with a doping concentration of 1×10 19 ~5×10 19 cm -3 .

[0017] In one embodiment of the present invention, an n-GaN layer is further included between the p-InGaN / GaN superlattice layer and the gate electrode.

[0018] In one embodiment of the present invention, the thickness of the n-GaN layer is 30-50 nm, and Si is doped with a doping concentration of 1×10 16 ~5×10 16cm -3 .

[0019] In a second aspect, the present invention provides a method for preparing an enhanced-mode GaN device based on a p-InGaN / GaN superlattice structure, comprising:

[0020] Step 1: epitaxially growing a GaN buffer layer, a first UID-GaN layer, an AlGaN barrier layer, a second UID-GaN layer, and a p-InGaN / GaN superlattice layer on a substrate in sequence to obtain a GaN epitaxial wafer;

[0021] Step 2: Etching the GaN epitaxial wafer to form a gate region of the device, and then performing mesa etching again to form device isolation;

[0022] Step 3: preparing a source electrode and a drain electrode on the source and drain regions on both sides of the device, and preparing a gate electrode on the p-InGaN / GaN superlattice layer;

[0023] Step 4: growing a passivation layer on the entire sample surface;

[0024] Step 5: Depositing metal on the source electrode, drain electrode and gate electrode to form interconnect metal, thereby completing the preparation of the device.

[0025] In one embodiment of the present invention, after step 1 and before step 2, the method further includes:

[0026] Step x: epitaxially growing an n-GaN layer on the p-InGaN / GaN superlattice layer.

[0027] Beneficial effects of the present invention:

[0028] 1. On the one hand, the present invention grows a layer of UID-GaN on the AlGaN barrier layer, reducing the impact of impurity scattering on carrier mobility and improving hole mobility. The UID-GaN and AlGaN polarize to form a two-dimensional hole gas, increasing the hole concentration and improving the device threshold voltage. On the other hand, a p-InGaN / GaN superlattice layer is added on the GaN layer, reducing the activation energy of Mg impurities, obtaining a high concentration of holes, and further improving the device threshold voltage. At the same time, the UID-GaN layer inhibits the diffusion of Mg ions in the p-InGaN / GaN superlattice layer into the underlying material, improving device reliability and laying a solid foundation for the realization of high-performance GaN-based power electronic devices and integrated circuits.

[0029] 2. The present invention also suppresses gate leakage and increases forward gate voltage swing by growing a layer of n-GaN on the p-InGaN / GaN superlattice layer.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of a p-GaN gate enhancement mode HEMT structure provided by the prior art;

[0032] Figure 2 Schematic diagram of the structure of an enhancement-mode GaN device based on a p-InGaN / GaN superlattice structure provided by an embodiment of the present invention;

[0033] Figure 3 Schematic diagram of another enhanced-mode GaN device based on a p-InGaN / GaN superlattice structure provided by an embodiment of the present invention;

[0034] Figure 4 The p-GaN / AlGaN / GaN heterojunction energy band diagram and the enhanced GaN device heterojunction energy band diagram based on the p-InGaN / GaN superlattice structure provided by the embodiments of the present invention are as follows;

[0035] Figure 5 This is a flow chart of a method for preparing an enhancement-mode GaN device based on a p-InGaN / GaN superlattice structure provided by an embodiment of the present invention;

[0036] Figures 6a-6h This is a schematic diagram of the preparation process of an enhanced GaN device based on a p-InGaN / GaN superlattice structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0038] Example 1

[0039] See Figure 2 , Figure 2 This is a schematic diagram of the structure of an enhancement-mode GaN device based on a p-InGaN / GaN superlattice structure provided by an embodiment of the present invention, which includes, from bottom to top, a substrate 1, a buffer layer 2, a first UID-GaN layer 3, and a barrier layer 4. The upper surfaces of the barrier layer 4 on both sides are provided with a source electrode 7 and a drain electrode 8; wherein,

[0040] A second UID-GaN layer 5, a p-InGaN / GaN superlattice layer 6 and a gate electrode 9 are sequentially arranged upward on the barrier layer 4 between the source electrode 7 and the drain electrode 8;

[0041] A passivation layer 10 is provided on part of the upper surface of the first UID-GaN layer 3 , the barrier layer 4 , and the p-InGaN / GaN superlattice layer 6 ;

[0042] Interconnection metal 11 is provided on the source electrode 7 , the drain electrode 8 and the gate electrode 9 .

[0043] In this embodiment, the substrate 1 is made of silicon; the buffer layer 2 is made of AlGaN with a thickness of 1 to 5 μm; the thickness of the first UID-GaN layer 3 is 300 to 500 nm; the barrier layer 4 is made of AlGaN material with a thickness of 10 to 20 nm and an Al component of 15% to 25%; the thickness of the second UID-GaN layer 5 is 5 to 10 nm.

[0044] Furthermore, the p-InGaN / GaN superlattice layer 6 includes a plurality of p-InGaN layers and p-GaN layers alternately arranged up and down; wherein,

[0045] The thickness of each p-InGaN layer is 1 to 2 nm, and the In composition is 5% to 10%; the thickness of each p-GaN layer is 5 to 10 nm, that is, the thickness ratio of the p-InGaN layer to the p-GaN layer is 1:5. Therefore, in this embodiment, the p-InGaN / GaN superlattice layer 6 can also be recorded as a p-(InGaN)1 / (GaN)5 layer.

[0046] Specifically, the p-GaN layer and the p-InGaN layer are repeatedly arranged 6-16 times to form a p-InGaN / GaN superlattice layer 6 with a total thickness of 72-96 nm.

[0047] Preferably, both the p-InGaN layer and the p-GaN layer are doped with Mg, with a doping concentration of 1×10 19 ~5×10 19 cm -3 .

[0048] In this embodiment, the source electrode 7 and the drain electrode 8 are made of titanium, aluminum, nickel and gold from bottom to top, and the titanium metal forms an ohmic contact with the AlGaN barrier layer 4, and the thickness is 200 to 300 nm; the gate electrode 9 is made of titanium nitride, titanium and gold, and forms a Schottky contact with the p-InGaN / GaN superlattice layer 6, and the thickness is 200 nm to 350 nm.

[0049] The passivation layer 10 is made of Al2O3 material with a thickness of 20 to 30 nm; the interconnection metal 11 is made of nickel and gold.

[0050] The enhanced GaN device based on the p-InGaN / GaN superlattice structure provided in this embodiment, on the one hand, grows a layer of UID-GaN on the AlGaN barrier layer, which reduces the influence of impurity scattering on carrier mobility and improves hole mobility. The UID-GaN and AlGaN are polarized to form a two-dimensional hole gas, which increases the hole concentration and improves the device threshold voltage. On the other hand, a p-InGaN / GaN superlattice layer is added on the GaN layer, which reduces the activation energy of Mg impurities, obtains a high concentration of holes, and further improves the device threshold voltage. At the same time, the UID-GaN layer suppresses the diffusion of Mg ions in the p-InGaN / GaN superlattice layer to the underlying material, thereby improving device reliability.

[0051] In another embodiment of the present invention, an n-GaN layer 12 is further included between the p-InGaN / GaN superlattice layer 6 and the gate electrode 9; wherein the thickness of the n-GaN layer 12 is 30 to 50 nm, and the n-GaN layer 12 is doped with Si at a doping concentration of 1×10 16 ~5×10 16 cm -3 See Figure 3 , Figure 3 This is a schematic diagram of the structure of another enhancement-mode GaN device based on a p-InGaN / GaN superlattice structure provided by an embodiment of the present invention.

[0052] In this embodiment, a layer of n-GaN is grown on the p-InGaN / GaN superlattice layer, thereby suppressing gate leakage and increasing the forward gate voltage swing.

[0053] To further verify the beneficial effects of the present invention, this example also compares the heterojunction energy band of an enhanced GaN device based on a p-InGaN / GaN superlattice structure with the existing p-GaN / AlGaN / GaN heterojunction energy band. Figure 4 , Figure 4 1 is a p-GaN / AlGaN / GaN heterojunction energy band diagram provided by an embodiment of the present invention and an enhanced GaN device heterojunction energy band diagram based on a p-InGaN / GaN superlattice structure, wherein the solid line represents the enhanced GaN device heterojunction energy band based on the p-InGaN / GaN superlattice structure of the present invention, and the dotted line represents the existing p-GaN / AlGaN / GaN heterojunction energy band diagram.

[0054] from Figure 4 It can be seen that compared with existing p-GaN / AlGaN / GaN enhancement-mode devices, the enhancement-mode GaN device based on the p-InGaN / GaN superlattice structure obtains a high concentration of holes, has a better depletion effect on the two-dimensional electron gas, and further improves the device threshold voltage.

[0055] Example 2

[0056] Based on the above embodiment 1, this embodiment provides a method for preparing an enhancement mode GaN device based on a p-InGaN / GaN superlattice structure. Figure 5 , Figure 5 The flowchart of the method for preparing an enhancement-mode GaN device based on a p-InGaN / GaN superlattice structure provided by an embodiment of the present invention specifically includes the following steps:

[0057] Step 1: A GaN buffer layer, a first UID-GaN layer, an AlGaN barrier layer, a second UID-GaN layer, and a p-InGaN / GaN superlattice layer are sequentially grown on a substrate to obtain a GaN epitaxial wafer.

[0058] Specifically, a GaN buffer layer, a first UID-GaN, an AlGaN barrier layer, a second UID-GaN and a p-InGaN / GaN superlattice layer are sequentially grown on a silicon substrate using a metal organic chemical vapor deposition process to obtain a silicon substrate GaN epitaxial wafer substrate.

[0059] Specifically, for the p-InGaN / GaN superlattice layer, a metal organic chemical vapor deposition process may be used, and p-GaN and p-InGaN are alternately deposited at a certain period to form the p-InGaN / GaN superlattice layer.

[0060] Step 2: Etch the GaN epitaxial wafer to form the gate region of the device, and then perform mesa etching again to form device isolation.

[0061] First, the second UID-GaN and p-InGaN / GaN superlattice layers outside the gate region are etched using photolithography and inductively coupled plasma etching processes to form a gate region of the device.

[0062] Then, photolithography and inductively coupled plasma etching processes are used to perform mesa etching to expose the source and drain regions of the two devices and simultaneously form device isolation.

[0063] Step 3: Prepare source and drain electrodes on the source and drain regions on both sides of the device, and prepare a gate electrode on the p-InGaN / GaN superlattice layer.

[0064] 31) Preparation of source and drain electrodes

[0065] Specifically, photolithography was used to define the source and drain regions, and the sample was then cleaned with a 20:1 BOE solution for 1 minute to remove oxides from the source and drain regions. Using electron beam evaporation, 20-50nm thick titanium, 100-150nm thick aluminum, 30-60nm thick nickel, and 40-60nm thick gold were sequentially deposited on the AlGaN barrier layer to form the source and drain electrodes of the enhanced GaN power electronic device based on the p-InGaN / GaN superlattice structure. The samples were then annealed in a nitrogen atmosphere at 850°C for 30 seconds to ensure that both the source and drain electrodes formed ohmic contacts with the AlGaN barrier layer.

[0066] 32) Preparation of gate electrode

[0067] The gate region was defined using photolithography, and the sample was cleaned for 1 minute in a 20:1 BOE solution to remove the oxide in the gate region. Using magnetron sputtering, titanium nitride (20-40nm thick), titanium (20-50nm thick), and gold (200-250nm thick) were sequentially deposited on the p-InGaN / GaN superlattice layer to form the gate electrode for the enhancement-mode GaN power electronic device based on the p-InGaN / GaN superlattice structure.

[0068] Step 4: Grow a passivation layer over the entire sample surface.

[0069] Specifically, an atomic layer deposition process was used to deposit a 20nm thick layer of aluminum oxide on the entire sample to form a passivation layer for an enhanced GaN power electronic device based on a p-InGaN / GaN superlattice structure.

[0070] Step 5: Deposit metal on the source electrode, drain electrode, and gate electrode to form interconnect metal, thereby completing the preparation of the device.

[0071] It should be noted that before fabricating the interconnect metal, the passivation layer must be etched to create holes to expose the interconnect metal fabrication area. Specifically, a wet etching process is used with a 20:1 BOE solution to etch away the aluminum oxide covering the source, drain, and gate electrodes; or a reactive ion etching process is used to etch away the aluminum oxide covering the source, drain, and gate electrodes.

[0072] Then, an electron beam evaporation process is used to sequentially deposit 20 to 50 nm thick nickel metal and 200 to 500 nm thick gold metal in the opening etching areas of the source electrode, drain electrode and gate electrode to form interconnect metal.

[0073] At this point, the preparation of enhancement-mode GaN devices based on the p-InGaN / GaN superlattice structure is completed.

[0074] In another embodiment of the present invention, in order to further improve the gate withstand voltage and reduce the gate leakage, a layer of n-GaN is grown on the p-InGaN / GaN superlattice layer, that is, after step 1 and before step 2, the following is further included:

[0075] Step x: epitaxially growing an n-GaN layer on the p-InGaN / GaN superlattice layer.

[0076] Accordingly, when forming the source and drain regions of the device in step 2, the n-GaN layer needs to be etched to form an enhanced GaN power electronic device based on a p-InGaN / GaN superlattice structure with n-GaN.

[0077] It should be noted that in order to form a Schottky contact between the gate electrode and the n-GaN layer, nickel and gold metals are used when preparing the gate electrode on the subsequent epitaxial n-GaN layer. Specifically, the gate region is defined by photolithography, and the sample is cleaned for 1 minute using a 20:1 BOE solution to remove the oxide in the gate region. Using a magnetron sputtering process, nickel metal with a thickness of 20-50nm and gold metal with a thickness of 200-250nm are sequentially deposited on the n-GaN to form the gate electrode of the enhancement-mode GaN power electronic device based on the p-InGaN / GaN superlattice structure with n-GaN.

[0078] Example 3

[0079] The process of the preparation method provided by the present invention is described in detail below with reference to the accompanying drawings.

[0080] See Figures 6a-6h , Figures 6a-6h This is a schematic diagram of a fabrication process for an enhancement-mode GaN device based on a p-InGaN / GaN superlattice structure provided by an embodiment of the present invention, specifically including:

[0081] S1: Fabrication of GaN epitaxial wafers on silicon substrates

[0082] Using metal organic chemical vapor deposition process, GaN buffer layer (GaNBuffer), first UID-GaN layer, AlGaN barrier layer, second UID-GaN, p-(InGaN)1 / (GaN)5 superlattice layer are sequentially grown on Si substrate to obtain GaN epitaxial wafer on silicon substrate, such as Figure 6a shown.

[0083] S2: p-GaN etching

[0084] The UID-GaN and p-InGaN / GaN superlattice layers outside the gate region are etched using photolithography and inductively coupled plasma etching to form the device gate region, such as Figure 6b shown.

[0085] S3: Countertop Isolation

[0086] The mesa is etched using photolithography and inductively coupled plasma etching to form device isolation, such as Figure 6c shown.

[0087] S4: Make source electrode S and drain electrode D, such as Figure 6d For detailed process, see step 31 in Example 2).

[0088] S5: Make gate electrode S, such as Figure 6e For detailed process, see step 32 in Example 2).

[0089] S6: Passivation Dielectric Growth

[0090] Atomic layer deposition was used to deposit 20nm thick aluminum oxide on the entire sample to form a passivation layer for enhanced GaN power electronic devices based on p-InGaN / GaN superlattice structure, such as Figure 6f shown.

[0091] S7: Passivation layer etching and hole opening

[0092] A wet etching process is used to etch away the aluminum oxide covering the source electrode, drain electrode and gate electrode using a 20:1 BOE solution; or a reactive ion etching process is used to etch away the aluminum oxide covering the source electrode, drain electrode and gate electrode, such as Figure 6g shown.

[0093] S8: Interconnect Metal Evaporation

[0094] 20nm thick nickel metal and 200nm thick gold metal are deposited in the source electrode, drain electrode and gate electrode opening etching areas to form interconnect metal, such as Figure 6h shown.

[0095] At this point, the preparation of enhancement-mode GaN devices based on the p-InGaN / GaN superlattice structure is completed.

[0096] In the description of the present invention, it should be understood that the terms "thickness", "up", "down", "left", "right", "top", "bottom", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0097] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0098] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0099] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

[0100] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An enhancement-mode GaN device based on a p-InGaN / GaN superlattice structure, characterized in that: The device comprises, from bottom to top, a substrate (1), a buffer layer (2), a first UID-GaN layer (3), and a barrier layer (4), wherein the upper surfaces on the left and right sides of the barrier layer (4) are provided with a source electrode (7) and a drain electrode (8); wherein, A second UID-GaN layer (5), a p-InGaN / GaN superlattice layer (6), and a gate electrode (9) are sequentially arranged upward on the barrier layer (4) between the source electrode (7) and the drain electrode (8); wherein the p-InGaN / GaN superlattice layer (6) comprises a plurality of p-InGaN layers and p-GaN layers alternately arranged up and down; and the In component of each of the p-InGaN layers is 5% to 10%. A passivation layer (10) is provided on a portion of the upper surface of the first UID-GaN layer (3), the barrier layer (4), and the p-InGaN / GaN superlattice layer (6); Interconnection metal (11) is provided on the source electrode (7), the drain electrode (8) and the gate electrode (9); An n-GaN layer (12) is further included between the p-InGaN / GaN superlattice layer (6) and the gate electrode (9).

2. The enhancement-mode GaN device based on the p-InGaN / GaN superlattice structure according to claim 1, characterized in that: The barrier layer (4) is made of AlGaN with a thickness of 10-20 nm, wherein the Al content is 15%-25%.

3. The enhancement-mode GaN device based on the p-InGaN / GaN superlattice structure according to claim 1, characterized in that: The thickness of the second UID-GaN layer (5) is 5-10 nm.

4. The enhancement-mode GaN device based on the p-InGaN / GaN superlattice structure according to claim 1, characterized in that: The thickness of each p-InGaN layer is 1~2nm; the thickness of each p-GaN layer is 5~10nm.

5. The enhancement-mode GaN device based on the p-InGaN / GaN superlattice structure according to claim 4, characterized in that: The thickness of the p-InGaN / GaN superlattice layer (6) is 72-96 nm.

6. The enhancement-mode GaN device based on the p-InGaN / GaN superlattice structure according to claim 1, characterized in that: The p-InGaN layer and the p-GaN layer are both doped with Mg, with a doping concentration of 1×10 19 ~5×10 19 cm -3 .

7. The enhancement-mode GaN device based on the p-InGaN / GaN superlattice structure according to claim 1, characterized in that: The thickness of the n-GaN layer (12) is 30-50 nm, and Si is doped with a doping concentration of 1×10 16 ~5×10 16 cm -3 .

8. A method for preparing an enhancement-mode GaN device based on a p-InGaN / GaN superlattice structure, characterized in that: include: Step 1: epitaxially growing a GaN buffer layer, a first UID-GaN layer, an AlGaN barrier layer, a second UID-GaN layer, a p-InGaN / GaN superlattice layer, and an n-GaN layer on a substrate to obtain a GaN epitaxial wafer; wherein the p-InGaN / GaN superlattice layer comprises a plurality of p-InGaN layers and p-GaN layers alternately arranged up and down; the In component of each p-InGaN layer is 5% to 10%; Step 2: Etching the GaN epitaxial wafer to form a gate region of the device, and then performing mesa etching again to form device isolation; Step 3: preparing a source electrode and a drain electrode on the source and drain regions on both sides of the device, and preparing a gate electrode on the n-GaN layer; Step 4: growing a passivation layer on the entire sample surface; Step 5: Depositing metal on the source electrode, drain electrode and gate electrode to form interconnect metal, thereby completing the preparation of the device.

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