A Hardware Implementation Method, Device, and Electronic Device for In-Memory Computing in a Storage Pool

Abstract

The present application discloses a hardware implementation method, device, and electronic device for reservoir in-memory computing, which relates to the fields of machine learning and artificial intelligence. The hardware implementation method for reservoir in-memory computing includes: obtaining a voltage signal transmitted by an input module to a memristor array; mapping a linear feature vector at a target moment to the memristor array based on the voltage signal; controlling the memristor array to determine a non-linear feature vector based on the linear feature vector at the target moment; controlling the memristor array to determine a total feature vector at the target moment based on the linear feature vector and the non-linear feature vector at the target moment; controlling the memristor array to predict the input data coordinates at the next moment based on the total feature vector at the target moment, so that an output module can convert the input data coordinates into an output value of a digital signal for output, effectively reducing the data transfer during the calculation process, improving the calculation rate of reservoir computing, and improving the reliability and stability of reservoir computing.

Description

Technical Field

[0001] This application relates to the fields of machine learning and artificial intelligence, and particularly to a hardware implementation method, device, and electronic device for reservoir in-memory computing. Background Art

[0002] With the development of the fields of machine learning and artificial intelligence, reservoir computing, as a special recurrent neural network computing mode, has also attracted much attention. Reservoir computing has the advantages of simple structure, few training parameters, and low energy consumption, and has great application potential in aspects such as time series signal processing and chaotic dynamics system prediction.

[0003] Currently, the reservoir computing uses randomly initialized network weights. Traditional reservoir computing structures can include an echo state network composed of randomly connected multiple neurons and a single-node delay reservoir computing structure, both of which require a large amount of data and computing time for preprocessing and parameter optimization. Research has shown that the next-generation reservoir computing (NGRC) is a special non-linear vector autoregressive process, which is equivalent to the combination of a reservoir with linear activation nodes and a non-linear readout layer, and can effectively alleviate the above problems of the traditional reservoir computing that require a large amount of data and computing time for preprocessing and parameter optimization under the condition of ensuring the prediction accuracy.

[0004] However, the non-linear vector autoregressive process itself still requires a large amount of hardware computing resource overhead for multiplication operations, which is difficult to achieve under limited computing resources and computing power conditions, resulting in that the reservoir computing still requires a large amount of data and computing time for preprocessing and parameter optimization, reducing the computing rate of the reservoir computing and reducing the reliability and stability of the reservoir computing. Summary of the Invention

[0005] The purpose of this application is to provide a hardware implementation method, device, and electronic device for reservoir in-memory computing, so as to solve the problems that the existing reservoir computing still requires a large amount of data and computing time for preprocessing and parameter optimization, reducing the computing rate of the reservoir computing and reducing the reliability and stability of the reservoir computing.

[0006] In a first aspect, this application provides a hardware implementation method for reservoir in-memory computing, which is applied to an electronic device having an input module, a weight module composed of a memristor array, and an output module connected in sequence. The method includes:

[0007] Obtain the voltage signal transmitted from the input module to the memristor array;

[0008] Map the linear feature vector at the target moment to the memristor array based on the voltage signal;

[0009] Control the memristor array to determine a non - linear feature vector based on the linear feature vector at the target time;

[0010] Control the memristor array to determine the total feature vector at the target time based on the linear feature vector and the non - linear feature vector at the target time;

[0011] Control the memristor array to predict the input data coordinates at the next time based on the total feature vector at the target time, so that the output module can convert the input data coordinates into the output value of the digital signal to complete the output.

[0012] In the case of adopting the above - mentioned technical solution, the hardware implementation method of reservoir in - memory computing provided by the embodiments of the present application can obtain the voltage signal transmitted from the input module to the memristor array; map the linear feature vector at the target time to the memristor array based on the voltage signal; control the memristor array to determine the non - linear feature vector based on the linear feature vector at the target time; control the memristor array to determine the total feature vector at the target time based on the linear feature vector and the non - linear feature vector at the target time; control the memristor array to predict the input data coordinates at the next time based on the total feature vector at the target time, so that the output module can convert the input data coordinates into the output value of the digital signal to complete the output. Among them, due to the above - mentioned reservoir in - memory computing, the matrix - vector multiplication operation in the non - linear vector autoregressive process is completed by using the memristor array, effectively reducing the data transfer in the calculation process, providing a new way for the hardware implementation of reservoir computing, improving the computing rate of reservoir computing, and improving the reliability and stability of reservoir computing.

[0013] In a possible implementation manner, the control of the memristor array to determine the non - linear feature vector based on the linear feature vector at the target time includes:

[0014] Control the memristor array to determine the non - linear feature vector based on the linear feature vector at the target time through Ohm's law and Kirchhoff's law.

[0015] In a possible implementation manner, the control of the memristor array to determine the total feature vector at the target time based on the linear feature vector and the non - linear feature vector at the target time includes:

[0016] Control the memristor array to determine the total feature vector at the target time based on the linear feature vector and the non - linear feature vector at the target time in combination with the target constant.

[0017] In a possible implementation manner, the control of the memristor array to predict the input data coordinates at the next time based on the total feature vector at the target time includes:

[0018] Control the memristor array to predict the input data coordinates at the next moment based on the total feature vector and the output mapping weights at the target moment.

[0019] In a possible implementation, the linear feature vector at the target moment is a linear feature vector composed of three-dimensional time series signals at the i-th moment in the weather prediction model time series.

[0020] In a second aspect, the present application also provides a hardware implementation device for reservoir in-memory computing, which is applied to an electronic device having an input module, a weight module composed of a memristor array, and an output module connected in sequence. The device includes:

[0021] An acquisition module, configured to acquire the voltage signal transmitted from the input module to the memristor array;

[0022] A mapping module, configured to map the linear feature vector at the target moment to the memristor array based on the voltage signal;

[0023] A first control module, configured to control the memristor array to determine a non-linear feature vector based on the linear feature vector at the target moment;

[0024] A second control module, configured to control the memristor array to determine the total feature vector at the target moment based on the linear feature vector and the non-linear feature vector at the target moment;

[0025] A third control module, configured to control the memristor array to predict the input data coordinates at the next moment based on the total feature vector at the target moment, so that the output module converts the input data coordinates into an output value of a digital signal to complete the output.

[0026] In a possible implementation, the first control module includes:

[0027] A first control sub-module, configured to control the memristor array to determine the non-linear feature vector based on the linear feature vector at the target moment through Ohm's law and Kirchhoff's law.

[0028] In a possible implementation, the second control module includes:

[0029] A second control sub-module, configured to control the memristor array to determine the total feature vector at the target moment based on the linear feature vector and the non-linear feature vector at the target moment in combination with a target constant.

[0030] In a possible implementation, the third control module includes:

[0031] A third control sub-module, configured to control the memristor array to predict the input data coordinates at the next moment based on the total feature vector at the target moment and the output mapping weights;

[0032] The beneficial effects of the hardware implementation device for reservoir in-memory computing provided by the target moment linear feature vector for the second aspect of weather are the same as those of the hardware implementation method for reservoir in-memory computing described in the first aspect or any possible implementation manner of the first aspect, and will not be elaborated here.

[0033] In a third aspect, the present application further provides an electronic device, including: one or more processors; and one or more machine-readable media storing instructions thereon, which, when executed by the one or more processors, cause the electronic device to execute the hardware implementation device for reservoir in-memory computing described in any possible implementation manner of the second aspect.

[0034] The beneficial effects of the electronic device provided by the third aspect are the same as those of the hardware implementation device for reservoir in-memory computing described in the second aspect or any possible implementation manner of the second aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0036] Figure 1 A schematic flowchart of a hardware implementation method for reservoir in-memory computing provided by an embodiment of the present application is shown;

[0037] Figure 2 A schematic flowchart of another hardware implementation method for reservoir in-memory computing provided by an embodiment of the present application is shown;

[0038] Figure 3 A schematic structural diagram of a simulation platform for a hardware implementation method for reservoir in-memory computing provided by an embodiment of the present application is shown;

[0039] Figure 4 A schematic diagram showing the change of the vector of the convective observable of a weather prediction model provided by an embodiment of the present application over time is shown;

[0040] Figure 5 A schematic diagram showing the formation of a strange attractor by the phase space trajectory of a weather prediction model provided by an embodiment of the present application is shown;

[0041] Figure 6 A schematic mapping diagram showing mapping the target moment linear feature vector to the memristor array provided by an embodiment of the present application is shown;

[0042] Figure 7 A schematic prediction experiment diagram provided by an embodiment of the present application is shown;

[0043] Figure 8 It shows a schematic structural diagram of a hardware implementation device for reservoir in-memory computing provided by an embodiment of the present application;

[0044] Figure 9 It is a schematic hardware structure diagram of an electronic device provided by an embodiment of the present application;

[0045] Figure 10 It is a schematic structural diagram of a chip provided by an embodiment of the present application. Specific embodiments

[0046] For the convenience of clearly describing the technical solutions of the embodiments of the present application, in the embodiments of the present application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and roles. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their sequence. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and "first", "second", etc. do not necessarily mean different.

[0047] It should be noted that in the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly, using words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0048] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression below refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b or c may represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c may be single or multiple.

[0049] Figure 1 It shows a schematic flow diagram of a hardware implementation method for reservoir in-memory computing provided by an embodiment of the present application. The hardware implementation method for reservoir in-memory computing is applied to an electronic device having an input module, a weight module composed of a memristor array, and an output module connected in sequence. As Figure 1As shown in the figure, the hardware implementation method of reservoir in-memory computing includes:

[0050] Step 101: Obtain the voltage signal transmitted from the input module to the memristor array.

[0051] In this application, the electronic device can be a simulation platform. Figure 3 FIG. shows a schematic structural diagram of a simulation platform for a hardware implementation method of reservoir in-memory computing provided by an embodiment of this application. As Figure 3 shown, the simulation platform may include a weight module 02 and an output module 03 composed of an input module 01 and a memristor array A connected in sequence. Among them, the input module 01 can convert an external signal into a voltage signal.

[0052] Optionally, the conversion of the signal can be completed based on the following formulas (1), (2), and (3):

[0053] ΔX = max(|X|) / 2 n-1 (1);

[0054] ΔV = (V_ max - V_ min ) / 2 n-1 (2);

[0055] X = [X / ΔX]×ΔV (3);

[0056] where n represents the accuracy of the digital-to-analog converter (DAC) in the input module; V_ max represents the maximum value of the input voltage, and V_ min represents the minimum value of the input voltage; [X] represents the rounding operation, and the highest conversion accuracy can be fixed-point 32 bits (bit). The accuracy ΔX and ΔV of the input signal (external signal) and the voltage signal can be calculated according to the DAC accuracy, and then the signal is converted into a fixed-point integer through the rounding operation and multiplied by ΔV to obtain the corresponding voltage input.

[0057] In this application, the memristor array is composed of multiple non-volatile storage devices, and the non-volatile storage device is composed of any one of a memristor, a phase change memory, a ferroelectric tunneling device, a magnetic random access memory, or a Flash resistive switching device, and may also include other resistive switching devices. This application embodiment does not make specific limitations on this, and can be specifically adjusted according to the actual application scenario.

[0058] Step 102: Map the linear feature vector at the target moment to the memristor array based on the voltage signal.

[0059] In this application, the target - moment linear feature vector is a linear feature vector composed of three - dimensional time - series signals at the i - th moment in the time series of the weather prediction model.

[0060] Step 103: Control the memristor array to determine a non - linear feature vector based on the target - moment linear feature vector.

[0061] In this application, the memristor array can be controlled to determine the non - linear feature vector based on the target - moment linear feature vector through Ohm's law and Kirchhoff's law.

[0062] Step 104: Control the memristor array to determine the total feature vector at the target moment based on the target - moment linear feature vector and the non - linear feature vector.

[0063] In this application, the memristor array can be controlled to determine the total feature vector at the target moment by combining the target - moment linear feature vector and the non - linear feature vector with a target constant.

[0064] Step 105: Control the memristor array to predict the input data coordinates at the next moment based on the total feature vector at the target moment, so that the output module can convert the input data coordinates into the output value of a digital signal to complete the output.

[0065] In this application, the memristor array can be controlled to predict the input data coordinates at the next moment based on the total feature vector at the target moment and the output mapping weight, so that the output module can convert the input data coordinates into the output value of a digital signal to complete the output.

[0066] The hardware implementation method of reservoir in - memory computing in this application uses a memristor array to complete the matrix - vector multiplication operation in the non - linear vector autoregressive process, effectively reducing the data transfer in the calculation process and providing a new way for the hardware implementation of reservoir computing.

[0067] The hardware implementation method of reservoir in-memory computing provided by the embodiments of the present application can obtain the voltage signal transmitted by the input module to the memristor array; map the linear feature vector at the target moment to the memristor array based on the voltage signal; control the memristor array to determine the non-linear feature vector based on the linear feature vector at the target moment; control the memristor array to determine the total feature vector at the target moment based on the linear feature vector and the non-linear feature vector at the target moment; control the memristor array to predict the input data coordinates at the next moment based on the total feature vector at the target moment, so that the output module can convert the input data coordinates into the output value of the digital signal to complete the output. Among them, due to the above-mentioned reservoir in-memory computing, the matrix-vector multiplication operation in the non-linear vector autoregressive process is completed by using the memristor array, effectively reducing the data transfer in the calculation process, providing a new way for the hardware implementation of reservoir computing, improving the computing rate of reservoir computing, and improving the reliability and stability of reservoir computing.

[0068] Figure 2 Fig. 4 shows a schematic flowchart of another hardware implementation method of reservoir in-memory computing provided by the embodiments of the present application. This hardware implementation method of reservoir in-memory computing is applied to an electronic device having an input module, a weight module composed of a memristor array, and an output module connected in sequence. As Figure 2 shown, the hardware implementation method of reservoir in-memory computing includes:

[0069] Step 201: Obtain the voltage signal transmitted by the input module to the memristor array.

[0070] In the present application, the electronic device can be a simulation platform. Figure 3 Fig. 14 shows a schematic structural diagram of a simulation platform for a hardware implementation method of reservoir in-memory computing provided by the embodiments of the present application. As Figure 3 shown, the simulation platform may include an input module 01, a weight module 02 composed of a memristor array A, and an output module 03 connected in sequence. Among them, the input module 01 can convert an external signal into a voltage signal.

[0071] Optionally, the conversion of the signal can be completed based on the following formulas (1), (2), and (3):

[0072] ΔX = max(|X|) / 2 n-1 (1);

[0073] ΔV = (V_ max - V_ min ) / 2 n-1 (2);

[0074] X = [X / ΔX]×ΔV (3);

[0075] where n represents the precision of the Digital to Analog Converter (DAC) in the input module; V_ max represents the maximum value of the input voltage, and V_ min represents the minimum value of the input voltage; [X] represents the rounding operation, and the highest conversion precision can be fixed-point 32 bits (bit). The precision ΔX and ΔV of the input signal (external signal) and the voltage signal can be calculated according to the DAC precision, and then the signal is converted into a fixed-point integer through the rounding operation and multiplied by ΔV to obtain the corresponding voltage input.

[0076] In this application, the memristor array is composed of multiple non-volatile memory devices, and the non-volatile memory device is composed of any one of a memristor, a phase change memory, a ferroelectric tunneling device, a magnetic random access memory, or a Flash resistive switching device, and may also include other resistive switching devices. The embodiments of this application do not make specific limitations on this, and can be specifically adjusted according to the actual application scenario.

[0077] Step 202: Map the target time linear feature vector to the memristor array based on the voltage signal.

[0078] Optionally, the input data set adopted in this application can be a time series prediction data set of a weather prediction model (Lorenz63), Figure 4 which shows a schematic diagram of the change of the vector of the convective observables of a weather prediction model provided by the embodiments of this application over time, Figure 5 which shows a schematic diagram of the formation of a strange attractor by the phase space trajectory of a weather prediction model provided by the embodiments of this application. Among them, the weather prediction model (Lorenz63) is a weather prediction model proposed by Lorenz in 1963, and X(t)≡[x, y, z]T is a vector with components being the convective observables of Rayleigh-Bénard.

[0079] In this application, the target time linear feature vector is a linear feature vector composed of three-dimensional time series signals at the i-th moment in the time series of the weather prediction model.

[0080] Among them, the Lorenz63 time series prediction data set is composed of the following three equations (4), (5), and (6),

[0081] dx / dt = a(y - x) (4);

[0082] dy / dt = ax(b - z) - y (5);

[0083] dz / dt = xy - cz (6);

[0084] where a = 10, b = 28, and c = 8 / 3.

[0085] Optionally, referring to Figure 3 , the weight module 02 maps the external signal into the memristor array and performs operations. Among them, the quantization conductance mapping formula may include formula (7) and formula (8):

[0086] ΔG = (G_ max -G_ min ) / 2 n-1 (7);

[0087] G = [W / ΔG] × ΔG (8);

[0088] Among them, G_ max represents the maximum variable conductance of the memristor; G_ min represents the minimum variable conductance of the memristor; W is the weight to be mapped; G is the conductance value mapped to the corresponding position of the memristor array.

[0089] Figure 6 shows a mapping schematic diagram for mapping the linear feature vector at the target moment to the memristor array according to an embodiment of the present application. As Figure 6 shown, the size of the memristor array is 64 × 64. The linear feature vector O_ lin，i constituted by the three-dimensional time series signal at the i-th moment in the weather prediction model time series can be selected, and the linear feature vector O_ lin，i is mapped onto the memristor array, and 0 is filled in the remaining places. Its resistance matrix is expressed as the following formula (9):

[0090]

[0091] Step 203: Control the memristor array to determine the non-linear feature vector based on the linear feature vector at the target moment through Ohm's law and Kirchhoff's law.

[0092] In the present application, the non-linear feature vector O_ nonlin,i can be obtained by the memristor array through Ohm's law and Kirchhoff's law.

[0093] Step 204: Control the memristor array to determine the total feature vector at the target moment based on the linear feature vector and the non-linear feature vector at the target moment in combination with the target constant.

[0094] In the present application, the constant c, O_ lin,i and O_ nonlin,i can be spliced together to obtain the total feature vector O_ total,i : as shown in formula (10):

[0095] O_ total,i = [c, O_lin,i , O_ nonlin,i (10).

[0096] Step 205: Control the memristor array to predict the input data coordinates at the next moment based on the total feature vector and the output mapping weight at the target moment, so that the output module can convert the input data coordinates into the output value of the digital signal to complete the output.

[0097] In this application, the memristor array can determine the predicted value at the next moment (i + 1):

[0098] [x_ i+1 , y_ i+1 , z_ i+1 = O_ total,i ·W_ out

[0099] where [x_ i+1 , y_ i+1 , z_ i+1 is the three-dimensional coordinate of the predicted point at the (i + 1)-th moment.

[0100] Optionally, referring to Figure 3 , the output module 03 can convert the output of the memristor array A into a digital signal through the analog-to-digital converter (ADC) in the output module, and its output accuracy is the accuracy of the ADC.

[0101] Exemplarily, Figure 7 shows a schematic diagram of a prediction experiment provided by an embodiment of this application. Keeping the input accuracy as fixed-point integer 32bit and the output accuracy as fixed-point integer 64bit, Figure 7 successively shows the schematic diagrams of the prediction results and their xz cross-sections when performing prediction experiments under the conditions of weight accuracies of 4bit, 6bit, 8bit, 16bit, 32bit, and 64bit. It can be seen from Figure 7 that chaotic phenomena cannot be generated when the weight accuracy is 4it or 6bit; when the weight accuracy reaches 8bit and above, obvious Lorenz chaotic attractors begin to appear. It is proved that when the weight accuracy corresponding to the memristor array reaches a certain value, the system composed of the NGRC structure implemented based on the memristor array can transition from a stable state to a chaotic state.

[0102] The hardware implementation method of reservoir in-memory computing provided by the embodiments of the present application can obtain the voltage signal transmitted from the input module to the memristor array; map the linear feature vector at the target moment to the memristor array based on the voltage signal; control the memristor array to determine the non-linear feature vector based on the linear feature vector at the target moment; control the memristor array to determine the total feature vector at the target moment based on the linear feature vector and the non-linear feature vector at the target moment; control the memristor array to predict the input data coordinates at the next moment based on the total feature vector at the target moment, so that the output module can convert the input data coordinates into the output value of the digital signal to complete the output. Among them, due to the above-mentioned reservoir in-memory computing, the matrix-vector multiplication operation in the non-linear vector autoregressive process is completed by using the memristor array, effectively reducing the data transfer in the calculation process, providing a new way for the hardware implementation of reservoir computing, improving the computing rate of reservoir computing, and improving the reliability and stability of reservoir computing.

[0103] Figure 8 The structural schematic diagram of a hardware implementation device of reservoir in-memory computing provided by the embodiments of the present application is shown, which is applied to an electronic device having an input module, a weight module composed of a memristor array, and an output module connected in sequence, such as Figure 8 As shown, the hardware implementation device 300 of reservoir in-memory computing includes:

[0104] An acquisition module 301, configured to acquire the voltage signal transmitted from the input module to the memristor array;

[0105] A mapping module 302, configured to map the linear feature vector at the target moment to the memristor array based on the voltage signal;

[0106] A first control module 303, configured to control the memristor array to determine the non-linear feature vector based on the linear feature vector at the target moment;

[0107] A second control module 304, configured to control the memristor array to determine the total feature vector at the target moment based on the linear feature vector and the non-linear feature vector at the target moment;

[0108] A third control module 305, configured to control the memristor array to predict the input data coordinates at the next moment based on the total feature vector at the target moment, so that the output module can convert the input data coordinates into the output value of the digital signal to complete the output.

[0109] Optionally, the first control module includes:

[0110] A first control sub-module, configured to control the memristor array to determine the non-linear feature vector based on the linear feature vector at the target moment through Ohm's law and Kirchhoff's law.

[0111] Optionally, the second control module includes:

[0112] A second control sub-module, configured to control the memristor array to determine a total feature vector at a target time based on the linear feature vector and the non-linear feature vector at the target time, in combination with a target constant.

[0113] Optionally, the third control module includes:

[0114] A third control sub-module, configured to control the memristor array to predict the input data coordinates at the next time based on the total feature vector at the target time and the output mapping weights;

[0115] The linear feature vector at the target time is a linear feature vector composed of three-dimensional time series signals at the i-th time in the weather prediction model time series.

[0116] The hardware implementation device for reservoir in-memory computing provided by the embodiments of the present application can obtain the voltage signal transmitted by the input module to the memristor array; map the linear feature vector at the target time to the memristor array based on the voltage signal; control the memristor array to determine the non-linear feature vector based on the linear feature vector at the target time; control the memristor array to determine the total feature vector at the target time based on the linear feature vector and the non-linear feature vector at the target time; control the memristor array to predict the input data coordinates at the next time based on the total feature vector at the target time, so that the output module can convert the input data coordinates into an output value of a digital signal for output. Among them, due to the above-mentioned reservoir in-memory computing, the matrix-vector multiplication operation in the non-linear vector autoregressive process is completed by using the memristor array, effectively reducing the data transfer in the calculation process, providing a new way for the hardware implementation of reservoir computing, improving the computing rate of reservoir computing, and improving the reliability and stability of reservoir computing.

[0117] A hardware implementation device for reservoir in-memory computing provided by the present application is applied to a hardware implementation method for reservoir in-memory computing as shown in any one of Figures 1 to 7 the above, and for the sake of avoiding repetition, it will not be elaborated here.

[0118] The electronic device in the embodiments of the present application may be a device, or a component, an integrated circuit, or a chip in a terminal. The device may be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device may be a mobile phone, a tablet computer, a laptop computer, a handheld computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc. The non-mobile electronic device may be a server, a Network Attached Storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, etc. The embodiments of the present application do not make specific limitations.

[0119] The electronic device in the embodiments of the present application may be a device with an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems. The embodiments of the present application do not make specific limitations.

[0120] Figure 9 The schematic hardware structure diagram of an electronic device provided by the embodiments of the present application is shown. As Figure 9 shown, the electronic device 400 includes a processor 410.

[0121] As Figure 9 shown, the above-mentioned processor 410 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application solution.

[0122] As Figure 9 shown, the above-mentioned electronic device 400 may further include a communication line 440. The communication line 440 may include a path for transmitting information between the above-mentioned components.

[0123] Optionally, as Figure 9 shown, the above-mentioned electronic device may further include a communication interface 420. The communication interface 420 may be one or more. The communication interface 420 may use any transceiver-like device for communicating with other devices or communication networks.

[0124] Optionally, as Figure 9As shown in the figure, the electronic device may further include a memory 430. The memory 430 is used to store computer-executable instructions for implementing the solution of this application, and is controlled by the processor for execution. The processor is used to execute the computer-executable instructions stored in the memory, so as to implement the method provided in the embodiments of this application.

[0125] As Figure 9 shown in the figure, the memory 430 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or may also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 430 may exist independently and be connected to the processor 410 through a communication line 440. The memory 430 may also be integrated with the processor 410.

[0126] Optionally, the computer-executable instructions in the embodiments of this application may also be referred to as application code, and the embodiments of this application do not make specific limitations thereto.

[0127] In a specific implementation, as an embodiment, as Figure 9 shown in the figure, the processor 410 may include one or more CPUs, such as Figure 9 CPU0 and CPU1 in the figure.

[0128] In a specific implementation, as an embodiment, as Figure 9 shown in the figure, the terminal device may include multiple processors, such as Figure 9 the first processor 4101 and the second processor 4102 in the figure. Each of these processors may be a single-core processor or a multi-core processor.

[0129] Figure 10 is a schematic structural diagram of a chip provided in the embodiments of this application. As Figure 10 shown in the figure, the chip 500 includes one or two or more (including two) processors 410.

[0130] Optionally, as Figure 10As shown, the chip further includes a communication interface 420 and a memory 430. The memory 430 may include a read-only memory and a random access memory, and provide operation instructions and data to the processor. A part of the memory may further include a non-volatile random access memory (NVRAM).

[0131] In some embodiments, as Figure 10 shown, the memory 430 stores the following elements, execution modules or data structures, or subsets thereof, or extended sets thereof.

[0132] In the embodiments of the present application, as Figure 10 shown, by invoking the operation instructions stored in the memory (the operation instructions may be stored in the operating system), corresponding operations are performed.

[0133] As Figure 10 shown, the processor 410 controls the processing operations of any one of the terminal devices. The processor 410 may also be referred to as a central processing unit (CPU).

[0134] As Figure 10 shown, the memory 430 may include a read-only memory and a random access memory, and provide instructions and data to the processor. A part of the memory 430 may further include NVRAM. For example, in an application, the memory, the communication interface, and the memory are coupled together through a bus system. The bus system may include a power bus, a control bus, a status signal bus, etc. in addition to a data bus. However, for the sake of clarity, in Figure 10 all the various buses are labeled as the bus system 540.

[0135] As Figure 10As shown, the method disclosed in the embodiments of the present application can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor or the instructions in the form of software. The above-mentioned processor may be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by the combination of the hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0136] On the one hand, a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium. When the instructions are run, the functions executed by the terminal device in the above embodiments are realized.

[0137] On the one hand, a chip is provided. The chip is applied to a terminal device. The chip includes at least one processor and a communication interface. The communication interface is coupled to the at least one processor. The processor is used to run instructions to realize the functions executed by the hardware implementation method of in-memory computing in the above embodiments.

[0138] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are executed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user device, or other programmable devices. The computer program or instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid state drive (SSD).

[0139] Although the present application has been described in connection with various embodiments, however, in the process of implementing the claimed present application, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0140] Although the present application has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the present application. Accordingly, the present specification and the drawings are merely exemplary illustrations of the present application defined by the appended claims, and are considered to have covered any and all modifications, variations, combinations, or equivalents within the scope of the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A hardware implementation method for reservoir in-memory computing, characterized in that, applied to an electronic device having an input module, a weight module composed of a memristor array, and an output module connected in sequence, the method includes: Obtaining a voltage signal transmitted by the input module to the memristor array; Mapping a target-time linear feature vector to the memristor array based on the voltage signal; Controlling the memristor array to determine a non-linear feature vector based on the target-time linear feature vector; Controlling the memristor array to determine a total feature vector at the target time based on the target-time linear feature vector and the non-linear feature vector; Controlling the memristor array to predict the input data coordinates at the next time based on the total feature vector at the target time, so that the output module converts the input data coordinates into an output value of a digital signal to complete the output.

2. The hardware implementation method for reservoir in-memory computing according to claim 1, characterized in that, The controlling the memristor array to determine a non-linear feature vector based on the target-time linear feature vector includes: Controlling the memristor array to determine the non-linear feature vector based on the target-time linear feature vector through Ohm's law and Kirchhoff's law.

3. The hardware implementation method for reservoir in-memory computing according to claim 1, characterized in that, The controlling the memristor array to determine a total feature vector at the target time based on the target-time linear feature vector and the non-linear feature vector includes: Controlling the memristor array to determine a total feature vector at the target time based on the target-time linear feature vector, the non-linear feature vector, and a target constant.

4. The hardware implementation method for reservoir in-memory computing according to claim 1, characterized in that, The controlling the memristor array to predict the input data coordinates at the next time based on the total feature vector at the target time includes: Controlling the memristor array to predict the input data coordinates at the next time based on the total feature vector at the target time and the output mapping weight.

5. The hardware implementation method for reservoir in-memory computing according to any one of claims 1-4, characterized in that, The target-time linear feature vector is a linear feature vector composed of three-dimensional time-series signals at the i-th time in the weather prediction model time series.

6. A hardware implementation device for reservoir in-memory computing, characterized in that, applied to an electronic device having an input module, a weight module composed of a memristor array, and an output module connected in sequence, the device includes: An acquisition module for acquiring a voltage signal transmitted by the input module to the memristor array; A mapping module for mapping a target-time linear feature vector to the memristor array based on the voltage signal; A first control module for controlling the memristor array to determine a non-linear feature vector based on the target-time linear feature vector; A second control module for controlling the memristor array to determine a total feature vector at the target time based on the target-time linear feature vector and the non-linear feature vector; A third control module, configured to control the memristor array to predict the input data coordinates at the next moment based on the total feature vector at the target moment, so that the output module can convert the input data coordinates into an output value of a digital signal to complete the output.

7. The hardware implementation device for reservoir in-memory computing according to claim 6, wherein, the first control module includes: A first control sub-module, configured to control the memristor array to determine the non-linear feature vector based on the linear feature vector at the target moment through Ohm's law and Kirchhoff's law.

8. The hardware implementation device for reservoir in-memory computing according to claim 6, wherein, the second control module includes: A second control sub-module, configured to control the memristor array to determine the total feature vector at the target moment by combining the linear feature vector and the non-linear feature vector at the target moment with a target constant.

9. The hardware implementation device for reservoir in-memory computing according to claim 6, wherein, the third control module includes: A third control sub-module, configured to control the memristor array to predict the input data coordinates at the next moment based on the total feature vector and the output mapping weight at the target moment; The linear feature vector at the target moment is a linear feature vector composed of three-dimensional time series signals at the i-th moment in the time series of the weather prediction model.

10. An electronic device, wherein, it includes: One or more processors; And one or more machine-readable media storing instructions thereon, which when executed by the one or more processors cause the electronic device to execute the hardware implementation method for reservoir in-memory computing according to any one of claims 1-5.

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