Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element has a first semiconductor die, a first conductive layer, a first etch stop layer on the first conductive layer, a second semiconductor die having a second conductive layer on the first etch stop layer, a second etch stop layer on the second conductive layer, a first through-substrate via along the second semiconductor die and the first etch stop layer, extending to the first semiconductor die and on the first conductive layer, and a second through-substrate via extending to the second semiconductor die, along the second etch stop layer, and on the second conductive layer. A thickness of the second etch stop layer is greater than a thickness of the first etch stop layer.

Description

Technical Field

[0001] This disclosure asserts priority and benefits to U.S. Official Application No. 17 / 087,073, filed November 2, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the semiconductor device. In particular, it relates to a semiconductor device having an etch-stop layer of considerable thickness and a method for fabricating the semiconductor device. Background Technology

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is gradually shrinking to meet the ever-increasing demands for computing power. However, this shrinking process introduces new and increasing problems, both in number and complexity. Therefore, the challenge of improving quality, yield, performance, and reliability, while reducing complexity, continues.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device having a first semiconductor die including a first conductive layer; a first etch-stop layer located on the first conductive layer; a second semiconductor die including a second conductive layer located on the first etch-stop layer; a second etch-stop layer located on the second conductive layer; a first through-substrate via disposed along the second semiconductor die and the first etch-stop layer, extending to the first semiconductor die and located on the first conductive layer; and a second through-substrate via extending to the second semiconductor die, disposed along the second etch-stop layer, and located on the second conductive layer. The thickness of the second etch-stop layer is greater than the thickness of the first etch-stop layer.

[0006] In some embodiments, the first etch stop layer and the second etch stop layer comprise the same material.

[0007] In some embodiments, the thickness of the second etch-stop layer is a ratio of the thickness of the first etch-stop layer to approximately 1.1 to approximately 2.0.

[0008] In some embodiments, the width of the second through-substrate via is equal to or greater than the width of the first through-substrate via.

[0009] In some embodiments, the semiconductor device further includes an upper conductive layer located on the first through-substrate via and the second through-substrate via.

[0010] In some embodiments, the semiconductor device further includes a plurality of insulating layers located on each sidewall of the first through-substrate via, wherein the plurality of insulating layers comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate, or a combination thereof.

[0011] In some embodiments, the semiconductor device further includes an adhesive layer located between the first conductive layer and the first through-substrate via, wherein the adhesive layer comprises titanium, tantalum, titanium tungsten, or manganese nitride.

[0012] In some embodiments, the semiconductor device further includes a seed layer located between the first conductive layer and the first through-substrate via, wherein the seed layer comprises copper or ruthenium.

[0013] In some embodiments, the semiconductor element further includes a first bonding layer located on the first etch-stop layer and between the first semiconductor die and the second semiconductor die.

[0014] In some embodiments, the aspect ratio of the second through-substrate via is between approximately 1:6 and approximately 1:15.

[0015] In some embodiments, the second semiconductor die includes a second dielectric layer and a second substrate, the second dielectric layer being located on the first bonding layer, the second substrate being located on the second dielectric layer, the second conductive layer and the second etch stop layer being located in the second dielectric layer, and the second through-substrate via being disposed along the second substrate, extending to the second dielectric layer, disposed along the second etch stop layer, and located on the second conductive layer.

[0016] In some embodiments, the second dielectric layer comprises silicon oxide, and the first etch stop layer and the second etch stop layer comprise silicon nitride, silicon oxynitride, or silicon carbonitride.

[0017] In some embodiments, the seed layer has a thickness between about 10 nm and about 40 nm.

[0018] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a first semiconductor die, the first semiconductor die including a first conductive layer; forming a first etch-stop layer on the first conductive layer; bonding a second semiconductor die to the first etch-stop layer, wherein the second semiconductor die includes a second conductive layer and a second etch-stop layer, the second conductive layer being located on the first etch-stop layer, the second etch-stop layer being located on the second conductive layer, and the second etch-stop layer having a thickness greater than the thickness of the first etch-stop layer; performing a via etching process to simultaneously form a first via opening and a second via opening, wherein... In this process, the first etch stop layer is exposed through the first via opening, and the second etch stop layer is exposed through the second via opening; a plurality of insulating layers are conformally formed in the first via opening and the second via opening; a punch etching process is performed to extend the first via opening and the second via opening by removing the plurality of insulating layers formed on the first via opening and the second via opening, the first etch stop layer formed on the first conductive layer, and the second etch stop layer formed on the second conductive layer; and a first through-substrate via and a second through-substrate via are integrally formed in the first via opening and the second via opening.

[0019] In some embodiments, the first etch stop layer and the second etch stop layer comprise the same material.

[0020] In some embodiments, the first etch stop layer and the second etch stop layer comprise silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0021] In some embodiments, the through-hole etching process uses an etchant comprising perfluoroisobutylene or hexafluorobutadiene.

[0022] In some embodiments, the punching etching process uses an etchant that contains tetrafluoromethane.

[0023] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a first semiconductor die, the first semiconductor die including a first conductive layer; forming a first etch stop layer on the first conductive layer; bonding a second semiconductor die to the first etch stop layer, wherein the second semiconductor die includes a second conductive layer and a second etch stop layer, the second conductive layer being located on the first etch stop layer, the second etch stop layer being located on the second conductive layer, and the second etch stop layer including a material having an etch selectivity relative to the first etch stop layer; performing a via etching process to simultaneously form a first via opening and a... A second via opening, wherein the first etch stop layer is exposed through the first via opening, and the second etch stop layer is exposed through the second via opening; a plurality of insulating layers are conformally formed in the first via opening and the second via opening; a punching etch process is performed to extend the first via opening and the second via opening by removing the plurality of insulating layers formed on the first via opening and the second via opening, the first etch stop layer formed on the first conductive layer, and the second etch stop layer formed on the second conductive layer; and simultaneously forming a first through-substrate via in the first via opening and a second through-substrate via in the second via opening.

[0024] In some embodiments, the via etching process has an etch ratio between the first etch stop layer and the second etch stop layer, which is between approximately 1.05:1 and approximately 25:1.

[0025] Due to the design of the semiconductor device disclosed herein, the greater thickness of the second etch-stop layer can compensate for the adverse effect of over-etching during the formation of the plurality of via openings. Therefore, the yield / performance of the semiconductor device can be improved.

[0026] The technical features and advantages of this disclosure have been summarized quite extensively above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0027] A more complete understanding of the disclosure can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0028] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure is shown.

[0029] Figures 2 to 15 A cross-sectional schematic diagram illustrating the fabrication process of the semiconductor device according to an embodiment of the present disclosure.

[0030] Figures 16 to 20 A cross-sectional schematic diagram illustrating a portion of the fabrication process for preparing the semiconductor device according to another embodiment of this disclosure.

[0031] Figure 21 A cross-sectional schematic diagram illustrating a portion of the fabrication process for preparing the semiconductor device according to another embodiment of this disclosure.

[0032] Figures 22 to 24 A cross-sectional schematic diagram illustrating a portion of the fabrication process for preparing the semiconductor device according to another embodiment of this disclosure.

[0033] Figures 25 to 27 A cross-sectional schematic diagram illustrating a portion of a fabrication process for preparing the semiconductor device according to another embodiment of the present disclosure.

[0034] Explanation of reference numerals in the attached figures:

[0035] 1A: Semiconductor components

[0036] 1B: Semiconductor components

[0037] 1C: Semiconductor components

[0038] 1D: Semiconductor components

[0039] 1E: Semiconductor components

[0040] 10: Preparation method

[0041] 100: First semiconductor die

[0042] 101: First basement

[0043] 103: First dielectric layer

[0044] 105: First Device

[0045] 107: First conductive layer

[0046] 200: Second semiconductor die

[0047] 201: Second basement

[0048] 203: Second dielectric layer

[0049] 205: Second device

[0050] 207: Second conductive layer

[0051] 301: First etch stop layer

[0052] 301BS: Lower surface

[0053] 303: Second etch stop layer

[0054] 305: First bonding layer

[0055] 307: Second bonding layer

[0056] 309: First passivation layer

[0057] 311: Insulation layer

[0058] 311SW: Sidewall

[0059] 313: Barrier Layer

[0060] 315: Adhesive layer

[0061] 317: Seed layer

[0062] 319: Upper conductive layer

[0063] 321: First through-hole in the substrate

[0064] 321SW: Sidewall

[0065] 323: Second through-hole in the substrate

[0066] 323SW: Sidewall

[0067] 325: Adjustment Layer

[0068] 325SW: Sidewall

[0069] 401: First Opening

[0070] 403: First mask layer

[0071] 405: First through hole opening

[0072] 407: Second through hole opening

[0073] 409: Filler material

[0074] 411: First concave space

[0075] 411BS: Lower surface

[0076] 411SW: Sidewall

[0077] 413: Second recessed space

[0078] D1: Depth

[0079] D2: Depth

[0080] D3: Depth

[0081] S11: Steps

[0082] S13: Steps

[0083] S15: Steps

[0084] S21: Steps

[0085] S23: Steps

[0086] S25: Steps

[0087] T1: Thickness

[0088] T2: Thickness

[0089] T3: Thickness

[0090] W1: Width

[0091] W2: Width

[0092] W3: Width

[0093] W4: Width

[0094] Z: Direction Detailed Implementation

[0095] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0096] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0097] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0098] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0099] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, substantially identical orientation, layout, location, shape, size, amount, or other measure, for example, that may occur due to manufacturing processes. The term “substantially” may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" can mean exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which may occur due to the manufacturing process.

[0100] In this disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor elements.

[0101] It should be understood that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, while "below" corresponds to the opposite direction of the Z-direction arrow.

[0102] Figure 1 A schematic flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure is shown. Figures 2 to 15 A cross-sectional schematic diagram illustrating the fabrication process of the semiconductor device 1A according to an embodiment of the present disclosure.

[0103] Please refer to Figure 1 and Figure 2 In step S11, a first semiconductor die 100 may be provided, and the first semiconductor die 100 includes a first conductive layer 107, a first etch stop layer 301 may be formed on the first conductive layer 107, and a first bonding layer 305 may be formed on the first etch stop layer 301.

[0104] Please refer to Figure 2 The first semiconductor die 100 may include a first substrate 101, a first dielectric layer 103, a plurality of first devices 105 (only two are shown for clarity) and a first conductive layer 107.

[0105] For example, the first substrate 101 may comprise silicon, germanium, silicon-germanium, silicon-carbon, silicon-germanium-carbon, gallium, gallium arsenide, indium arsenide, indium phosphorus, or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the first substrate 101 may comprise an organic semiconductor or a single-layer semiconductor, such as silicon / silicon-germanium, silicon-on-insulator, or silicon-germanium-on-insulator. When the substrate 101 comprises silicon-on-insulator, the substrate 101 may comprise an upper semiconductor layer and a lower semiconductor layer containing silicon, and a buried isolation layer that separates the upper semiconductor layer from the lower semiconductor layer. For example, the buried isolation layer may comprise a crystalline or non-crystalline oxide, nitride, or any combination thereof.

[0106] Please refer to Figure 2 A first dielectric layer 103 may be formed on a first substrate 101. In some embodiments, the first dielectric layer 103 may be a stacked layer structure. The first dielectric layer 103 may include a plurality of first isolation sublayers. Each first isolation sublayer may have a thickness between approximately 0.5 μm and approximately 3.0 μm. For example, the plurality of first isolation sublayers may comprise silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, the like, or combinations thereof. The plurality of first isolation sublayers may comprise different materials, but are not limited thereto. The low-k dielectric material may have a dielectric constant less than 3.0, or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0. In the described embodiment, the first dielectric layer 103 comprises silicon oxide.

[0107] The fabrication technique for the first dielectric layer 103 may include multiple deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. Following these deposition processes, multiple planarization processes may be performed to remove excess material and provide a generally flat surface for subsequent processing steps. After the first dielectric layer 103 is formed, the plurality of first devices 105 and the first conductive layer 107 may be formed.

[0108] Please refer to Figure 2 The plurality of first devices 105 may be formed in a lower portion of the first dielectric layer 103. In some embodiments, the plurality of first devices 105 may be formed on the first substrate 101. For example, the plurality of first devices 105 may be bipolar junction transistors, metal-oxide-semiconductor field-effect transistors, diodes, flash memory, dynamic random access memory, static random access memory, electrically erasable programmable read-only memory, image sensors, microelectromechanical systems, active components, or passive components.

[0109] Please refer to Figure 2 A first conductive layer 107 may be formed on top of the first dielectric layer 103. In the described embodiment, the upper surface of the first conductive layer 107 may be substantially coplanar with the upper surface of the first dielectric layer 103. The first conductive layer 107 may be a pad layer of the first semiconductor die 100. For example, the first conductive layer 107 may comprise aluminum, copper, aluminum-copper alloy, aluminum alloy, copper alloy, or other suitable conductive materials. The fabrication technique of the first conductive layer 107 may include a deposition process and a subsequent photoetching process, the deposition process being, for example, chemical vapor deposition, physical vapor deposition, evaporation, or sputtering, and the photoetching process defining the pattern of the first conductive layer 107.

[0110] Please refer to Figure 2 The first etch stop layer 301 may be formed on the first conductive layer 107 and the first dielectric layer 103. The fabrication technology of the first etch stop layer 301 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition or similar processes.

[0111] Please refer to Figure 2A first bonding layer 305 may be formed on the first etch-stop layer 301. In some embodiments, for example, the first bonding layer 305 may comprise an organic material selected from the following: undoped silicate glass, silicon nitride, silicon oxynitride, silicon oxide, silicon nitride oxide, and combinations thereof. In some embodiments, for example, the first bonding layer 305 may comprise a polymer layer, such as an epoxy resin, polyimide, benzocyclobutene, polybenzoxazole, or the like. The fabrication technique of the first bonding layer 305 may include a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a plurality of dummy conductive layers (not shown for clarity) may be formed in the first bonding layer 305. The upper surfaces of each of the plurality of dummy conductive layers may be substantially coplanar with the upper surface of the first bonding layer 305.

[0112] For example, the plurality of virtual conductive layers may comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0113] It should be understood that, in the description of this disclosure, an element is considered a "dummy" element, meaning that when semiconductor element 1A is in operation, no external voltage or current is applied to the element.

[0114] Please refer to Figure 1 and Figure 3 In step S13, a second semiconductor die 200 may be provided, and the second semiconductor die 200 has a second conductive layer 207 and a second etch stop layer 303, and a second bonding layer 307 may be formed on the second semiconductor die 200.

[0115] Please refer to Figure 3 The second semiconductor die 200 and the first semiconductor die 100 can provide different functions. For example, the first semiconductor die 100 can provide a logic function, and the second semiconductor die 200 can provide a memory function. In some embodiments, the first semiconductor die 100 and the second semiconductor die 200 can provide the same function.

[0116] Please refer to Figure 3The second semiconductor die 200 may have a structure similar to that of the first semiconductor die 100. The second semiconductor die 200 may include a second substrate 201, a second dielectric layer 203, a plurality of second devices 205 (only one is shown for clarity), a second conductive layer 207, and a second etch-stop layer 303. Similar element designations between the first semiconductor die 100 and the second semiconductor die 200 may include the same materials, and their fabrication techniques may include the same processes, but are not limited thereto. For example, the second substrate 201 may contain the same material as the first substrate 101.

[0117] In some embodiments, the second conductive layer 207 may be formed in the second dielectric layer 203. The second conductive layer 207 may be a back end conductive line of the second semiconductor die 200. For example, the second conductive layer 207 may comprise copper, aluminum, titanium, tungsten, the like, or a combination thereof.

[0118] In some embodiments, the second conductive layer 207 may be a pad layer of the second semiconductor die 200. The upper surface of the second conductive layer 207 may be substantially coplanar with the upper surface of the second dielectric layer 203. The second conductive layer 207 may contain the same material as the first conductive layer 107, but is not limited thereto.

[0119] Please refer to Figure 3 The second etch stop layer 303 may be formed on the second conductive layer 207 and in the second dielectric layer 203. The fabrication techniques for the second etch stop layer 303 include chemical vapor deposition, plasma-enhanced chemical vapor deposition or similar processes, and the second etch stop layer 303 may be formed during the formation of the second dielectric layer 203.

[0120] Please refer to Figure 3 The second bonding layer 307 may be formed on the second semiconductor die 200. In particular, the second bonding layer 307 may be formed on the second dielectric layer 203. The second bonding layer 307 may contain the same material as the first bonding layer 305. In some embodiments, a plurality of dummy conductive layers (not shown for clarity) may be formed in the second bonding layer 307. The upper surfaces of each of the plurality of dummy conductive layers may be substantially coplanar with the upper surface of the second bonding layer 307.

[0121] Please refer to Figure 1 and Figure 4 In step S15, the second semiconductor die 200 can be bonded to the first semiconductor die 100 in an upside-down manner via a bonding process.

[0122] Please refer to Figure 4The second semiconductor die 200 and the first semiconductor die 100 can be bonded face-to-face. Specifically, during the bonding process, a second bonding layer 307 can be placed on the first bonding layer 305. A second dielectric layer 203 can be placed on the second bonding layer 307. A second substrate 201 can be placed on the second dielectric layer 203. A second conductive layer 207 can be placed above the first etch-stop layer 301. The second etch-stop layer 303 can be placed on the second conductive layer 207. In some embodiments, the second semiconductor die 200 and the first semiconductor die 100 can be bonded back-to-face.

[0123] In some embodiments, a thermal processing step may be performed to achieve a hybrid bonding between multiple elements of the first bonding layer 305 and the second bonding layer 307 for the bonding process. A temperature of the bonding process may be between approximately 300°C and approximately 450°C. The hybrid bonding may include a dielectric-to-dielectric bonding and / or a metal-to-metal bonding. The dielectric-to-dielectric bonding may originate from the bonding between the first bonding layer 305 and the second bonding layer 307. The metal-to-metal bonding may originate from the bonding between the multiple dummy conductive layers in the first bonding layer 305 and the second bonding layer 307. That is, the multiple dummy conductive layers facilitate the bonding process between the first semiconductor die 100 and the second semiconductor die 200.

[0124] In some embodiments, the first etch stop layer 301 and the second etch stop layer 303 may comprise the same material, such as silicon nitride, silicon oxynitride, silicon nitride oxide, or silicon carbide nitride. A thickness T2 of the second etch stop layer 303 may be greater than a thickness T1 of the first etch stop layer 301. The ratio of the thickness T2 of the second etch stop layer to the thickness T1 of the first etch stop layer is between approximately 1.1 and 2.0. The thickness T2 of the second etch stop layer 303 may compensate for adverse reactions arising from over-etching during the formation of the plurality of via openings, as described later.

[0125] It should be understood that, in this disclosure, silicon oxynitride represents a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide represents a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0126] In some embodiments, the first etch stop layer 301 and the second etch stop layer 303 may comprise different materials. For example, the first etch stop layer 301 may comprise a material that has etch selectivity for the second etch stop layer 303. For example, the first etch stop layer 301 and the second etch stop layer 303 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon carbide nitride, silicon boron nitride, or boron carbon silicon nitride. In some embodiments, the first etch stop layer 301 and the second etch stop layer 303 have the same thickness. In some embodiments, the first etch stop layer 301 and the second etch stop layer 303 may have different thicknesses. The thickness T1 of the first etch stop layer 301 and the thickness T2 of the second etch stop layer 303 can be determined based on the etch selectivity of the first etch stop layer 301 for the second etch stop layer 303.

[0127] Please refer to Figure 1 , Figure 5 and Figure 6 In step S17, a first passivation layer 309 may be formed on the second substrate 201 of the second semiconductor die 200, and a first opening 401 may be formed in the first passivation layer 309.

[0128] Please refer to Figure 5 The first passivation layer 309 may be formed on the second substrate 201 by a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, for example, the first passivation layer 309 comprises an organic material selected from the following: silicon nitride, silicon oxynitride, silicon oxide, silicon nitride oxynitride, or combinations thereof. In some embodiments, for example, the first passivation layer 309 may comprise a polymer layer, such as epoxy resin, polyimide, benzocyclobutene, polybenzoxazole, or the like.

[0129] In some embodiments, before forming the first passivation layer 309, the second substrate 201 can be thinned by a thinning process. The thinning process can be an etching process, a chemical polishing process, or a polishing process.

[0130] Please refer to Figure 6 The first opening 401 can be formed in the first passivation layer 309 by a photolithography process followed by an etching process.

[0131] Please refer to Figure 1 , Figure 7 and Figure 9In step S19, a first through-hole opening 405 and a second through-hole opening 407 can be formed simultaneously to expose the first etch stop layer 301 and the second etch stop layer 303.

[0132] Please refer to Figure 7 A first mask layer 403 may be formed on the first passivation layer 309 and in the first opening 401 by a photolithography process. The first mask layer 403 may have a pattern of a first through-hole opening 405 and a second through-hole opening 407.

[0133] Please refer to Figure 8 A via etching process can be performed to simultaneously form a first via opening 405 and a second via opening 407. In some embodiments, the via etching process can be a multi-step anisotropic dry etching process. The first via opening 405 may be formed by extending from the first opening 401 along the first passivation layer 309, along the second substrate 201, along the second dielectric layer 203, along the second bonding layer 307, and along the first bonding layer 305, and exposes a portion of the first etch stop layer 301. The second via opening 407 may be formed by extending from the first opening 401 along the first passivation layer 309, along the second substrate 201, and along the second dielectric layer 203, and exposes a portion of the second etch stop layer 303.

[0134] Please refer to Figure 8 The width W1 of the first through-hole opening 405 may be equal to or less than the width W2 of the second through-hole opening 407. In some embodiments, the width W2 of the second through-hole opening 407 may be between approximately 5 μm and 15 μm. In some embodiments, the first through-hole opening 405 may have a depth D1, between approximately 20 μm and 160 μm. In particular, the depth D1 of the first through-hole opening 405 may be between approximately 50 μm and approximately 130 μm. In some embodiments, the first through-hole opening 405 may have a depth-to-width ratio between approximately 1:8 and approximately 1:35. In particular, the depth-to-width ratio of the first through-hole opening 405 may be between approximately 1:13 and approximately 1:25. In some embodiments, the second through-hole opening 407 has a depth-to-width ratio between approximately 1:6 and approximately 1:15. In particular, the depth-to-width ratio of the second through-hole opening 407 may be between approximately 1:7 and approximately 1:12.

[0135] In some embodiments, the first through-hole opening 405 and the second through-hole opening 407 have a slight positive slope and / or a tapered profile near their respective upper portions. Such a tapered profile can improve the diffusion of multiple metal ions within the first through-hole opening 405 and the second through-hole opening 407, and can reduce the time required to fill the first through-hole opening 405 and the second through-hole opening 407.

[0136] Conventionally, when simultaneously forming a first via opening 405 and a second via opening 407 with different aspect ratios, the etch duration of the via etching process may need to be long enough to form a deeper via opening (e.g., for the first via opening 405 in this embodiment). In this case, the shallower via opening (e.g., the second via opening 407) may be over-etched. Therefore, the second etch stop layer 303 may be completely removed, potentially damaging the second conductive layer 207.

[0137] In some embodiments, to overcome the aforementioned problems, the via etching process may include multiple etchants rich in carbon and halogens. For example, the multiple etchants may be octafluoroisobutylene or hexafluorobutadiene. The multiple carbon / halogen-rich etchants may react with the second etch stop layer 303 and / or the first etch stop layer 301 to form multiple polymeric byproducts, wherein the second etch stop layer 303 and / or the first etch stop layer 301 comprises silicon nitride, silicon oxynitride, or silicon carbide nitride. The multiple polymeric byproducts may act as multiple protective layers to mitigate adverse reactions caused by over-etching in the via etching process. Furthermore, the greater thickness of the second etch stop layer 303 may act as a buffer to compensate for the adverse reactions of over-etching.

[0138] In some embodiments, during the via etching process, the first etch stop layer 301 may comprise a material having etch selectivity relative to the second etch stop layer 303. For example, the etch ratio of the first etch stop layer 301 to the second etch stop layer 303 is between approximately 1.05:1 and approximately 25:1; particularly, during the via etching process, it is between approximately 1.5:1 and approximately 15:1. In this case, during the via etching process, the etch ratio can be adjusted to modify the thickness T1 of the first etch stop layer 301 and the thickness T2 of the second etch stop layer 303 based on the etch ratio of the first etch stop layer 301 to the second etch stop layer 303. After the first via opening 405 and the second via opening 407 are formed, the first masking layer 403 can be removed.

[0139] In some embodiments, the second etch stop layer 303 may comprise a material having etch selectivity relative to the second dielectric layer 203. For example, the etch rate of the first etch stop layer 301 to the second etch stop layer 303 may be between approximately 1.05:1 and approximately 25:1; in particular, during the via etching process, the etch rate is between approximately 105:1 and approximately 15:1.

[0140] Please refer to Figure 1 and Figure 9 In step S21, an insulating layer 311 may be conformally formed in the first opening 401, the first through-hole opening 405, and the second through-hole opening 407.

[0141] Please refer to Figure 9 In some embodiments, for example, the insulating layer 311 may comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, or a combination thereof. The insulating layer 311 may have a thickness between approximately 50 nm and approximately 200 nm. For example, the fabrication technique of the insulating layer 311 may include chemical vapor deposition or plasma-enhanced chemical vapor deposition. In some embodiments, for example, the insulating layer 311 may comprise parylene, epoxy resin, or poly(p-xylene). In some embodiments, the insulating layer 311 may have a thickness between approximately 1 μm and approximately 5 μm. For example, the fabrication technique of the insulating layer 311 includes spin coating followed by a curing process.

[0142] Please refer to Figure 1 and Figure 10 In step S23, a punching etching process can be performed to expand the first through hole opening 405 and the second through hole opening 407.

[0143] Please refer to Figure 10 The portion of insulating layer 311 formed on the first etch stop layer 301, the portion of first etch stop layer 301 formed on the first conductive layer 107, the portion of insulating layer 311 formed on the second etch stop layer 303, and the portion of second etch stop layer 303 formed on the second conductive layer 207 can be removed by the punching etching process. After the punching etching process, insulating layer 311 can be divided into multiple segments. First conductive layer 107 can be exposed through first via opening 405. Second conductive layer 207 can be exposed through second via opening 407. In some embodiments, the punching etching process can be a multi-step anisotropic dry etching process. In some embodiments, the punching etching process can include tetrafluoromethane.

[0144] It should be understood that in this disclosure, the term "segment" is used interchangeably with the term "portion".

[0145] Please refer to Figure 1 and Figures 11 to 15 In step S25, a first through-base through-hole 321 may be formed in the first opening 405, and a second through-base through-hole 323 may be formed in the second opening 407.

[0146] Please refer to Figure 11 A barrier layer 313 may be conformally formed on the first conductive layer 107, the second conductive layer 207, and the insulating layer 311. The barrier layer 313 may be located in the first opening 401, the first via opening 405, and the second via opening 407. The barrier layer 313 may have a thickness between approximately 5 nm and approximately 50 nm. For example, the barrier layer 313 may comprise tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a bilayer of tantalum nitride / tantalum. The fabrication technique of the barrier layer 313 may include deposition processes such as physical vapor deposition, ion layer deposition, chemical vapor deposition, or sputtering. The barrier layer 313 may inhibit the diffusion of conductive material from the first through-substrate via 321 and the second through-substrate via 323 into the first semiconductor die 100 or the second semiconductor die 200.

[0147] Please refer to Figure 12 An adhesive layer 315 may be conformally formed on the barrier layer 313, in the first opening 401, in the first via opening 405, and in the second via opening 407. The adhesive layer 315 may have a thickness between approximately 5 nm and approximately 50 nm. For example, the adhesive layer 315 may comprise titanium, tantalum, tungsten titanate, or manganese nitride. The fabrication technique for the adhesive layer 315 may include deposition processes such as physical vapor deposition, ion layer deposition, chemical vapor deposition, or sputtering. The adhesive layer 315 may improve the adhesion between a seed layer to be subsequently fabricated and the barrier layer 313.

[0148] Please refer to Figure 13A seed layer 317 may be formed on the adhesive layer 315, in the first opening 401, in the first via opening 405, and in the second via opening 407. The seed layer may have a thickness between approximately 10 nm and approximately 40 nm. For example, the seed layer 317 may contain copper or ruthenium. The fabrication technique of the seed layer 317 may include deposition processes such as physical vapor deposition, ion layer deposition, chemical vapor deposition, or sputtering. During the formation of the first through-substrate via 321 and the second through-substrate via 323 by an electroplating process, the seed layer 317 may reduce the resistance of the first via opening 405 and the second via opening 407.

[0149] Please refer to Figure 14 A filler material 409 can be formed to completely fill the first through-hole opening 405, the second through-hole opening 407, and the first opening 401. For example, the filler material 409 contains copper. The fabrication technique of the filler material 409 may include an electroplating process using a plating solution. The plating solution may contain copper sulfate, copper methane sulfonate, copper gluconate, copper sulfamate, copper nitrate, copper phosphate, or copper chloride. The pH value of the plating solution may be between approximately 2 and 6; particularly, between approximately 3 and 5. The process temperature of the electroplating process may be maintained between approximately 40°C and approximately 75°C; particularly, between approximately 50°C and approximately 70°C.

[0150] In some embodiments, the plating solution may contain accelerators, suppressors, or levelers. The accelerators may contain a polar sulfur, oxygen, or nitrogen functional group that helps increase the deposition rate and promotes dense nucleation. The accelerators may be present at a low concentration level, for example, between about 0 and about 200 ppm. The suppressors are additives that reduce the plating rate and are typically present in higher concentration plating baths, for example, between about 5 ppm and about 1000 ppm. The suppressors may be polymeric surfactants with high molecular weight, such as polyethylene glycol.

[0151] These multiple inhibitors slow down the deposition rate by absorbing copper ions onto the surface and forming a barrier layer. Due to their large size and low diffusivity, these multiple inhibitors are unlikely to reach the lower portions of the first via opening 405 and the second via opening 407. Therefore, most of the inhibition effect occurs at the lower portions of the first via opening 405 and the second via opening 407, helping to reduce overburdening of the filler material 409 and preventing the first via opening 405 and the second via opening 407 from "closing".

[0152] These multiple balancing agents can be used to improve filling efficiency, reduce surface roughness, and prevent copper deposition at the top of the first via opening 405 and the second via opening 407. The multiple balancing agents can be present at a low concentration, for example, between approximately 1 ppm and approximately 100 ppm. For example, the multiple balancing agents can be 3-mercapto-1-propanesulfonate, (3-sulfopropyl)disulfide, or 3,3-thiobis(1-propanesulfonate).

[0153] In some embodiments, an annealing process may be performed after the layer filler 409 is formed. This annealing process can reduce adverse reactions during copper-pumping in the subsequent semiconductor processes, improve the adhesion between the layer filler 409 and the insulating layer 311, and stabilize the microstructure of the layer filler 409.

[0154] Please refer to Figure 15 A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the first passivation layer 309 is exposed to remove excess material, provide a generally flat surface for subsequent processing steps, and simultaneously form an upper conductive layer 319 in the first opening 401, form a first through-substrate via 321 in the first via opening 405, and form a second through-substrate via 323 in the second via opening 407.

[0155] Please refer to Figure 15 The upper conductive layer 319 may be deposited on the first through-substrate via 321 and the second through-substrate via 323. The first through-substrate via 321 may be disposed along the first passivation layer 309, along the second substrate 201, along the second dielectric layer 203, along the second bonding layer 307, along the first bonding layer 305, along the first etch stop layer 301, extending to the first dielectric layer 103, and disposed on the first conductive layer 107. The second through-substrate via 323 may be disposed along the first passivation layer 309, along the second substrate 201, extending to the second dielectric layer 203, along the second etch stop layer 303, and disposed on the second conductive layer 207.

[0156] Please refer to Figure 15 The width W3 of the first through-hole 321 may be equal to or less than the width W4 of the second through-hole 323. In some embodiments, the width W4 of the second through-hole 323 may be between approximately 5 μm and approximately 15 μm. In some embodiments, the first through-hole 321 may have a depth D2, between approximately 20 μm and approximately 160 μm. In particular, the depth D2 of the first through-hole 321 may be between approximately 50 μm and approximately 130 μm. In some embodiments, the first through-hole 321 may have a depth-to-width ratio between approximately 1:8 and approximately 1:35. In particular, the depth-to-width ratio of the first through-hole 321 may be between approximately 1:13 and approximately 1:25. In some embodiments, the second through-hole 323 may have a depth-to-width ratio between approximately 1:6 and approximately 1:15. In particular, the depth-to-width ratio of the second through-hole 323 may be between approximately 1:7 and approximately 1:12.

[0157] Please refer to Figure 15An insulating layer 311 may be disposed on each sidewall 321SW of the first through-hole 321 and on each sidewall 323SW of the second through-hole 323. A barrier layer 313 may be disposed on the first conductive layer 107, on the second conductive layer 207, between the first through-hole 321 and the insulating layer 311, and between the second through-hole 323 and the insulating layer 311. An adhesive layer 315 may be disposed between the first conductive layer 107 and the first through-hole 321, between the second conductive layer 207 and the second through-hole 323, between the first through-hole 321 and the insulating layer 311, and between the second through-hole 323 and the insulating layer 311. The seed layer 317 may be disposed between the first conductive layer 107 and the first through-substrate via 321, between the second conductive layer 207 and the second through-substrate via 323, between the first through-substrate via 321 and the insulating layer 311, and between the second through-substrate via 323 and the insulating layer 311.

[0158] It should be understood that the same or similar element numbers are used throughout the drawings to indicate the same or similar features, elements or structures, and therefore, for each drawing, a detailed explanation of the same or similar features, elements or structures will not be repeated.

[0159] Figures 16 to 20 A cross-sectional schematic diagram illustrating a portion of the fabrication process for a semiconductor element 1B according to another embodiment of the present disclosure.

[0160] Please refer to Figure 16 An intermediate semiconductor device can be similar to, for example Figures 2 to 5 The process shown is used for manufacturing. A first via opening 405 may be formed along the first passivation layer 309, along the second substrate 201, along the second dielectric layer 203, along the second bonding layer 307, along the first bonding layer 305, and exposes a portion of the first etch-stop layer 301. A second via opening 407 may be formed along the first passivation layer 309, along the second substrate 201, extending to the second dielectric layer 203, and exposing a portion of the second etch-stop layer 303. It should be understood that in this embodiment, there is no first opening.

[0161] Please refer to Figure 17 Insulating layer 311 can be similar to, for example Figure 9 The procedure shown is conformally formed in the first through-hole opening 405 and the second through-hole opening 407.

[0162] Please refer to Figure 18 This punching and etching process can be similar to, for example... Figure 10 The program shown is executed to the point where... Figure 17 The intermediate semiconductor element shown.

[0163] Please refer to Figure 19 Barrier layer 313 can be similar to, for example Figure 11 They are conformally formed in the first through hole opening 405 and the second through hole opening 407 in a process.

[0164] Please refer to Figure 20 It can be similar to, for example Figures 12 to 15 The procedure shown forms a first through-substrate via 321 in a first via opening 405 and a second through-substrate via 323 in a second via opening 407. For clarity, the adhesive layer and seed layer are not shown. The first through-substrate via 321 and the second through-substrate via 323 can be electrically coupled to different external conductive elements and can be individually controlled.

[0165] Figure 21 A cross-sectional schematic diagram illustrating a portion of the fabrication process for a semiconductor device 1C according to another embodiment of the present disclosure.

[0166] Please refer to Figure 21 An intermediate semiconductor device can be similar to, for example Figures 16 to 20 The process shown is used for manufacturing. A first conductive layer 107 may be formed in a first dielectric layer 103. The upper surface of the first conductive layer 107 may be located at a vertical plane, which is lower than a vertical plane of the upper surface of the first dielectric layer 103. A first etch stop layer 301 may be formed in the first dielectric layer 103 and on the first conductive layer 107. A first bonding layer 305 may be formed on the first dielectric layer 103. The first conductive layer 107 may be a back end conductive line of the first semiconductor die 100.

[0167] Figures 22 to 24 A cross-sectional schematic diagram illustrating a portion of the fabrication process for a semiconductor device 1D according to another embodiment of the present disclosure.

[0168] Please refer to Figure 22 An intermediate semiconductor device can be similar to, for example Figures 16 to 20The process shown is used for manufacturing. An expansion etching process can be performed to expand the first via opening 405 and the second via opening 407 in the first passivation layer 309. During the expansion etching process, the etch ratio of the first passivation layer 309 to the second substrate 201 can be between approximately 100:1 and approximately 1.05:1, or between approximately 20:1 and approximately 10:1. In some embodiments, the expansion etching process can be a wet etching process using a wet etching solution. The wet etching solution can be a hydrofluoride solution having a 6:1 buffer oxide etchant and containing 7% w / w hydrofluoric acid, 34% w / w ammonium fluoride, and 59% w / w water. In some embodiments, the expansion etching process can be a dry etching process using a gas selected from the group consisting of CH2F2, CHF3, and C4F8.

[0169] After the extended etching process, the widths of the first via opening 405 and the second via opening 407 in the first passivation layer 309 may widen, while the widths of the first via opening 405 and the second via opening 407 in the second semiconductor die 200 or the first semiconductor die 100 may remain unchanged. Therefore, after the extended etching process, the sidewalls of the first via opening 405 and the second via opening 407 in the first passivation layer 309 may be tapered. The widened first via opening 405 and the widened second via opening 407 in the first passivation layer 309 can eliminate the adverse effects of the faster deposition rate at the first via opening 405 and the second via opening 407 in the first passivation layer 309 by providing additional space, thereby achieving an improved tolerance window. The first via opening 405 and the second via opening 407 in the first passivation layer 309 are used to form multiple void-free filling layers.

[0170] Please refer to Figure 23 Insulating layer 311 can be similar to, for example Figure 9 The process is shown, conformally formed in the first via opening 405 and the second via opening 407. An adjustment layer 325 may be formed to cover the upper portions of the insulating layer 311. The fabrication technique of the adjustment layer 325 may include a deposition process, such as an ion layer deposition method, which precisely controls the amount of a first precursor in the ion layer deposition method. For example, the adjustment layer 325 may comprise alumina, hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tungsten nitride, silicon nitride, or silicon oxide.

[0171] In some embodiments, when the conditioning layer 325 comprises aluminum oxide, the first precursor of the ion layer deposition method may be trimethylaluminum, and a second precursor of the ion layer deposition method may be water or ozone.

[0172] In some embodiments, when the conditioning layer 325 contains hafnium oxide, the first precursor of the ion layer deposition method may be hafnium tetrachloride, hafnium tert-butoxide, hafnium dimethylamide, hafnium ethylmethylamide, hafnium diethylamide, or hafnium methoxy-t-butoxide, and the second precursor of the ion layer deposition method may be water or ozone.

[0173] In some embodiments, when the conditioning layer 325 comprises zirconium oxide, the first precursor of the ion layer deposition method may be zirconium tetrachloride, and the second precursor of the ion layer deposition method may be water or ozone.

[0174] In some embodiments, when the conditioning layer 325 comprises titanium oxide, the first precursor of the ion layer deposition method may be titanium tetrachloride or titanium isopropoxide, and the second precursor of the ion layer deposition method may be water or ozone.

[0175] In some embodiments, when the conditioning layer 325 comprises titanium nitride, the first precursor of the ion layer deposition method may be titanium tetrachloride and ammonia.

[0176] In some embodiments, when the conditioning layer 325 comprises tungsten nitride, the first precursor of the ion layer deposition method may be tungsten hexafluoride and ammonia.

[0177] In some embodiments, when the conditioning layer 325 comprises silicon nitride, the first precursor of the ion layer deposition method may be silylene, chlorine, ammonia and / or dinitrogen tetrahydride.

[0178] In some embodiments, when the adjustment layer 325 comprises silicon oxide, the first precursor of the ion layer deposition method may be silicon tetraisocyanate or CH3OSi(NCO)3, and the second precursor of the ion layer deposition method may be hydrogen or ozone.

[0179] Due to the tapered sidewalls of the first via opening 405 and the second via opening 407 in the first passivation layer 309, the sidewalls 325SW of the plurality of adjustment layers 325 can be substantially vertical. During subsequent semiconductor processes, the plurality of adjustment layers 325 can provide additional protection for the first passivation layer 309 and the second substrate 201. Therefore, metal-to-silicon leakage typically occurs at the interface between the first passivation layer 309 and the second substrate 201, while preventing the formation of the first through-substrate via 321 and the second through-substrate via 323. As a result, the performance / yield of semiconductor device 1D can be improved.

[0180] Furthermore, due to the presence of the plurality of adjustment layers 325, the deposition rate on the sidewalls of the first through-substrate via 321 and the second through-substrate via 323 can be reduced during their formation. Therefore, the deposition rate on the sidewalls of the first through-substrate via 405 and the second through-substrate via 407, as well as the deposition rate on the bottom of the first through-substrate via 405 and the second through-substrate via 407, can become closer to each other. As a result, the first through-substrate via 321 and the second through-substrate via 407 can be filled without forming any voids, thus improving the yield of semiconductor device 1D.

[0181] It should be understood that, in the description of this disclosure, if a surface (or sidewall) is "vertical" in the presence of a vertical plane, then the deviation of the surface from the vertical plane will not exceed three times the root mean square roughness of the surface.

[0182] Please refer to Figure 24 It can be similar to, for example Figures 11 to 15 The procedure shown allows a first through-substrate via 321 to be formed in a first via opening 405, and a second through-substrate via 323 to be formed in a second via opening 407. For clarity, the barrier layer, adhesive layer, and seed layer are not shown.

[0183] Figures 25 to 27 A cross-sectional schematic diagram illustrating a portion of the fabrication process for a semiconductor element 1E according to another embodiment of the present disclosure.

[0184] Please refer to Figure 25 An intermediate semiconductor device can be similar to, for example Figures 16 to 18The process shown is used for manufacturing. An anisotropic etching process can be performed to form a first recess 411 in the first conductive layer 107 and a second recess 413 in the second conductive layer 207. In some embodiments, during the anisotropic etching process, the etching rate of the first conductive layer 107 to the insulating layer 311 may be between approximately 100:1 and approximately 1.05:1, or between approximately 20:1 and approximately 10:1. In some embodiments, during the anisotropic etching process, the etching rate of the second conductive layer 207 to the insulating layer 311 may be between approximately 100:1 and approximately 1.05:1, or between approximately 20:1 and approximately 10:1.

[0185] Please refer to Figure 25 The first recessed space 411 is formed by extending downward from the first through-hole opening 405. The depth D3 of the first recessed space 411 can be greater than half the thickness T3 of the first conductive layer 107 and less than the thickness T3 of the first conductive layer 107. The depth D3 is a vertical distance between the lower surface 301BS of the first etch stop layer 301 and the lower surface 411BS of the first recessed space 411. The horizontal distance H1 between the sidewall 311SW of the insulating layer 311 and one sidewall 411SW of the first recessed space 411 can be equal to or less than the depth D3 of the first recessed space 411.

[0186] Please refer to Figure 25 In some embodiments, the lower surface 411BS of the first recessed space 411 and each sidewall 411SW of the first recessed space 411 may be flat. In some embodiments, the lower surface 411BS of the first recessed space 411 and each sidewall 411SW of the first recessed space 411 may be curved. In some embodiments, the intersection of the lower surface 411BS of the first recessed space 411 and each sidewall 411SW of the first recessed space 411 may be curved. If the intersection is curved, corner effects can be avoided. The second recessed space 413 may have a shape and size similar to the first recessed space 411.

[0187] Please refer to Figure 26 Barrier layer 313 can be similar to, for example Figure 19 The barrier layer 313 is conformally formed in the first via opening 405, the second via opening 407, the first recessed space 411, and the second recessed space 413, as shown in the diagram. The barrier layer 313 formed in the first recessed space 411 and the second recessed space 413 can respectively increase the contact surface between the barrier layer 313 and the first conductive layer 107, and between the barrier layer 313 and the second conductive layer 207. Therefore, the contact resistance of the barrier layer 313 can be reduced. As a result, the reliability of the semiconductor device 1E can be improved.

[0188] Please refer to Figure 27 , in a similar way Figure 20 In the illustrated procedure, a first through-substrate via 321 may be formed in the first via opening 405 and the first recessed space 411. A second through-substrate via 323 may be formed in the second via opening 407 and the second recessed space 413. For clarity, the adhesive layer and the seed layer are not shown.

[0189] Due to the design of the semiconductor device disclosed herein, the greater thickness of the second etch-stop layer can compensate for the adverse effects of over-etching during the formation of the plurality of via openings. Therefore, the yield / performance of the semiconductor device 1A can be improved.

[0190] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0191] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A semiconductor element, comprising: A first semiconductor die, comprising a first conductive layer; A first etch stop layer is located on the first conductive layer; A second semiconductor die includes a second conductive layer located on the first etch stop layer; A second etch stop layer is located on the second conductive layer: A first through-substrate via is disposed along the second semiconductor grain and the first etch-stop layer, extends to the first semiconductor grain, and is located on the first conductive layer; and A second through-substrate via extends to the second semiconductor die, is disposed along the second etch-stop layer, and is located on the second conductive layer; Multiple insulating layers are located on the sidewalls of the first through-hole and the second through-hole of the substrate; Multiple adjustment layers cover the upper part of each of the multiple insulating layers; The thickness of the second etch stop layer is greater than the thickness of the first etch stop layer, and the dimensions of the first through-substrate via and the second through-substrate via are narrowed at the plurality of adjustment layers.

2. The semiconductor device of claim 1, wherein the first etch stop layer and the second etch stop layer comprise the same material.

3. The semiconductor device of claim 2, wherein the ratio of the thickness of the second etch stop layer to the thickness of the first etch stop layer is between about 1.1 and about 2.

0.

4. The semiconductor device of claim 3, wherein the width of the second through-substrate via is equal to or greater than the width of the first through-substrate via.

5. The semiconductor device of claim 4 further includes an upper conductive layer located on the first through-substrate via and the second through-substrate via.

6. The semiconductor device as claimed in claim 5, wherein, The multiple insulating layers comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, or combinations thereof.

7. The semiconductor device of claim 5, further comprising an adhesive layer located between the first conductive layer and the first through-substrate via, wherein, The adhesive layer contains titanium, tantalum, titanium tungsten, or manganese nitride.

8. The semiconductor device of claim 5, further comprising a seed layer located between the first conductive layer and the first through-hole in the substrate, wherein, The seed layer contains either copper or ruthenium.

9. The semiconductor device of claim 6 further includes a first bonding layer located on the first etch-stop layer and between the first semiconductor die and the second semiconductor die.

10. The semiconductor device of claim 9, wherein the aspect ratio of the second through-substrate via is between approximately 1:6 and approximately 1:

15.

11. The semiconductor device of claim 4, wherein the second semiconductor die includes a second dielectric layer and a second substrate, the second dielectric layer being located on the first bonding layer, the second substrate being located on the second dielectric layer, the second conductive layer and the second etch-stop layer being located in the second dielectric layer, and the second through-substrate via being disposed along the second substrate, extending to the second dielectric layer, disposed along the second etch-stop layer, and located on the second conductive layer.

12. The semiconductor device of claim 11, wherein the second dielectric layer comprises silicon oxide, and the first etch stop layer and the second etch stop layer comprise silicon nitride, silicon oxynitride, or silicon carbide nitride.

13. The semiconductor device of claim 8, wherein the seed layer has a thickness between about 10 nm and about 40 nm.

14. A method for fabricating a semiconductor device, comprising: A first semiconductor die is provided, the first semiconductor die comprising a first conductive layer; A first etch stop layer is formed on the first conductive layer; A second semiconductor die is bonded to the first etch stop layer, wherein the second semiconductor die includes a second conductive layer and a second etch stop layer, the second conductive layer is located on the first etch stop layer, the second etch stop layer is located on the second conductive layer, and the second etch stop layer has a thickness greater than the thickness of the first etch stop layer. A through-hole etching process is performed to simultaneously form a first through-hole opening and a second through-hole opening, wherein the upper part of the first through-hole opening and the upper part of the second through-hole opening have a tapered profile, the first etch stop layer is exposed through the first through-hole opening, and the second etch stop layer is exposed through the second through-hole opening. Multiple insulating layers are conformally formed in the first through-hole opening and the second through-hole opening; Multiple adjustment layers are formed to cover the upper part of each of the multiple insulating layers; A punching and etching process is performed to extend the first and second through-hole openings by removing the plurality of insulating layers formed on the first and second through-hole openings, the first etch stop layer formed on the first conductive layer, and the second etch stop layer formed on the second conductive layer; and An integrally formed first through-hole in the substrate is present in the first through-hole opening and a second through-hole in the substrate is present in the second through-hole opening; The dimensions of the first through-substrate via and the second through-substrate via are narrowed at the plurality of adjustment layers.

15. The method for fabricating a semiconductor device as claimed in claim 14, wherein the first etch stop layer and the second etch stop layer comprise the same material.

16. The method for fabricating a semiconductor device as claimed in claim 15, wherein the first etch stop layer and the second etch stop layer comprise silicon nitride, silicon oxynitride, or silicon carbide nitride.

17. The method for fabricating a semiconductor device as claimed in claim 16, wherein the via etching process uses an etchant comprising octafluoroisobutylene or hexafluorobutadiene.

18. The method for fabricating a semiconductor device as claimed in claim 17, wherein the punching and etching process uses an etchant comprising tetrafluoromethane.

19. A method for fabricating a semiconductor element, comprising: A first semiconductor die is provided, the first semiconductor die comprising a first conductive layer; A first etch stop layer is formed on the first conductive layer; A second semiconductor die is bonded to the first etch stop layer, wherein the second semiconductor die includes a second conductive layer and a second etch stop layer, the second conductive layer is located on the first etch stop layer, the second etch stop layer is located on the second conductive layer, and the second etch stop layer includes a material having an etch selectivity relative to the first etch stop layer. A through-hole etching process is performed to simultaneously form a first through-hole opening and a second through-hole opening, wherein the upper part of the first through-hole opening and the upper part of the second through-hole opening have a tapered profile, the first etch stop layer is exposed through the first through-hole opening, and the second etch stop layer is exposed through the second through-hole opening. Multiple insulating layers are conformally formed in the first through-hole opening and the second through-hole opening; Multiple adjustment layers are formed to cover the upper part of each of the multiple insulating layers; A punching and etching process is performed to extend the first and second through-hole openings by removing the plurality of insulating layers formed on the first and second through-hole openings, the first etch stop layer formed on the first conductive layer, and the second etch stop layer formed on the second conductive layer; and Simultaneously, a first through-hole is formed in the opening of the first through-hole and a second through-hole is formed in the opening of the second through-hole; The dimensions of the first through-substrate via and the second through-substrate via are narrowed at the plurality of adjustment layers.

20. The method of fabricating a semiconductor device as claimed in claim 19, wherein the via etching process has an etching ratio between the first etch stop layer and the second etch stop layer, which is between approximately 1.05:1 and approximately 25:1.

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