MCM packaging structure and manufacturing method thereof

Abstract

The present invention provides an MCM packaging structure and a manufacturing method thereof, wherein the packaging structure comprises: a first bare chip assembly, a pre-wiring substrate, a plastic packaging layer, a first conductive trace, a first conductive bump, a first dielectric layer, a second conductive trace, a second conductive bump, a second dielectric layer and passive devices. The pre-wiring substrate can transfer the wiring layer that needs to be formed on the active surface of the bare chip to the pre-wiring substrate, and the pre-wiring substrate includes complex multi-circuits, which are embedded in the packaging structure by being electrically connected to the pads on the active surface of the bare chip, thereby improving the performance of the entire MCM packaging structure and incorporating passive devices into the MCM packaging structure. The pre-wiring substrate can be tested before packaging to avoid using a known bad pre-wiring substrate. The pre-wiring substrate is a prefabricated substrate, and its manufacturing process is independent of the packaging process, thereby saving the packaging time of the entire packaging process.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to an MCM packaging structure and a manufacturing method thereof. Background Art

[0002] During the packaging process, bare chips with different functions are often packaged in a packaging structure to form a specific function, which is called a multi-chip module (MCM). It has the advantages of small size, high reliability, high performance and multi-function.

[0003] As electronic devices become smaller and lighter, chip packages with compact structures and small volumes are increasingly favored by the market.

[0004] In MCM, the internal circuit structure of the chip is often complex, and the wiring density in the wiring layer is high, which makes wiring difficult because the chip surface area is too small. In addition, due to the overly dense wiring, it is easy to cause short circuits in fine wiring, thus affecting the yield of the product. At the same time, the service life of the chip is also low; especially when it is necessary to form multiple wiring layers, the process is difficult to control due to the complexity of the process. Summary of the invention

[0005] The object of the present invention is to provide a MCM packaging structure and a manufacturing method thereof to solve the problems in the related art.

[0006] To achieve the above object, a first aspect of the present invention provides an MCM packaging structure, comprising:

[0007] A first die assembly at least comprising: a first die and a second die, wherein the first die comprises a plurality of first pads, the first pads being located on an active surface of the first die, and the second die comprises a plurality of second pads, the second pads being located on an active surface of the second die; the active surface of the second die is covered with a second protective layer, the second protective layer exposes the second pads; the active surface of the first die faces opposite to the active surface of the second die;

[0008] A pre-wiring substrate is arranged around the first bare chip assembly; a pre-wiring circuit is arranged in the pre-wiring substrate, and the pre-wiring circuit includes a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate;

[0009] A plastic encapsulation layer, covering the first bare chip assembly and the pre-wiring substrate, wherein the back side of the plastic encapsulation layer exposes the second protective layer, the second pad and the back side of the pre-wiring substrate, and the front side of the plastic encapsulation layer exposes the active surface of the first bare chip and the front side of the pre-wiring substrate;

[0010] a first conductive trace, located on the first pad, the front electrical connection point and the front side of the plastic encapsulation layer, for electrically connecting the first die to the pre-wiring circuit;

[0011] a first conductive bump connected to the first conductive trace;

[0012] a first dielectric layer, embedding the first conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer;

[0013] A second conductive trace, located on the second pad, the back electrical connection point and the back side of the plastic layer, for electrically connecting the second die to the pre-wiring circuit;

[0014] a second conductive bump connected to the second conductive trace;

[0015] a second dielectric layer, embedding the second conductive trace and the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer; and

[0016] A passive device is electrically connected to the second conductive trace through the second conductive bump.

[0017] Optionally, the first bare die assembly is a bare die stacking structure.

[0018] Optionally, the passive device is connected to the second conductive trace via the second conductive bump instead of: the passive device is connected to the first conductive trace via the first conductive bump.

[0019] Optionally, it also includes: a third dielectric layer, located on the active surface of the first bare chip, the front side of the pre-wiring substrate and the front side of the plastic layer; the third dielectric layer exposes the first pad and the front electrical connection point; the first conductive trace is located on the first pad, the front electrical connection point and the third dielectric layer.

[0020] Optionally, it further includes: a first protective layer covering the active surface of the first bare chip, the first protective layer exposing the first pad; and a front side of the plastic packaging layer exposing the first protective layer and the first pad.

[0021] Optionally, the material of the second protective layer is an organic polymer insulating material, an inorganic insulating material or a composite material; and / or the material of the first dielectric layer is an organic polymer insulating material, an inorganic insulating material or a composite material; and / or the material of the second dielectric layer is an organic polymer insulating material, an inorganic insulating material or a composite material.

[0022] Optionally, the first conductive trace includes a metal pattern layer; and / or the second conductive trace includes a metal pattern layer.

[0023] A second aspect of the present invention provides a method for manufacturing an MCM packaging structure, comprising:

[0024] A carrier and a plurality of groups of components to be packaged carried on the carrier are provided, each group of components to be packaged comprises: a pre-wiring substrate having a through opening, and a first bare chip assembly located in the through opening; a pre-wiring circuit is arranged in the pre-wiring substrate, the pre-wiring circuit comprises a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate; the first bare chip assembly comprises at least: a first bare chip and a second bare chip, the first bare chip comprises a plurality of first pads, the first pads are located on the active side of the first bare chip, the second bare chip comprises a plurality of second pads, the second pads are located on the active side of the second bare chip; the active side of the second bare chip is covered with a second protective layer; the active side of the first bare chip and the active side of the second bare chip face opposite to each other; the front side of the pre-wiring substrate and the active side of the first bare chip face the carrier;

[0025] Forming a plastic encapsulation layer on the surface of the carrier board to bury each group of the components to be encapsulated; thinning the plastic encapsulation layer until the second protective layer and the back side of the pre-wiring substrate are exposed;

[0026] Removing the carrier to expose the active surface of the first bare die, the front surface of the pre-wiring substrate and the front surface of the plastic layer; forming a first conductive trace on the first pad, the front electrical connection point and the front surface of the plastic layer to electrically connect the first bare die in the group with the pre-wiring circuit;

[0027] forming a first conductive bump on the first conductive trace and forming a first dielectric layer that buries the first conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer;

[0028] forming a second opening in the second protective layer to expose the second pad; forming a second conductive trace on the second protective layer, the second pad, the back electrical connection point and the back of the plastic layer to electrically connect the second die in the group to the pre-wiring circuit;

[0029] forming a second conductive bump on the second conductive trace and forming a second dielectric layer that buries the second conductive trace and the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer;

[0030] Disposing a passive device on the second conductive bump and the second dielectric layer, the passive device being connected to the second conductive trace in the group through the second conductive bump;

[0031] Cutting to form a plurality of MCM packaging structures, each of the MCM packaging structures includes a group of the components to be packaged.

[0032] Optionally, the second conductive trace is formed first, a second conductive bump is formed on the second conductive trace, and a second dielectric layer is formed to bury the second conductive trace and the second conductive bump, and the second conductive bump is exposed outside the second dielectric layer; then the carrier is removed to form the first conductive trace, a first conductive bump is formed on the first conductive trace, and a first dielectric layer is formed to bury the first conductive trace and the first conductive bump, and the first conductive bump is exposed outside the first dielectric layer, passive devices are arranged on the first conductive bump and the first dielectric layer, and the passive devices are connected to the first conductive trace in the group through the first conductive bump.

[0033] Optionally, the step of thinning the plastic encapsulation layer until the second protection layer and the back side of the pre-wiring substrate are exposed is performed after the step of forming the first dielectric layer and before the step of forming the second conductive trace.

[0034] Optionally, after removing the carrier, a third dielectric layer is formed on the exposed active surface of the first bare chip, the front side of the pre-wiring substrate and the front side of the plastic encapsulation layer; a plurality of third openings are formed in the third dielectric layer, the third openings exposing the first solder pad and the front side electrical connection point; and the first conductive trace is formed on the first solder pad, the front side electrical connection point and the third dielectric layer.

[0035] Optionally, in the first bare chip assembly, the active surface of the first bare chip is covered with a first protective layer; the first protective layer faces the carrier; a first opening exposing the first pad is provided in the first protective layer, or after the step of removing the carrier and before the step of forming the first conductive trace, a first opening is formed in the first protective layer to expose the first pad.

[0036] Optionally, the pre-wiring substrates of each group of the components to be packaged are connected together and are cut apart in the step of cutting to form a plurality of MCM packaging structures.

[0037] A third aspect of the present invention provides an MCM packaging structure, comprising:

[0038] A bare die, the bare die comprising a plurality of pads, wherein the pads are located on an active surface of the bare die;

[0039] A pre-wiring substrate is arranged around the bare chip; a pre-wiring circuit is arranged in the pre-wiring substrate, and the pre-wiring circuit includes a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate;

[0040] A plastic encapsulation layer, covering the bare die and the pre-wiring substrate, wherein the back side of the plastic encapsulation layer exposes the back side of the pre-wiring substrate, and the front side of the plastic encapsulation layer exposes the active surface of the bare die and the front side of the pre-wiring substrate;

[0041] Conductive traces, located on the pads, the front electrical connection points and the front side of the plastic encapsulation layer, for electrically connecting the die to the pre-wiring circuit;

[0042] a first conductive bump connected to the conductive trace;

[0043] A first dielectric layer, embedding the conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer;

[0044] A second conductive bump connected to the back electrical connection point;

[0045] a second dielectric layer, embedding the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer; and

[0046] A passive device is electrically connected to the second conductive bump.

[0047] Optionally, the passive device being electrically connected to the second conductive bump is replaced by: the passive device being electrically connected to the first conductive bump.

[0048] Optionally, the die is replaced by a second die assembly, the second die assembly comprising a plurality of dies, and active surfaces of the plurality of dies face the same direction.

[0049] A fourth aspect of the present invention provides a method for manufacturing an MCM packaging structure, comprising:

[0050] A carrier and a plurality of groups of components to be packaged carried on the carrier are provided, each group of components to be packaged comprises: a pre-wiring substrate having a through opening, and a bare chip located in the through opening; a pre-wiring circuit is arranged in the pre-wiring substrate, the pre-wiring circuit comprises a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate; the bare chip comprises a plurality of pads, and the pads are located on the active surface of the bare chip; the front side of the pre-wiring substrate and the active surface of the bare chip face the carrier;

[0051] Forming a plastic encapsulation layer on the surface of the carrier board to embed each group of the components to be encapsulated; thinning the plastic encapsulation layer until the back side of the pre-wiring substrate is exposed;

[0052] The carrier is removed to expose the active surface of the die, the front surface of the pre-wiring substrate and the front surface of the plastic layer; conductive traces are formed on the pads, the front electrical connection points and the front surface of the plastic layer to electrically connect the die in the group with the pre-wiring circuit;

[0053] forming a first conductive bump on the conductive trace and forming a first dielectric layer that buries the conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer;

[0054] forming a second conductive bump on the back electrical connection point and forming a second dielectric layer that buries the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer;

[0055] Disposing a passive device on the second conductive bump and the second dielectric layer, the passive device being electrically connected to the second conductive bump in the group;

[0056] Cutting to form a plurality of MCM packaging structures, each of the MCM packaging structures includes a group of the components to be packaged.

[0057] Optionally, the second conductive bump and the second dielectric layer that bury the second conductive bump are formed first, and the second conductive bump is exposed outside the second dielectric layer; then the carrier is removed to form the conductive trace, and the first conductive bump is formed on the conductive trace and the first dielectric layer that bury the conductive trace and the first conductive bump is formed, and the first conductive bump is exposed outside the first dielectric layer; passive devices are arranged on the first conductive bump and the first dielectric layer, and the passive devices are electrically connected to the first conductive bump.

[0058] Optionally, the die is replaced by a second die assembly, the second die assembly comprising a plurality of dies, and active surfaces of the plurality of dies face the same direction.

[0059] Compared with the prior art, the present invention has the following beneficial effects:

[0060] First, the pre-wiring substrate can transfer the wiring layer that needs to be formed on the active surface of the die to the pre-wiring substrate. The pre-wiring substrate includes complex multi-circuits. These complex multi-circuits are embedded in the packaging structure by being electrically connected to the pads on the active surface of the die, which can improve the performance of the entire MCM packaging structure. Second, the fine wiring in the rewiring layer is transferred to the pre-wiring substrate, which reduces the probability of short circuits and increases the product yield. At the same time, the number of layers of the first conductive trace and / or the second conductive trace can be reduced, and the complexity of the process can be reduced. Third, a pre-formed pre-wiring substrate is provided, and the pre-wiring substrate can be tested before packaging to avoid the use of known bad pre-wiring substrates. Fourth, the pre-wiring substrate is a prefabricated substrate, and its production process is independent of the packaging process, which can save the packaging time of the entire packaging process.

[0061] In addition, bare die components with active surfaces facing the same or opposite directions can achieve the effect of small volume and compact structure of MCM packaging structure. For bare die components with active surfaces facing opposite directions, the pre-wiring substrate can not only realize the electrical connection between the first bare die and the second bare die, but also realize wiring on both sides of the front and back of the plastic layer. Compared with wiring on only one side, the density of wiring can be improved, forming a MCM packaging structure with more complex wiring and smaller volume, and passive devices can also be incorporated into the MCM packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 is a schematic cross-sectional structural diagram of an MCM packaging structure according to a first embodiment of the present invention;

[0063] Figure 2 yes Figure 1 A flow chart of a method for making an MCM packaging structure;

[0064] Figures 3 to 9 yes Figure 2 Schematic diagram of the intermediate structure corresponding to the process in;

[0065] Fig.10 is a schematic cross-sectional structural diagram of an MCM packaging structure according to a second embodiment of the present invention;

[0066] Fig.11 is a schematic cross-sectional structural diagram of an MCM packaging structure according to a third embodiment of the present invention;

[0067] Fig.12 yes Fig.11 A flow chart of a method for making an MCM packaging structure;

[0068] Fig.13 and Fig.14 yes Fig.12 Schematic diagram of the intermediate structure corresponding to the process in;

[0069] Fig.15FIG. 4 is a schematic cross-sectional view of an MCM packaging structure according to a fourth embodiment of the present invention.

[0070] To facilitate understanding of the present invention, all reference numerals appearing in the present invention are listed below:

[0071] MCM packaging structure 1, 6, 7, 8 first bare chip assembly 10

[0072] First bare chip 11 First protective layer 110

[0073] First pad 111 Back side 11b of first die

[0074] The active surface 11a of the first die and the second die 12

[0075] Second protection layer 120 Second pad 121

[0076] Back side 12b of the second die Active side 12a of the second die

[0077] Pre-wiring substrate 13 Pre-wiring line 130

[0078] Front electrical connection point 131 Back electrical connection point 132

[0079] Front surface 13a of pre-wiring substrate Back surface 13b of pre-wiring substrate

[0080] Plastic sealing layer 14 Front side 14a of plastic sealing layer

[0081] Back side of plastic encapsulation layer 14b First conductive trace 15

[0082] First conductive bump 16 First dielectric layer 17

[0083] Second conductive trace 18 Second conductive bump 19

[0084] Second dielectric layer 20 Passive device 21

[0085] Through opening 133 First opening 110a

[0086] Second opening 120a Metal pattern blocks 15a, 18a

[0087] Carrier 2 Components to be packaged 3

[0088] First support plate 4 Second support plate 5

[0089] The third opening 22a and the third dielectric layer 22 DETAILED DESCRIPTION

[0090] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0091] Figure 1 FIG. 1 is a schematic cross-sectional view of the MCM packaging structure according to the first embodiment of the present invention.

[0092] Reference Figure 1 As shown, the MCM packaging structure 1 includes:

[0093] The first die assembly 10 at least comprises: a first die 11 and a second die 12, the first die 11 comprises a plurality of first pads 111, the first pads 111 are located on the active surface 11a of the first die 11, the second die 12 comprises a plurality of second pads 121, the second pads 121 are located on the active surface 12a of the second die 12; the active surface 12a of the second die 12 is covered with a second protective layer 120, the second protective layer 120 exposes the second pads 121; the active surface 11a of the first die 11 and the active surface of the second die 12 face opposite to each other;

[0094] A pre-wiring substrate 13 is arranged around the first bare chip assembly 10; a pre-wiring circuit 130 is arranged in the pre-wiring substrate 13, and the pre-wiring circuit 130 includes a front electrical connection point 131 and a back electrical connection point 132, the front electrical connection point 131 is exposed on the front side 13a of the pre-wiring substrate 13, and the back electrical connection point 132 is exposed on the back side 13b of the pre-wiring substrate 13;

[0095] The plastic encapsulation layer 14 covers the first bare chip assembly 10 and the pre-wiring substrate 13, the back side 14b of the plastic encapsulation layer 14 exposes the second protection layer 120, the second pad 121 and the back side 13b of the pre-wiring substrate 13, and the front side 14a of the plastic encapsulation layer 14 exposes the active surface 11a of the first bare chip 11 and the front side 13a of the pre-wiring substrate 13;

[0096] The first conductive trace 15 is located on the first pad 111, the front electrical connection point 131 and the front surface 14a of the plastic encapsulation layer 14, and is used to electrically connect the first bare chip 11 and the pre-wiring circuit 130;

[0097] A first conductive bump 16 connected to the first conductive trace 15;

[0098] A first dielectric layer 17 burying the first conductive trace 15 and the first conductive bump 16 , wherein the first conductive bump 16 is exposed outside the first dielectric layer 17 ;

[0099] The second conductive trace 18 is located on the second pad 121, the back electrical connection point 132 and the back surface 14b of the plastic layer 14, and is used to electrically connect the second bare die 12 and the pre-wiring circuit 130;

[0100] A second conductive bump 19 connected to the second conductive trace 18;

[0101] A second dielectric layer 20 embeds the second conductive trace 18 and the second conductive bump 19 , and the second conductive bump 19 is exposed outside the second dielectric layer 20 ; and

[0102] The passive device 21 is connected to the second conductive trace 18 via the second conductive bump 19 .

[0103] The first die 11 and the second die 12 may be die that need to be electrically interconnected, and their respective functions are not limited. In some embodiments, the first die 11 and the second die 12 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE) or a corresponding control chip.

[0104] Reference Figure 1 As shown, the first die 11 includes an active surface 11a and a back surface 11b opposite to each other. The first pad 111 is exposed on the active surface 11a. The first die 11 may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The first pad 111 is connected to the electrical interconnection structure for inputting / outputting electrical signals of each device.

[0105] It should be noted that, in the present invention, “ / ” means “or”.

[0106] The second die 12 includes an active surface 12a and a back surface 12b opposite to each other. A second pad 121 is exposed to the active surface 12a. The second die 12 may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The second pad 121 is connected to the electrical interconnection structure for inputting / outputting electrical signals of each device.

[0107] Continue to refer to Figure 1 As shown, in this embodiment, the first die assembly 10 is a die stacking structure, that is, the first die 11 and the second die 12 are arranged back to back. The first die 11 and the second die 12 are arranged back to back means that the back side 11b of the first die 11 and the back side 12b of the second die 12 are attached together.

[0108] In other embodiments, the first die assembly 10 may include one or more first die 11, and may also include one or more second die 12. The first die 11 and the second die 12 may be arranged in a staggered manner, or even arranged side by side, that is, the front side 14a of the plastic encapsulation layer 14 also exposes the back side 12b of the second die 12.

[0109] In this embodiment, the area of ​​the first die 11 is larger than the area of ​​the second die 12. In other embodiments, the area of ​​the second die 12 may also be larger than the area of ​​the first die 11.

[0110] In this embodiment, the active surface 11 a of the first die 11 is provided with a first protective layer 110 . In some embodiments, the active surface 11 a of the first die 11 may also omit the first protective layer 110 .

[0111] The first protective layer 110 and / or the second protective layer 120 are insulating materials, which may be organic high molecular polymer insulating materials, inorganic insulating materials or composite materials. Examples of organic high molecular polymer insulating materials include polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer films or other organic materials with similar insulating properties. Examples of inorganic insulating materials include at least one of silicon dioxide and silicon nitride. The composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as a SiO2 / resin polymer composite material.

[0112] The pre-wiring substrate 13 includes a pre-wiring circuit 130 and an insulating material layer filled between the pre-wiring circuits 130. Compared with the solution of making a re-wiring layer on the plastic package of the first bare chip 11 and the second bare chip 12, the advantages of using the pre-wiring substrate 13 in this solution are: first, the fine wiring in the re-wiring layer is transferred to the pre-wiring substrate 13, which reduces the probability of short circuit and increases the product yield. At the same time, the number of layers of the first conductive trace 15 and / or the second conductive trace 18 can be reduced, and the complexity of the process can be reduced. Second, a pre-formed pre-wiring substrate 13 is provided, and the pre-wiring substrate 13 can be tested before packaging to avoid the use of a known bad pre-wiring substrate 13. Third, the pre-wiring substrate 13 is a prefabricated substrate, and its manufacturing process is independent of the packaging process, which can save the packaging time of the entire packaging process.

[0113] In addition, the wiring layer that needs to be formed on the active surfaces 11a and 12a of the die is transferred to the pre-wiring substrate 13. The pre-wiring substrate 13 includes complex multi-circuits. These complex multi-circuits are embedded in the packaging structure 1 by being electrically connected to the pads 111 and 121 on the active surfaces 11a and 12a of the die, thereby improving the performance of the entire packaging structure 1.

[0114] The pre-wiring substrate 13 may be a whole piece disposed around the first bare chip assembly 10 , or may be a plurality of pieces.

[0115] The pre-wiring substrate 13 may include a front side 13a and a back side 13b opposite to each other. In this embodiment, the front side 13a of the pre-wiring substrate 13 is flush with the first protective layer 110, and the back side 13b of the pre-wiring substrate 13 is flush with the second protective layer 120. There may be multiple front electrical connection points 131 exposed on the front side 13a of the pre-wiring substrate, and there may also be multiple back electrical connection points 132 exposed on the back side 13b of the pre-wiring substrate.

[0116] The material of the plastic encapsulation layer 14 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc. The material of the plastic encapsulation layer 14 can also be various polymers or composite materials of resins and polymers.

[0117] The plastic encapsulation layer 14 includes a front side 14a and a back side 14b opposite to each other. In the present embodiment, the front side 14a of the plastic encapsulation layer 14 exposes the first protective layer 110, the first pad 111 and the front side 13a of the pre-wiring substrate 13, and the back side 14b of the plastic encapsulation layer 14 exposes the second protective layer 120, the second pad 121 and the back side 13b of the pre-wiring substrate 13.

[0118] Figure 1 In the illustrated embodiment, the first conductive trace 15 includes a plurality of metal pattern blocks 15a, which have a layer. A portion of the metal pattern blocks 15a selectively electrically connects the front electrical connection point 131 with the first pad 111 to achieve electrical connection between the pre-wiring substrate 13 and the first bare chip 11; a portion of the metal pattern blocks 15a selectively electrically connects the front electrical connection point 131 to lead out the front electrical connection points 131 through the first conductive bump 16. In addition, a portion of the metal pattern blocks 15a selectively electrically connects a plurality of electrically connected front electrical connection points 131 to achieve circuit layout or electrical conduction of the front electrical connection points 131; a portion of the metal pattern blocks 15a selectively electrically connects a plurality of first pads 111 to achieve circuit layout or electrical conduction of the first pads 111.

[0119] The layout of the first conductive traces 15 may be determined according to a predetermined circuit layout.

[0120] In some embodiments, the first conductive trace 15 may further include two or more metal pattern layers.

[0121] Reference Figure 1 As shown, in this embodiment, the first conductive bump 16 on the first conductive trace 15 serves as an external connection terminal of the MCM packaging structure 1 .

[0122] In some embodiments, an anti-oxidation layer may be formed on the first conductive bump 16 .

[0123] The anti-oxidation layer may include: b1) a tin layer, or b2) a nickel layer and a gold layer stacked from bottom to top, or b3) a nickel layer, a palladium layer and a gold layer stacked from bottom to top. The material of the first conductive bump 16 may be copper, and the anti-oxidation layer may prevent copper oxidation, thereby preventing the electrical connection performance from being deteriorated due to copper oxidation.

[0124] Figure 1 In the illustrated embodiment, the second conductive trace 18 includes a plurality of metal pattern blocks 18a, which have a layer. A portion of the metal pattern blocks 18a selectively electrically connects the back electrical connection point 132 with the second pad 121 to achieve electrical connection between the pre-wiring substrate 13 and the second die 12. In addition, a portion of the metal pattern blocks 18a selectively electrically connects a plurality of back electrical connection points 132 to achieve circuit layout or electrical conduction of the back electrical connection points 132; a portion of the metal pattern blocks 18a selectively electrically connects a plurality of second pads 121 to achieve circuit layout or electrical conduction of the second pads 121.

[0125] The layout of the second conductive traces 18 may be determined according to a predetermined circuit layout.

[0126] In some embodiments, the second conductive trace 18 may further include two or more metal pattern layers.

[0127] The material of the second conductive bump 19 can be copper.

[0128] The materials of the first dielectric layer 17 and the second dielectric layer 20 can be organic high molecular polymer insulating materials, inorganic insulating materials or composite materials. The organic high molecular polymer insulating materials are, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film or other organic materials with similar insulating properties. The inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride. The composite material is an inorganic-organic composite material, which can be an inorganic-organic polymer composite material, such as SiO2 / resin polymer composite material. Compared with inorganic insulating materials, the tensile stress of organic high molecular polymer insulating materials and composite materials is smaller, which can prevent the surface of the MCM packaging structure 1 from warping.

[0129] The passive device 21 may include resistors, inductors and capacitors, and their common feature is that they can work when there is a signal without adding power to the circuit. The passive device 21 includes an electrical connection point, which is connected to the second conductive bump 19 to achieve the electrical signal input / output of the passive device 21.

[0130] This embodiment does not limit the number and types of the first bare chip components 10 and the passive components 21 .

[0131] Reference Figure 1 As shown, the MCM packaging structure 1 in this embodiment realizes external circuit connection through the first conductive bump 16 .

[0132] In the MCM packaging structure 1, on the one hand, the first bare chip assembly 10 with the active surface facing away from each other realizes the effect of small volume and compact structure of the MCM packaging structure 1. On the other hand, the pre-wiring substrate 13 not only realizes the electrical connection between the first bare chip 11 and the second bare chip 12, but also realizes the wiring on the front side 14a and the back side 14b of the plastic packaging layer 14. Compared with the wiring on only one side, the density of the wiring can be improved, forming a MCM packaging structure 1 with more complex wiring and smaller volume. On the other hand, through the wiring on the back side 14b of the plastic packaging layer, the passive device 21 can be incorporated into the MCM packaging structure 1.

[0133] One embodiment of the present invention provides Figure 1 A method for manufacturing the MCM packaging structure 1. Figure 2 It is a flowchart of the production method. Figures 3 to 9 yes Figure 2 Schematic diagram of the intermediate structure corresponding to the process in .

[0134] First, refer to Figure 2 Step S1 in Figure 3 and Figure 4 As shown, a carrier board 2 and a plurality of groups of components to be packaged 3 carried on the carrier board 2 are provided, each group of components to be packaged 3 includes: a pre-wiring substrate 13 having a through opening 133, and a first bare chip assembly 10 located in the through opening 133; a pre-wiring circuit 130 is provided in the pre-wiring substrate 13, and the pre-wiring circuit 130 includes a front electrical connection point 131 and a back electrical connection point 132, the front electrical connection point 131 is exposed on the front side 13a of the pre-wiring substrate 13, and the back electrical connection point 132 is exposed on the back side 13b of the pre-wiring substrate 13; the first bare chip assembly 10 includes at least : A first die 11 and a second die 12, the first die 11 includes a plurality of first pads 111, the first pads 111 are located on the active surface 11a of the first die 11, the second die 12 includes a plurality of second pads 121, the second pads 121 are located on the active surface 12a of the second die 12; the active surface 12a of the second die 12 is covered with a second protective layer 120; the active surface 11a of the first die 11 and the active surface 12a of the second die 12 face opposite to each other; the front surface 13a of the pre-wiring substrate 13 and the active surface 11a of the first die 11 face the carrier 2. Wherein, Figure 3 is a top view of a carrier board and multiple groups of components to be packaged; Figure 4 It is along Figure 3 Sectional view along line AA.

[0135] The first die 11 and the second die 12 may be die that need to be electrically interconnected, and their respective functions are not limited. In some embodiments, the first die 11 and the second die 12 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE) or a corresponding control chip.

[0136] Reference Figure 4 As shown, the first die 11 includes an active surface 11a and a back surface 11b opposite to each other. The first die 11 may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. A first pad 111 exposed to the active surface 11a of the first die 11 is connected to the electrical interconnection structure for inputting / outputting electrical signals of each device.

[0137] The second die 12 includes an active surface 12a and a back surface 12b opposite to each other. A second pad 121 is exposed on the active surface 12a. The second die 12 may also include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The second pad 121 exposed to the active surface 12a of the second die 12 is connected to the electrical interconnection structure for inputting / outputting electrical signals of each device.

[0138] Continue to refer to Figure 4 As shown, in this embodiment, the first die assembly 10 is a die stacking structure, that is, the first die 11 and the second die 12 are arranged back to back. In other embodiments, the first die assembly 10 may include a first or multiple first die 11, and may also include one or more second die 12. The first die 11 and the second die 12 may be arranged in a staggered manner, or even arranged side by side, that is, the front side 14a of the plastic encapsulation layer 14 also exposes the back side 12b of the second die 12.

[0139] In this embodiment, the area of ​​the first die 11 is larger than the area of ​​the second die 12. In other embodiments, the area of ​​the second die 12 may also be larger than the area of ​​the first die 11.

[0140] The second protection layer 120 covers the second pad 121 to protect the second pad 121 when the plastic layer 14 is thinned.

[0141] In this embodiment, the active surface 11a of the first die 11 is also provided with a first protective layer 110 to buffer stress on the first pad 111 when the plastic layer 14 is thinned. In some embodiments, the first protective layer 110 may also be omitted from the active surface 11a of the first die 11.

[0142] The first die 11 and the second die 12 are both formed by dividing the wafer. Taking the first die 11 as an example, the wafer includes an active surface of the wafer and a back surface of the wafer, and the active surface of the wafer exposes the first pad 111 and an insulating layer (not shown) protecting the first pad 111. After the wafer is cut, the first die 11 is formed. Accordingly, the first die 11 includes an active surface 11a and a back surface 11b, and the first pad 111 and the insulating layer electrically insulating the adjacent first pad 111 are exposed on the active surface 11a of the die.

[0143] A first protective layer 110 is applied on the active surface 11a of the first bare chip 11. The application process of the first protective layer 110 can be: applying the first protective layer 110 on the active surface of the wafer before the wafer is cut into the first bare chip 11, and cutting the wafer with the first protective layer 110 to form the first bare chip 11 with the first protective layer 110. It can also be: after the wafer is cut into the first bare chip 11, applying the first protective layer 110 on the active surface 11a of the first bare chip 11.

[0144] The first protective layer 110 and / or the second protective layer 120 are insulating materials, which may be organic high molecular polymer insulating materials, inorganic insulating materials or composite materials. Organic high molecular polymer insulating materials are, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film or other organic materials with similar insulating properties. The composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO2 / resin polymer composite material.

[0145] The organic high molecular polymer insulating material can be a) pressed onto the insulating layer between the first pad 111 and the adjacent first pad 111 / on the insulating layer between the second pad 121 and the adjacent second pad 121 by a lamination process, or b) first coated or printed on the insulating layer between the first pad 111 and the adjacent first pad 111 / on the insulating layer between the second pad 121 and the adjacent second pad 121 and then cured, or c) cured on the insulating layer between the first pad 111 and the adjacent first pad 111 / on the insulating layer between the second pad 121 and the adjacent second pad 121 by an injection molding process.

[0146] When the material of the first protective layer 110 and / or the second protective layer 120 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the first pad 111 and the insulating layer between adjacent first pads 111 / on the second pad 121 and the insulating layer between adjacent second pads 121 through a deposition process.

[0147] The first protective layer 110 and / or the second protective layer 120 may include one or more layers.

[0148] The wafer may be thinned from the back side before dicing to reduce the thickness of the first die 11 and / or the second die 12 .

[0149] The pre-wiring substrate 13 includes pre-wiring lines 130 and insulating material filled between the pre-wiring lines 130 .

[0150] The pre-wiring substrate 13 may be a whole piece disposed around the first bare chip assembly 10 , or may be a plurality of pieces.

[0151] In this embodiment, refer to Figure 3 As shown, the pre-wiring substrates 13 of each group of components to be packaged 3 are separated. In some embodiments, the pre-wiring substrates 13 of each group of components to be packaged 3 may also be connected together.

[0152] The carrier plate 2 is a hard plate, which may include a plastic plate, a glass plate, a ceramic plate or a metal plate.

[0153] In some embodiments, the thickness of the pre-wiring substrate 13 is less than the thickness of the die stacking structure. When multiple groups of components to be packaged 3 are arranged on the surface of the carrier 2, a solution may include:

[0154] a) The front surfaces 13a of the plurality of pre-wiring substrates 13 face the carrier 2, and the plurality of pre-wiring substrates 13 are first arranged on the carrier 2; specifically, a whole adhesive layer may be coated on the surface of the carrier 2, and the plurality of pre-wiring substrates 13 are placed on the adhesive layer;

[0155] b) the first protective layer 110 on the plurality of first bare chips 11 faces another carrier board, and the plurality of first bare chips 11 are arranged on the other carrier board, the second protective layer 120 on the plurality of second bare chips 12 faces another carrier board, and the plurality of second bare chips 12 are arranged on the another carrier board. Specifically, a whole-surface adhesive layer can be coated on the surfaces of the two carrier boards; an adhesive layer is provided on the back sides 11b of the plurality of first bare chips 11 and / or the back sides 12b of the plurality of second bare chips 12, the two carrier boards are aligned, and the back sides 11b of the first bare chips 11 and the back sides 12b of the second bare chips 12 are bonded together to form a bare chip stacking structure; and the other carrier board is removed;

[0156] c) The die stacking structure faces the through opening 133 of the pre-wiring substrate 13, the further carrier is aligned with the carrier 2, and the die stacking structure is fixed to the carrier 2 at the bottom of the through opening 133; the further carrier is removed.

[0157] There is no particular order for step a) and step b) and they can be performed simultaneously.

[0158] The adhesive layer on each carrier surface can be made of an easily peelable material so that the corresponding carrier can be peeled off, for example, a thermal separation material that can lose its viscosity by heating or a UV separation material that can lose its viscosity by ultraviolet irradiation.

[0159] In another scheme, step a) is performed first; then in step b), the first protective layer 110 on the multiple first bare chips 11 is fixed on the carrier 2 toward the through opening 133 of the pre-wiring substrate 13; then, the carrier on which the multiple second bare chips 12 are arranged is aligned with the carrier 2, and the back side 11b of the first bare chip 11 and the back side 12b of the second bare chip 12 are bonded together to form a bare chip stacking structure; the carrier carrying the multiple second bare chips 12 is removed.

[0160] In another scheme, the first protective layer 110 on the multiple first bare chips 11 faces the carrier 2, and the multiple first bare chips 11 are first arranged on the carrier 2; then, the front sides 13a of the multiple pre-wiring substrates 13 face the carrier 2, and the through opening 133 of each pre-wiring substrate 13 is aligned with a first bare chip 11, and the multiple pre-wiring substrates 13 are arranged on the carrier 2; then, the carrier on which the multiple second bare chips 12 are arranged is aligned with the carrier 2, and the back sides 11b of the first bare chips 11 and the back sides 12b of the second bare chips 12 are bonded together to form a bare chip stacking structure; and the carrier carrying the multiple second bare chips 12 is removed.

[0161] In some embodiments, the thickness of the pre-wiring substrate 13 is greater than the thickness of the die stacking structure. When multiple groups of components 3 to be packaged are arranged on the surface of the carrier 2, a solution may include: first performing the above steps a) and b), and then in step c), the through opening 133 of the pre-wiring substrate 13 faces the die stacking structure, the further carrier is aligned with the carrier 2, and the pre-wiring substrate 13 is fixed to the further carrier; and the carrier 2 is removed.

[0162] A group of components to be packaged 3 is located in an area on the surface of the carrier 2, which is convenient for subsequent cutting. Multiple groups of components to be packaged 3 are fixed on the surface of the carrier 2 to simultaneously manufacture multiple MCM packaging structures 1, which is conducive to mass production and cost reduction.

[0163] Next, refer to Figure 2 Step S2 in Figure 5 As shown, a plastic sealing layer 14 is formed on the surface of the carrier board 2 to embed each group of components 3 to be packaged; Figure 6 As shown, the plastic encapsulation layer 14 is thinned until the second protection layer 120 and the back surface 13 b of the pre-wiring substrate 13 are exposed.

[0164] The material of the plastic encapsulation layer 14 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol. The material of the plastic encapsulation layer 14 can also be various polymers or composite materials of resin and polymer. Correspondingly, the encapsulation can be performed by filling liquid plastic encapsulation material between each first bare chip assembly 10 and each pre-wiring substrate 13, and then curing at high temperature through a plastic encapsulation mold. In some embodiments, the plastic encapsulation layer 14 can also be formed by a plastic material forming method such as hot pressing molding and transfer molding.

[0165] The molding layer 14 may include a front surface 14 a and a back surface 14 b opposite to each other.

[0166] Reference Figure 6 As shown, the plastic packaging layer 14 is thinned from the back side 14b, and mechanical grinding, such as grinding with a grinding wheel, can be used.

[0167] Specifically, when the plastic encapsulation layer 14 is thinned, when the thickness of the pre-wiring substrate 13 is less than the thickness of the first bare chip assembly 10, when the back side 13b of the pre-wiring substrate 13 is exposed, part of the height of the second protective layer 120 has been removed; when the thickness of the pre-wiring substrate 13 is greater than the thickness of the first bare chip assembly 10, when the second protective layer 120 is exposed, part of the height of the back side 13b of the pre-wiring substrate 13 has been removed.

[0168] During the process of forming and grinding the plastic encapsulation layer 14 , the second protective layer 120 can prevent the second pad 121 , the second die 12 , and the electrical interconnection structure and devices in the first die 11 from being damaged; the first protective layer 110 can perform stress buffering on the first pad 111 .

[0169] This step forms a plastic package body for each group of components 3 to be packaged.

[0170] Next, refer to Figure 2 Step S3 in Figure 7 As shown, the carrier 2 is removed to expose the active surface 11a of the first bare chip 11, the front surface 13a of the pre-wiring substrate 13 and the front surface 14a of the plastic layer 14; a first conductive trace 15 is formed on the first pad 111, the front electrical connection point 131 and the front surface 14a of the plastic layer 14 to electrically connect the first bare chip 11 in the group with the pre-wiring circuit 130.

[0171] Reference Figure 7 As shown, after the carrier board 2 is removed, a first support board 4 may be disposed on the second protection layer 120 , the back surface 13 b of the pre-wiring substrate 13 , and the back surface 14 b of the plastic packaging layer 14 .

[0172] The carrier board 2 may be removed by conventional removal methods such as laser stripping and UV irradiation.

[0173] The first support plate 4 may play a supporting role in the subsequent steps of forming the first conductive trace 15 , and / or forming the first conductive bump 16 , and / or forming the first dielectric layer 17 .

[0174] The first support plate 4 is a hard plate, which may include a glass plate, a ceramic plate, a metal plate, etc.

[0175] In this embodiment, since the first protective layer 110 is disposed on the active surface 11 a of the exposed first die 11 , the first protective layer 110 is exposed after the carrier 2 is removed.

[0176] In this embodiment, the first conductive trace 15 includes a layer. Forming the first conductive trace 15 includes the following steps S31 to S38.

[0177] Step S31 : forming a photoresist layer on the first protection layer 110 of each first bare chip 12 , the front surface 13 a of each pre-wiring substrate 13 , and the front surface 14 a of the molding layer 14 .

[0178] In this step S31, in an optional solution, the photoresist layer formed may be a photosensitive film. The photosensitive film may be torn off from the tape and applied to the first protective layer 110 of each first bare chip 12, the front surface 13a of each pre-wiring substrate 13, and the front surface 14a of the plastic layer 14. In other optional solutions, the photoresist layer may also be formed by first applying a liquid photoresist and then heating and curing it.

[0179] Step S32: exposing and developing the photoresist layer to form a patterned photoresist layer.

[0180] In this step S32, the photoresist layer is patterned. In other optional solutions, other easily removable sacrificial materials can also be used to replace the photoresist layer.

[0181] Step S33: Using the patterned photoresist layer as a mask, dry-etch or wet-etch the first protection layer 110 to form a plurality of first openings 110a to expose a portion of each first pad 111. One first opening 110a may expose a portion of one first pad 111. In other embodiments, one first opening 110a may also expose portions of two or more first pads 111.

[0182] If the material of the first protective layer 110 is a laser-reactive material, such as epoxy resin, etc., the first opening 110a can be formed by modifying it by laser irradiation. If the material of the first protective layer 110 is a photosensitive material, such as polyimide, etc., the first opening 110a can be formed by first exposing and then developing. If the material of the first protective layer 110 is a material that can be dry-etched or wet-etched, such as silicon dioxide, silicon nitride, etc., the first opening 110a can be formed by dry-etching or wet-etching.

[0183] Step S34: removing the remaining photoresist layer by ashing.

[0184] Step S35 : forming a photoresist layer on the first protection layer 110 of each first bare chip 11 , the first pad 111 exposed by the first protection layer 110 , the front surface 13 a of each pre-wiring substrate 13 , and the front surface 14 a of the molding layer 14 .

[0185] The method for forming the photoresist layer may refer to the method for forming the photoresist layer in step S31 .

[0186] Step S36: exposing and developing the photoresist layer, and retaining the photoresist layer in a first predetermined area, the first predetermined area being complementary to the area where the metal pattern block 15a of the first conductive trace 15 to be formed is located.

[0187] Step S37 : filling a metal layer in a complementary region of the first predetermined region to form a metal pattern block 15 a of the first conductive trace 15 .

[0188] A portion of the metal pattern blocks 15a selectively electrically connects the front electrical connection points 131 and the first pads 111 to achieve electrical connection between the pre-wiring substrate 13 and the first bare chip 11; a portion of the metal pattern blocks 15a selectively electrically connects the front electrical connection points 131 to lead out the front electrical connection points 131 through the first conductive bumps 16. In addition, a portion of the metal pattern blocks 15a selectively electrically connects a plurality of electrically connected front electrical connection points 131 to achieve circuit layout or electrical conduction of the front electrical connection points 131; a portion of the metal pattern blocks 15a selectively electrically connects a plurality of first pads 111 to achieve circuit layout or electrical conduction of the first pads 111.

[0189] This step S37 can be completed by using an electroplating process. The process of electroplating copper or aluminum is relatively mature.

[0190] Specifically, before forming the photoresist layer in step S35, a seed layer (Seed Layer) can be formed by physical vapor deposition or chemical vapor deposition on the first protective layer 110 of each first bare chip 11, the first pad 111 exposed by the first protective layer 110, the front surface 13a of each pre-wiring substrate 13, and the front surface 14a of the plastic layer 14. The seed layer can be used as a power supply layer for electroplating copper or aluminum.

[0191] Electroplating may include electrolytic plating or electrodeless plating. Electrolytic plating is to use the workpiece to be plated as a cathode to electrolyze the electrolyte, thereby forming a layer of metal on the workpiece to be plated. Electroless plating is a method of reducing and precipitating metal ions in the solution to form a metal layer on the workpiece to be plated. In some embodiments, the metal pattern block 18a may also be formed by a method of first sputtering and then etching.

[0192] Step S38: removing the remaining photoresist layer in the first predetermined area by ashing.

[0193] After ashing, the seed layer in the first predetermined area is removed by dry etching or wet etching.

[0194] The metal pattern block 15 a of the first conductive trace 15 may be polished, for example, by chemical mechanical polishing to achieve a smooth upper surface.

[0195] It should be noted that the metal pattern blocks 15a of the first conductive traces 15 in step S3 are arranged according to design requirements, and the distribution of the first conductive traces 15 in different groups of components 3 to be packaged may be the same or different.

[0196] Furthermore, in some embodiments, the first conductive trace 15 may further include two or more metal pattern layers.

[0197] In some embodiments, in the plurality of groups of components 3 to be packaged in step S1 , specifically in the first bare chip assembly 10 , the first protective layer 110 may also have a first opening 110 a exposing the first pad 111 .

[0198] Next, refer to Figure 2 Step S4 in Figure 7 As shown, a first conductive bump 16 is formed on the first conductive trace 15 , and a first dielectric layer 17 is formed to embed the first conductive trace 15 and the first conductive bump 16 . The first conductive bump 16 is exposed outside the first dielectric layer 17 .

[0199] This step S4 may include steps S41-S45.

[0200] Step S41 : forming a photoresist layer on the metal pattern block 15 a , the insulating material layer exposed on the front surface 13 a of the pre-wiring substrate, and the front surface 14 a of the plastic packaging layer 14 .

[0201] In this step S41, in an optional solution, the photoresist layer formed may be a photosensitive film. The photosensitive film may be torn off from the tape and applied to the metal pattern block 15a, the insulating material layer exposed on the front side 13a of the pre-wiring substrate, and the front side 14a of the plastic layer 14. In other optional solutions, the photoresist layer may also be formed by first applying a liquid photoresist and then heating and curing it.

[0202] Step S42: exposing and developing the photoresist layer to retain the photoresist in the second predetermined area. The second predetermined area is complementary to the area where the first conductive bump 16 is to be formed.

[0203] In this step S42, the photoresist layer is patterned. In other optional solutions, other easily removable sacrificial materials can also be used to replace the photoresist layer.

[0204] Step S43 : filling a metal layer in a complementary region of the second predetermined region to form a first conductive bump 16 .

[0205] This step S43 can be completed by electroplating. The process of electroplating copper or aluminum is relatively mature. Before electroplating copper or aluminum, a seed layer (Seed Layer) can be firstly physically vapor deposited or chemically vapor deposited as a power supply layer.

[0206] Step S44: removing the remaining photoresist layer in the second predetermined area by ashing.

[0207] The first conductive bump 16 can be smoothed on its upper surface by a polishing process, such as chemical mechanical polishing.

[0208] Step S45: Refer to Figure 8 As shown, a first dielectric layer 17 is formed on the first conductive bump 16, the metal pattern block 15a, the insulating material layer exposed on the front side 13a of the pre-wiring substrate, and the front side 14a of the plastic layer 14; the first dielectric layer 17 is thinned until the first conductive bump 16 is exposed.

[0209] The first dielectric layer 17 is an insulating material, which may be an organic high molecular polymer insulating material, or an inorganic insulating material or a composite material. The organic high molecular polymer insulating material may be, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), an organic polymer film or other organic materials with similar insulating properties. The composite material may be an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as a SiO2 / resin polymer composite material.

[0210] The organic high molecular polymer insulating material can be pressed onto the first conductive trace 15 and the first protective layer 110 not covering the first conductive trace 15, the front surface 13a of the pre-wiring substrate 13, and the front surface 14a of the plastic encapsulation layer 14 by a) a lamination process, or b) first coated on the first conductive trace 15 and the first protective layer 110 not covering the first conductive trace 15, the front surface 13a of the pre-wiring substrate 13, and the front surface 14a of the plastic encapsulation layer 14 and then cured, or c) cured on the first conductive trace 15 and the first protective layer 110 not covering the first conductive trace 15, the front surface 13a of the pre-wiring substrate 13, and the front surface 14a of the plastic encapsulation layer 14 by an injection molding process.

[0211] When the material of the first dielectric layer 17 is an inorganic insulating material such as silicon dioxide or silicon nitride, it can be formed on the first conductive trace 15 and the front surface 14 a of the plastic packaging layer 14 through a deposition process.

[0212] Compared with inorganic insulating materials, organic high molecular polymer insulating materials have smaller tensile stress, which can prevent the plastic package from warping when the first dielectric layer 17 is formed over a large area.

[0213] In the step of forming the first dielectric layer 17 , in order to prevent the plastic encapsulation layer 14 from being scratched by the process, the first dielectric layer 17 may also be formed on the front surface 14 a of the plastic encapsulation layer 14 between adjacent groups of components 3 to be packaged.

[0214] When the first dielectric layer 17 covers the first conductive bump 16 , the first dielectric layer 17 is polished until the first conductive bump 16 is exposed.

[0215] The first dielectric layer 17 may include one or more layers.

[0216] After the first conductive bump 16 is manufactured, in the optional solution a), refer to Figure 8 As shown, the first conductive bump 16 serves as an external connection terminal of the MCM package structure 1 .

[0217] b) In an optional solution, after the first conductive bump 16 is exposed, an anti-oxidation layer is further formed on the first conductive bump 16 .

[0218] The anti-oxidation layer may include: b1) a tin layer, or b2) a nickel layer and a gold layer stacked from bottom to top, or b3) a nickel layer, a palladium layer and a gold layer stacked from bottom to top. The anti-oxidation layer may be formed by an electroplating process. The material of the first conductive bump 16 may be copper, and the anti-oxidation layer may prevent copper oxidation, thereby preventing the electrical connection performance from being deteriorated due to copper oxidation.

[0219] After forming the first conductive bump 16, refer to Figure 8 As shown, the first support plate 4 is removed.

[0220] The first support plate 4 can be removed by conventional removal methods such as laser stripping and UV irradiation.

[0221] Afterwards, refer to Figure 2 Step S5 in Figure 8 As shown, a second opening 120a is formed in the second protective layer 120 to expose the second pad 121; a second conductive trace 18 is formed on the second protective layer 120, the second pad 121, the back electrical connection point 132 and the back side 14b of the plastic layer 14 to electrically connect the second bare chip 12 in the group with the pre-wiring circuit 130.

[0222] Reference Figure 8 As shown, after removing the first support plate 4 , a second support plate 5 may be disposed on the first dielectric layer 17 and the first conductive bumps 16 .

[0223] The second support plate 5 may play a supporting role in the subsequent steps of forming the second conductive trace 18 , and / or forming the second conductive bump 19 , and / or forming the second dielectric layer 20 , and / or connecting the passive device 21 .

[0224] The second support plate 5 is a hard plate, which may include a glass plate, a ceramic plate, a metal plate, etc.

[0225] If the material of the second protective layer 120 is a laser-reactive material, such as epoxy resin, etc., the second opening 120a can be formed by modifying it by laser irradiation. If the material of the second protective layer 120 is a photosensitive material, such as polyimide, etc., the second opening 120a can be formed by first exposing and then developing. If the material of the second protective layer 120 is a dry-etchable or wet-etchable material, such as silicon dioxide, silicon nitride, etc., the second opening 120a can be formed by dry-etching or wet-etching.

[0226] The method for forming the metal pattern block 18a in the second conductive trace 18 may refer to the method for forming the metal pattern block 15a in the first conductive trace 15. The layout of the second conductive trace 18 may be determined according to a predetermined layout.

[0227] In this embodiment, the second conductive trace 18 includes one layer.

[0228] The positions of a part of the metal pattern blocks 18a enable electrical connection of the back electrical connection points 132 and the second pads 121 to achieve electrical connection between the pre-wiring substrate 13 and the second bare die 12. The positions of a part of the metal pattern blocks 18a enable electrical connection of multiple electrically connected back electrical connection points 132 to achieve circuit layout or electrical conduction of these back electrical connection points 132. In addition, the positions of a part of the metal pattern blocks 18a can also enable electrical connection of multiple second pads 121 to achieve circuit layout or electrical conduction of these second pads 121.

[0229] In other embodiments, the second conductive trace 18 may include two or more metal pattern layers.

[0230] In some embodiments, thinning the plastic packaging layer 14 may also be performed after step S4 is completed and before step S5 is started.

[0231] Next, refer to Figure 2 Step S6 in Figure 8 As shown, a second conductive bump 19 is formed on the second conductive trace 18 , and a second dielectric layer 20 is formed to embed the second conductive trace 18 and the second conductive bump 19 . The second conductive bump 19 is exposed outside the second dielectric layer 20 .

[0232] The method for forming the second conductive bump 19 may refer to the method for forming the first conductive bump 16 in step S4 .

[0233] In the step of forming the second dielectric layer 20 , in order to prevent the plastic encapsulation layer 14 from being scratched during the process, the second dielectric layer 20 may also be formed on the back side 14 b of the plastic encapsulation layer 14 .

[0234] The material and forming method of the second dielectric layer 20 may refer to the material and forming method of the first dielectric layer 17 .

[0235] Next, refer to Figure 2 Step S7 in Figure 8 As shown, a passive device 21 is disposed on the second conductive bump 19 and the second dielectric layer 20 , and the passive device 21 is connected to the second conductive trace 18 in the group through the second conductive bump 19 .

[0236] The passive device 21 may include resistors, inductors and capacitors, and their common feature is that they can work when there is a signal without adding power to the circuit. The passive device 21 includes an electrical connection point, which is connected to the second conductive bump 19 to achieve the electrical signal input / output of the passive device 21.

[0237] After the passive device 21 is fixed, refer to Fig. 9 As shown, the second support plate 5 is removed.

[0238] The second support plate 5 can be removed by conventional removal methods such as laser stripping and UV irradiation.

[0239] Afterwards, refer to Figure 2 Step S8 in Fig. 9 and Figure 1 As shown, a plurality of MCM packaging structures 1 are formed by cutting, and each MCM packaging structure 1 includes a group of components 3 to be packaged.

[0240] For the embodiment in which the pre-wiring substrates 13 of each group of components 3 to be packaged are connected together, the pre-wiring substrates 13 are cut apart during the cutting process in step S8 .

[0241] In the MCM packaging structure 1 formed through the above steps, on the one hand, the first bare chip assembly 10 with the active surface facing away from each other realizes the effect of small volume and compact structure of the MCM packaging structure 1. On the other hand, the pre-wiring substrate 13 not only realizes the electrical connection between the first bare chip 11 and the second bare chip 12, but also realizes the wiring on the front side 14a and the back side 14b of the plastic packaging layer 14. Compared with the wiring on only one side, the density of the wiring can be improved, forming a MCM packaging structure 1 with more complex wiring and smaller volume. In addition, through the wiring on the back side 14b of the plastic packaging layer, the passive device 21 can be incorporated into the MCM packaging structure 1.

[0242] The advantages of using the pre-wiring substrate 13 are: first, the fine wiring in the rewiring layer is transferred to the pre-wiring substrate 13, which reduces the probability of short circuits and increases the product yield. At the same time, the number of layers of the first conductive traces 15 and / or the second conductive traces 18 can be reduced, reducing the complexity of the process. Second, a pre-formed pre-wiring substrate 13 is provided, and the pre-wiring substrate 13 can be tested before packaging to avoid using a known bad pre-wiring substrate 13. Third, the pre-wiring substrate 13 is a prefabricated substrate, and its manufacturing process is independent of the packaging process, which can save the packaging time of the entire packaging process.

[0243] In addition, the wiring layer that needs to be formed on the active surfaces 11a and 12a of the die is transferred to the pre-wiring substrate 13. The pre-wiring substrate 13 includes complex multi-circuits. These complex multi-circuits are embedded in the packaging structure 1 by being electrically connected to the pads 111 and 121 on the active surfaces 11a and 12a of the die, thereby improving the performance of the entire packaging structure 1.

[0244] Fig.10 FIG. 2 is a schematic cross-sectional view of the MCM packaging structure of the second embodiment of the present invention. Fig.10 As shown, the MCM packaging structure 6 in this embodiment is substantially the same as the MCM packaging structure 1 in the aforementioned embodiment, with the only difference being that: the first protective layer 110 is omitted, the active surface 11a of the first bare chip 11, the front surface 13a of the pre-wiring substrate 13 and the front surface 14a of the plastic layer 14 are provided with a third dielectric layer 22; the third dielectric layer 22 has a third opening 22a exposing the first pad 111 and the front electrical connection point 131; and the first conductive trace 15 is located on the first pad 111, the front electrical connection point 131 and the third dielectric layer 22.

[0245] Correspondingly, the manufacturing method is different from the aforementioned embodiment in that: in step S3, after removing the carrier 2 to expose the active surface 11a of the first bare chip 11, the front surface 13a of the pre-wiring substrate 13, and the front surface 14a of the plastic encapsulation layer 14: a third dielectric layer 22 is formed on the exposed active surface 11a of the first bare chip 11, the front surface 13a of the pre-wiring substrate 13, and the front surface 14a of the plastic encapsulation layer 14; a plurality of third openings 22a are formed in the third dielectric layer 22, and the third openings 22a expose the first solder pad 111 and the front electrical connection point 131; and then a first conductive trace 15 is formed on the first solder pad 111, the front electrical connection point 131, and the third dielectric layer 22.

[0246] The material of the third dielectric layer 22 refers to the materials of the first dielectric layer 17 and the second dielectric layer 20 .

[0247] If the material of the third dielectric layer 22 is a laser-reactive material, such as epoxy resin, etc., the third opening 22a can be formed by modifying it by laser irradiation. If the material of the third dielectric layer 22 is a photosensitive material, such as polyimide, etc., the third opening 22a can be formed by first exposing and then developing. If the material of the third dielectric layer 22 is a dry-etchable or wet-etchable material, such as silicon dioxide, silicon nitride, etc., the third opening 22a can be formed by dry-etching or wet-etching.

[0248] Fig.11 FIG. 1 is a schematic cross-sectional view of the MCM packaging structure of the third embodiment of the present invention. Fig.11 As shown, the MCM packaging structure 7 in this embodiment is substantially the same as the MCM packaging structures 1 and 6 in the above-mentioned embodiments, with the only difference being that the passive device 21 is connected to the first conductive trace 15 via the first conductive bump 16 .

[0249] In addition, the MCM packaging structure 7 in this embodiment realizes external circuit connection through the second conductive bump 19 .

[0250] Fig.12 yes Fig.11 A flow chart of a method for making an MCM packaging structure; Fig.13 and Fig.14 yes Fig.12 Schematic diagram of the intermediate structure corresponding to the process in .

[0251] Accordingly, refer to Fig.12 As shown, the difference between this embodiment and the above two embodiments in terms of the manufacturing method is:

[0252] Step S3': Refer to Fig.13As shown, a second opening 120a is formed in the second protection layer 120 to expose the second pad 121; a second conductive trace 18 is formed on the second protection layer 120, the second pad 121, the back electrical connection point 132 and the back side 14b of the plastic layer 14 to electrically connect the second die 12 in the group with the pre-wiring circuit 130;

[0253] Step S4': Continue to refer to Fig.13 As shown, a second conductive bump 19 is formed on the second conductive trace 18 and a second dielectric layer 20 is formed to bury the second conductive trace 18 and the second conductive bump 19, and the second conductive bump 19 is exposed outside the second dielectric layer 20;

[0254] Step S5': Refer to Fig.14 As shown, the carrier 2 is removed to expose the active surface 11a of the first bare chip 11, the front surface 13a of the pre-wiring substrate 13, and the front surface 14a of the plastic layer 14; a first conductive trace 15 is formed on the first pad 111, the front electrical connection point 131, and the front surface 14a of the plastic layer 14 to electrically connect the first bare chip 11 in the group with the pre-wiring circuit 130;

[0255] Step S6': Continue to refer to Fig.14 As shown, a first conductive bump 16 is formed on the first conductive trace 15 and a first dielectric layer 17 is formed to bury the first conductive trace 15 and the first conductive bump 16, and the first conductive bump 16 is exposed outside the first dielectric layer 17;

[0256] Step S7': Still referring to Fig.14 As shown, a passive device 21 is disposed on the first conductive bump 16 and the first dielectric layer 17 , and the passive device 21 is connected to the first conductive trace 15 in the group through the first conductive bump 16 .

[0257] Step S3' may refer to step S5 of the aforementioned embodiment, step S4' may refer to steps S4 and S6 of the aforementioned embodiment, step S5' may refer to step S3 of the aforementioned embodiment, step S6' may refer to steps S6 and S4 of the aforementioned embodiment, and step S7' may refer to step S7 of the aforementioned embodiment.

[0258] Specifically, in this step 5', refer to Fig.14 As shown, after removing the carrier 2 , a first support plate 4 may be disposed on the second conductive bumps 19 and the second dielectric layer 20 ; after step S7 ′ is completed, the first support plate 4 is removed.

[0259] In other words, the second conductive trace 18 is first formed, the second conductive bump 19 is formed on the second conductive trace 18, and the second dielectric layer 20 is formed to embed the second conductive trace 18 and the second conductive bump 19, and the second conductive bump 19 is exposed outside the second dielectric layer 20; then the carrier 2 is removed to form the first conductive trace 15, the first conductive bump 16 is formed on the first conductive trace 15, and the first dielectric layer 17 is formed to embed the first conductive trace 15 and the first conductive bump 16, and the first conductive bump 16 is exposed outside the first dielectric layer 17, and the passive device 21 is set on the first conductive bump 16 and the first dielectric layer 17, and the passive device 21 is connected to the first conductive trace 15 in the group through the first conductive bump 16.

[0260] Fig.15 FIG. 4 is a schematic cross-sectional view of the MCM packaging structure according to the fourth embodiment of the present invention. Fig.15 As shown, the MCM packaging structure 8 in this embodiment is substantially the same as the MCM packaging structures 1, 6, 7 and the manufacturing methods thereof in the aforementioned embodiments, except that the first bare chip assembly 10 is replaced by a bare chip, for example, by the first bare chip 11. Accordingly, the second conductive bump 19 is connected to the back electrical connection point 132. The passive device 21 is electrically connected to the back electrical connection point 132 of the pre-wiring substrate 13 through the second conductive bump 19.

[0261] In this embodiment, the first conductive bump 16 serves as an external connection terminal of the MCM package structure 8 .

[0262] Accordingly, the manufacturing method is different from the previous embodiment in that the step of forming the second conductive trace 18 is omitted.

[0263] In some embodiments, the passive device 21 may also be electrically connected to the first conductive bump 16; in other words, the second conductive bump 19 serves as the external connection terminal of the MCM package structure 8. Accordingly, in the manufacturing method, the second conductive bump 19 and the second dielectric layer 20 for embedding the second conductive bump 19 are first formed, and the second conductive bump 19 is exposed outside the second dielectric layer 20; then the carrier 2 is removed to form the first conductive trace 15, the first conductive bump 16 is formed on the first conductive trace 15, and the first dielectric layer 17 for embedding the first conductive trace 15 and the first conductive bump 16 is formed, and the first conductive bump 16 is exposed outside the first dielectric layer 17, and the passive device 21 is arranged on the first conductive bump 16 and the first dielectric layer 17, and the passive device 21 is electrically connected to the first conductive bump 16.

[0264] In other embodiments, the first die assembly 10 may also be replaced by the second die 12, or by the second die assembly, the second die assembly including a plurality of first die 11, or a plurality of second die 12. In other words, in the second die assembly, the active surfaces of the dies face the same direction.

[0265] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An MCM packaging structure, characterized in that: include: A first die assembly at least comprising: a first die and a second die, wherein the first die comprises a plurality of first pads, the first pads being located on an active surface of the first die, and the second die comprises a plurality of second pads, the second pads being located on an active surface of the second die; the active surface of the second die is covered with a second protective layer, the second protective layer exposes the second pads; the active surface of the first die faces opposite to the active surface of the second die; A pre-wiring substrate is arranged around the first bare chip assembly; a pre-wiring circuit is arranged in the pre-wiring substrate, and the pre-wiring circuit includes a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate; A plastic encapsulation layer, covering the first bare chip assembly and the pre-wiring substrate, wherein the back side of the plastic encapsulation layer exposes the second protective layer, the second pad and the back side of the pre-wiring substrate, and the front side of the plastic encapsulation layer exposes the active surface of the first bare chip and the front side of the pre-wiring substrate; a first conductive trace, located on the first pad, the front electrical connection point and the front side of the plastic encapsulation layer, for electrically connecting the first die to the pre-wiring circuit; a first conductive bump connected to the first conductive trace; a first dielectric layer, embedding the first conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer; A second conductive trace, located on the second pad, the back electrical connection point and the back side of the plastic layer, for electrically connecting the second die to the pre-wiring circuit; a second conductive bump connected to the second conductive trace; a second dielectric layer, embedding the second conductive trace and the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer; and A passive device is electrically connected to the second conductive trace through the second conductive bump.

2. The MCM packaging structure according to claim 1, characterized in that: The first bare die assembly is a bare die stacking structure.

3. The MCM packaging structure according to claim 1, characterized in that: The passive device is connected to the second conductive trace via the second conductive bump instead of being connected to the first conductive trace via the first conductive bump.

4. The MCM packaging structure according to claim 1, characterized in that: Also includes: A third dielectric layer is located on the active surface of the first bare chip, the front surface of the pre-wiring substrate, and the front surface of the plastic packaging layer; The third dielectric layer exposes the first pad and the front electrical connection point; the first conductive trace is located on the first pad, the front electrical connection point and the third dielectric layer.

5. The MCM packaging structure according to claim 1, characterized in that: Also includes: A first protective layer covers the active surface of the first bare chip, and the first protective layer exposes the first pad; the front side of the plastic packaging layer exposes the first protective layer and the first pad.

6. The MCM packaging structure according to claim 1, characterized in that: The material of the second protective layer is an organic polymer insulating material, an inorganic insulating material or a composite material; and / or the material of the first dielectric layer is an organic polymer insulating material, an inorganic insulating material or a composite material; and / or the material of the second dielectric layer is an organic polymer insulating material, an inorganic insulating material or a composite material.

7. A method for manufacturing an MCM packaging structure, characterized in that: include: A carrier and a plurality of groups of components to be packaged carried on the carrier are provided, each group of components to be packaged comprises: a pre-wiring substrate having a through opening, and a first bare chip assembly located in the through opening; a pre-wiring circuit is arranged in the pre-wiring substrate, the pre-wiring circuit comprises a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate; the first bare chip assembly comprises at least: a first bare chip and a second bare chip, the first bare chip comprises a plurality of first pads, the first pads are located on the active side of the first bare chip, the second bare chip comprises a plurality of second pads, the second pads are located on the active side of the second bare chip; the active side of the second bare chip is covered with a second protective layer; the active side of the first bare chip and the active side of the second bare chip face opposite to each other; the front side of the pre-wiring substrate and the active side of the first bare chip face the carrier; Forming a plastic encapsulation layer on the surface of the carrier board to bury each group of the components to be encapsulated; thinning the plastic encapsulation layer until the second protective layer and the back side of the pre-wiring substrate are exposed; Removing the carrier to expose the active surface of the first bare die, the front surface of the pre-wiring substrate and the front surface of the plastic layer; forming a first conductive trace on the first pad, the front electrical connection point and the front surface of the plastic layer to electrically connect the first bare die in the group with the pre-wiring circuit; forming a first conductive bump on the first conductive trace and forming a first dielectric layer that buries the first conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer; forming a second opening in the second protective layer to expose the second pad; forming a second conductive trace on the second protective layer, the second pad, the back electrical connection point and the back of the plastic layer to electrically connect the second die in the group to the pre-wiring circuit; forming a second conductive bump on the second conductive trace and forming a second dielectric layer that buries the second conductive trace and the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer; Disposing a passive device on the second conductive bump and the second dielectric layer, the passive device being electrically connected to the second conductive trace in the group through the second conductive bump; Cutting to form a plurality of MCM packaging structures, each of the MCM packaging structures includes a group of the components to be packaged.

8. The method for manufacturing the MCM packaging structure according to claim 7, characterized in that: Firstly, forming the second conductive trace, forming a second conductive bump on the second conductive trace, and forming a second dielectric layer that buries the second conductive trace and the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer; The carrier is then removed to form the first conductive trace, a first conductive bump is formed on the first conductive trace, and a first dielectric layer is formed to bury the first conductive trace and the first conductive bump, the first conductive bump is exposed outside the first dielectric layer, passive devices are arranged on the first conductive bump and the first dielectric layer, and the passive devices are connected to the first conductive trace in the group through the first conductive bump.

9. The method for manufacturing the MCM packaging structure according to claim 7, characterized in that: The step of thinning the plastic packaging layer until the second protection layer and the back side of the pre-wiring substrate are exposed is performed after the step of forming the first dielectric layer and before the step of forming the second conductive trace.

10. The method for manufacturing the MCM packaging structure according to claim 7, characterized in that: After removing the carrier, a third dielectric layer is formed on the exposed active surface of the first bare chip, the front side of the pre-wiring substrate and the front side of the plastic layer; a plurality of third openings are formed in the third dielectric layer, and the third openings expose the first solder pad and the front side electrical connection point; and the first conductive trace is formed on the first solder pad, the front side electrical connection point and the third dielectric layer.

11. The method for manufacturing the MCM packaging structure according to claim 7, characterized in that: In the first bare chip assembly, the active surface of the first bare chip is covered with a first protective layer; the first protective layer faces the carrier; the first protective layer is provided with a first opening exposing the first pad, or after the step of removing the carrier and before the step of forming the first conductive trace, a first opening is formed in the first protective layer to expose the first pad.

12. The method for manufacturing the MCM packaging structure according to any one of claims 7 to 11, characterized in that: The pre-wiring substrates of each group of the components to be packaged are connected together and are cut apart in the step of cutting to form a plurality of MCM packaging structures.

13. An MCM packaging structure, characterized in that: include: A bare die, the bare die comprising a plurality of pads, wherein the pads are located on an active surface of the bare die; A pre-wiring substrate is arranged around the bare chip; a pre-wiring circuit is arranged in the pre-wiring substrate, and the pre-wiring circuit includes a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate; A plastic encapsulation layer, covering the bare die and the pre-wiring substrate, wherein the back side of the plastic encapsulation layer exposes the back side of the pre-wiring substrate, and the front side of the plastic encapsulation layer exposes the active surface of the bare die and the front side of the pre-wiring substrate; Conductive traces, located on the pads, the front electrical connection points and the front side of the plastic encapsulation layer, for electrically connecting the die to the pre-wiring circuit; a first conductive bump connected to the conductive trace; A first dielectric layer, embedding the conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer; a second conductive bump connected to the back electrical connection point; a second dielectric layer, embedding the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer; as well as A passive device is electrically connected to the second conductive bump.

14. The MCM packaging structure according to claim 13, characterized in that: The passive device being electrically connected to the second conductive bump is replaced by: the passive device being electrically connected to the first conductive bump.

15. The MCM packaging structure according to claim 13 or 14, characterized in that: The die is replaced by a second die assembly, the second die assembly comprising a plurality of dies, the active surfaces of the plurality of dies facing the same direction.

16. A method for manufacturing an MCM packaging structure, characterized in that: include: A carrier and a plurality of groups of components to be packaged carried on the carrier are provided, each group of components to be packaged comprises: a pre-wiring substrate having a through opening, and a bare chip located in the through opening; a pre-wiring circuit is arranged in the pre-wiring substrate, the pre-wiring circuit comprises a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate; the bare chip comprises a plurality of pads, and the pads are located on the active surface of the bare chip; the front side of the pre-wiring substrate and the active surface of the bare chip face the carrier; Forming a plastic encapsulation layer on the surface of the carrier board to embed each group of the components to be encapsulated; thinning the plastic encapsulation layer until the back side of the pre-wiring substrate is exposed; The carrier is removed to expose the active surface of the die, the front surface of the pre-wiring substrate and the front surface of the plastic layer; conductive traces are formed on the pads, the front electrical connection points and the front surface of the plastic layer to electrically connect the die in the group with the pre-wiring circuit; forming a first conductive bump on the conductive trace and forming a first dielectric layer that buries the conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer; forming a second conductive bump on the back electrical connection point and forming a second dielectric layer that buries the second conductive bump, wherein the second conductive bump is exposed outside the second dielectric layer; Disposing a passive device on the second conductive bump and the second dielectric layer, the passive device being electrically connected to the second conductive bump in the group; Cutting to form a plurality of MCM packaging structures, each of the MCM packaging structures includes a group of the components to be packaged.

17. The method for manufacturing the MCM packaging structure according to claim 16, characterized in that: First, the second conductive bump and the second dielectric layer that bury the second conductive bump are formed, and the second conductive bump is exposed outside the second dielectric layer; then the carrier is removed to form the conductive trace, and the first conductive bump is formed on the conductive trace and the first dielectric layer that bury the conductive trace and the first conductive bump is formed, and the first conductive bump is exposed outside the first dielectric layer, and passive devices are arranged on the first conductive bump and the first dielectric layer, and the passive devices are electrically connected to the first conductive bump.

18. The method for manufacturing the MCM packaging structure according to claim 16 or 17, characterized in that: The die is replaced by a second die assembly, the second die assembly comprising a plurality of dies, the active surfaces of the plurality of dies facing the same direction.

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