Optical Detection Device and System

Abstract

An optical detection device includes: a first pixel circuit including a first avalanche photodiode; a second pixel circuit including a second avalanche photodiode; a first delay circuit including an input coupled to the cathode of the second avalanche photodiode; a first circuit including: a first input coupled to the cathode of the second avalanche photodiode; and a second input coupled to the output of the first delay circuit. The optical detection device includes a control circuit that is coupled to the output of the first circuit and is configured to control the potential of the anode of the first avalanche photodiode based on the output of the first circuit. The control circuit is configured to control the potential of the anode of the second avalanche photodiode based on the output of the first circuit.

Description

Technical Field

[0001] The present technology relates to an optical detection device. Specifically, the present technology relates to an optical detection device and system for measuring the distance to an object. Background Art

[0002] In the past, regarding electronic devices having a distance measurement function, a distance measurement method called time of flight (ToF) has been known. ToF is a method of measuring the distance by causing an electronic device to emit irradiation light toward an object and calculating the round-trip time between the emission of the irradiation light and the return of the reflected irradiation light, which is the irradiation light that has been emitted and reflected, to the electronic device. In many cases, when detecting the reflected light corresponding to the irradiation light, a single photon avalanche diode (SPAD) is used as a photoelectric conversion element. However, when using an SPAD, sometimes the excess bias varies depending on the temperature. The excess bias is a value obtained by subtracting the breakdown voltage from the voltage between the anode and the cathode. Therefore, there is a possibility that the excess bias becomes too small and the sensitivity of the photodiode decreases, and a possibility that the reverse excess bias becomes too large and the dark current noise increases. Therefore, a solid-state image sensor has been provided that monitors the cathode potential of the SPAD when a photocurrent flows, and reduces the anode potential of the SPAD when the cathode potential becomes high.

[0003] Citation List

[0004] Patent Literature

[0005] PTL 1: Japanese Patent Application Laid-Open No. 2019-75394. Summary of the Invention

[0006] Technical Problem

[0007] The above related technology controls the anode potential to suppress the change in the excess bias caused by temperature changes. However, the monitoring voltage (cathode voltage) for controlling the anode potential follows the change in the excess bias caused by temperature, and the monitoring voltage also changes according to the decrease or increase in the incident light amount. Although the above solid-state image sensor enables suppression of the change in the excess bias caused by temperature changes, this solid-state image sensor has a problem of a change in the excess bias caused by the change in the monitoring voltage according to the decrease or increase in the incident light amount.

[0008] It is desired to suppress the change in the excess bias according to the decrease or increase in the incident light amount by using a solid-state image sensor that controls one of the anode potential and the cathode potential of a photoelectric conversion element based on the other of the anode potential and the cathode potential.

[0009] Solution to the Problem

[0010] According to a first embodiment of the present technology, a solid-state image sensor is provided, including: a photoelectric conversion element including an anode and a cathode, one of the anode and the cathode being connected to a predetermined node; a potential supply element configured to supply a first potential to the predetermined node; a time detection circuit configured to detect a time when a predetermined period of time has elapsed since the potential of the predetermined node starts to increase or decrease from the first potential; a sampling and holding circuit configured to capture the potential of the predetermined node based on an output from the time detection circuit and hold the potential as a second potential; and a control section configured to control the potential of the other of the anode and the cathode based on the second potential. This makes it possible to suppress changes in overbias.

[0011] Furthermore, according to the first embodiment, the time detection circuit may include an inverter configured to invert a signal of the potential of the predetermined node and output the inverted signal. This makes it possible to detect time based on the inverted signal.

[0012] Furthermore, according to the first embodiment, the time detection circuit may further include a pulse signal generation circuit configured to generate a pulse signal based on a signal obtained by delaying the inverted signal by a predetermined delay time, and the sampling and holding circuit may capture the potential of the predetermined node during a period of the pulse width of the pulse signal. This makes it possible to sample the cathode potential by using the pulse signal.

[0013] Furthermore, according to the first embodiment, the time detection circuit may further include a delay circuit configured to delay the inverted signal by a predetermined delay time and output the delayed signal, and the sampling and holding circuit captures the potential of the predetermined node when the delayed signal is one of two different values and holds the captured potential when the delayed signal is the other of the two values. This makes it possible to sample the cathode potential by using the delayed signal.

[0014] Furthermore, according to the first embodiment, the photoelectric conversion element, the time detection circuit, and the sampling and holding circuit may be mounted in pixels, the mounting being performed with respect to a plurality of pixels, and the control section includes: an inter-pixel average acquisition section configured to calculate an average value of the respective second potentials of the plurality of pixels as an inter-pixel average value; a time average acquisition section configured to calculate a time average value of the inter-pixel average value; and a potential control section configured to control the potential of the other of the anode and the cathode in such a manner that the potential becomes lower as the time average value becomes higher. This makes it possible to suppress adverse effects caused by changes in the second potential.

[0015] In addition, according to the first embodiment, the time-average acquisition section may include an analog filter configured to generate a time average. This enables the acquisition of the time average by using an analog circuit.

[0016] In addition, according to the first embodiment, the time-average acquisition section may include a digital filter configured to generate a time average. This enables a reduction in the occupied area.

[0017] In addition, according to the first embodiment, the potential control section may include an amplifier configured to compare the time average with a predetermined power supply potential and output the comparison result to the other of the anode and the cathode. This enables the control of the potential by using an analog circuit.

[0018] In addition, according to the first embodiment, the potential control section may include a power semiconductor configured to control the potential of the other of the anode and the cathode such that the potential becomes lower as the time average becomes higher. This enables a reduction in the occupied area.

[0019] In addition, according to the first embodiment, the inter-pixel average acquisition section may include a capacitor and a plurality of resistors connected in parallel between the plurality of pixels and the capacitor. This enables the acquisition of the inter-pixel average by using an analog circuit.

[0020] In addition, according to the first embodiment, the inter-pixel average acquisition section may include: an analog-to-digital conversion section configured to convert a second potential into a digital signal; and an average filter configured to calculate an average value of the digital signal as the inter-pixel average. This enables a reduction in the occupied area.

[0021] In addition, according to the first embodiment, the analog-to-digital conversion section may include a plurality of analog-to-digital converters configured to convert second potentials of different pixels into digital signals. This enables the conversion of a plurality of second potentials into digital signals simultaneously.

[0022] In addition, according to the first embodiment, the analog-to-digital conversion section may include: a selector configured to select any one of the respective second potentials of the plurality of pixels; and an analog-to-digital converter configured to convert the selected second potential into a digital signal. This enables a reduction in the number of analog-to-digital converters.

[0023] In addition, according to the first embodiment, the solid-state image sensor may further include an output-side buffer inserted between the sample-and-hold circuit and the control section. This enables the output of the second potential via the output-side buffer.

[0024] In addition, according to the first embodiment, the output-side buffer can generate a differential signal based on the second potential and output the generated differential signal. This enables a more accurate output value to be obtained.

[0025] In addition, according to the first embodiment, the solid-state image sensor may further include an input-side buffer inserted between a predetermined node and the sample-and-hold circuit. This allows the monitoring pixels and the imaging pixels to have the same breakdown voltage VBD.

[0026] In addition, according to the first embodiment, the input-side buffer can generate a differential signal based on the second potential and output the generated differential signal. This enables a more accurate output value to be obtained.

[0027] In addition, according to the first embodiment, the photoelectric conversion element and the potential supply element can be mounted in each of the imaging pixel circuit and the monitoring pixel circuit surrounding the imaging pixel circuit, and the time detection circuit and the sample-and-hold circuit can be mounted in the monitoring pixel circuit. This allows the potential of the anode or the cathode to be controlled based on the potential held by the monitoring pixel circuit.

[0028] In addition, according to the first embodiment, the cathode can be connected to a predetermined node, and the control section can control the potential of the anode. This allows the anode potential to be controlled in response to the cathode potential.

[0029] In addition, according to the first embodiment, the anode can be connected to a predetermined node, and the control section can control the potential of the cathode. This allows the cathode potential to be controlled in response to the anode potential.

[0030] In addition, according to the second embodiment of the present technology, a ranging system is provided, including: a light-emitting portion configured to provide irradiation light; and a solid-state image sensor including: a photoelectric conversion element including an anode and a cathode, one of the anode and the cathode being connected to a predetermined node; a potential supply element configured to supply a first potential to the predetermined node; a time detection circuit configured to detect the time when a predetermined period of time has elapsed since the potential of the predetermined node starts to increase or decrease from the first potential; a sample-and-hold circuit configured to capture the potential of the predetermined node based on an output from the time detection circuit and hold the potential as a second potential; a control section configured to control the potential of the other of the anode and the cathode based on the second potential; and a ranging section configured to measure a distance based on the round-trip time between the light emission time of the irradiation light and the light reception time of the reflected light corresponding to the irradiation light. This enables suppression of changes in excessive bias and improvement of ranging accuracy.

[0031] According to an embodiment of the present technology, an optical detection device includes: a first pixel circuit including a first avalanche photodiode; a second pixel circuit including a second avalanche photodiode; a first delay circuit including an input coupled to the cathode of the second avalanche photodiode; a first circuit including a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to the output of the first delay circuit. The optical detection device includes a control circuit coupled to the output of the first circuit and configured to control the potential of the anode of the first avalanche photodiode based on the output of the first circuit. The control circuit is configured to control the potential of the anode of the second avalanche photodiode based on the output of the first circuit. The optical detection device further includes: a third pixel circuit including a third avalanche photodiode; a second delay circuit including an input coupled to the potential of the cathode of the third avalanche photodiode; and a second circuit including a third input coupled to the cathode of the third avalanche photodiode and a fourth input coupled to the output of the second delay circuit. The control circuit includes an averaging circuit coupled to the outputs of the first circuit and the second circuit and configured to average the outputs of the first circuit and the second circuit to output an inter-pixel average signal. The control circuit includes a time averaging circuit having an input coupled to the output of the averaging circuit and configured to output a time-averaged signal based on the inter-pixel average signal. The control circuit includes a potential controller coupled to the anode of the first avalanche photodiode. The potential controller is configured to control the potential of the anode of the first avalanche photodiode to be lower when the time-averaged signal rises, and the potential controller is configured to control the potential of the anode of the first avalanche photodiode to be higher when the time-averaged signal falls. The control circuit includes an analog-to-digital converter configured to convert the time-averaged signal into a digital signal, and the potential controller includes a power electronic device configured to control the potential of the anode of the first avalanche photodiode based on the digital signal. The averaging circuit includes a capacitor, a first resistor coupled between the capacitor and the first delay circuit, and a second resistor coupled between the capacitor and the second delay circuit. The first circuit includes a holding circuit including a switch and a capacitor. The first circuit includes a first buffer circuit and a second buffer circuit. The first buffer circuit is coupled between the cathode of the second avalanche photodiode and the holding circuit, and the holding circuit is coupled between the first buffer circuit and the second buffer circuit.The first buffer circuit is configured to buffer the potential of the cathode of the second avalanche photodiode to output a first pair of differential signals including a first positive signal and a first negative signal, the holding circuit is configured to output the first positive signal according to a first delay signal, and the second buffer circuit is configured to buffer the first negative signal and the first positive signal to output a second pair of differential signals including a second positive signal and a second negative signal. The control circuit includes an averaging circuit, and the averaging circuit includes: an analog-to-digital converter (ADC), the analog-to-digital converter including a first input configured to receive the second positive signal, a second input configured to receive the second negative signal, and an output configured to output a digital signal based on the second positive signal and the second negative signal. The control circuit includes a first capacitor coupled to the first input of the ADC; and a second capacitor coupled to the second input of the ADC. The first buffer circuit includes a first current source and a first transistor coupled to the first current source, and a second current source and a second transistor coupled to the second current source. The first transistor is coupled to a node configured to receive the potential of the cathode of the second avalanche photodiode, and is configured to output the first positive signal according to the current from the first current source, and the second transistor is coupled to a node configured to receive a ground signal, and is configured to output the first negative signal according to the current from the second current source. The second buffer circuit includes a third current source and a third transistor coupled to the third current source, and a fourth current source and a fourth transistor coupled to the fourth current source. The third transistor is configured to receive the first positive signal and output the second positive signal according to the current from the third current source, and the fourth transistor is configured to receive the first negative signal and output the second negative signal according to the current from the fourth current source. According to an embodiment of the present technology, an optical detection device includes: a first pixel circuit including a first avalanche photodiode; a second pixel circuit including a second avalanche photodiode; a first delay circuit configured to generate a first delay signal based on a first potential of the cathode of the second avalanche photodiode; and a first circuit configured to sample a second potential of the cathode of the second avalanche photodiode and output the sampled second potential based on the first delay signal. The optical detection device includes a control circuit configured to control the potential of the anode of the first avalanche photodiode based on the sampled second potential output by the first circuit.According to an embodiment of the present technology, a system includes: a light source; and a light detection device including: a first pixel circuit including a first avalanche photodiode; a second pixel circuit including: a second avalanche photodiode; a first delay circuit including an input coupled to the cathode of the second avalanche photodiode; a first circuit including a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to the output of the first delay circuit. The system includes a control circuit coupled to the output of the first circuit and configured to control the potential of the anode of the first avalanche photodiode based on the output of the first circuit. According to an embodiment of the present technology, a light detection device includes: a first pixel circuit including a first avalanche photodiode; a second pixel circuit including: a second avalanche photodiode; a first delay circuit including an input coupled to the anode of the second avalanche photodiode; a first circuit including a first input coupled to the anode of the second avalanche photodiode and a second input coupled to the output of the first delay circuit; and a control circuit coupled to the output of the first circuit and configured to control the potential of the cathode of the first avalanche photodiode based on the output of the first circuit.

[0032] Advantages of the Invention

[0033] The monitoring pixel detects the time when a predetermined period of time has elapsed since the cathode potential decreased, and captures and holds the cathode potential at that time. This enables the potential to be maintained without depending on the light amount. When the control section controls the anode potential in response to the held potential, changes in the bias voltage caused by a decrease or increase in the light amount can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a block diagram showing a configuration example of a distance measurement module according to a first embodiment of the present technology;

[0035] Figure 2 is a diagram showing an example of a stacked structure of a solid-state image sensor according to a first embodiment of the present technology;

[0036] Figure 3 is a plan view showing a configuration example of a pixel chip according to a first embodiment of the present technology;

[0037] Figure 4 is a block diagram showing a configuration example of a circuit chip according to a first embodiment of the present technology;

[0038] Figure 5 is a block diagram showing a configuration example of a circuit block according to a first embodiment of the present technology;

[0039] Figure 6 is a block diagram showing a configuration example of a monitoring pixel according to a first embodiment of the present technology;

[0040] Figure 7 is a circuit diagram showing a configuration example of a monitoring pixel according to a first embodiment of the present technology;

[0041] Figure 8 is a circuit diagram showing a configuration example of a pulse generation circuit according to a first embodiment of the present technology;

[0042] Figure 9 is a timing diagram showing an operation example of a pulse generation circuit according to a first embodiment of the present technology;

[0043] Figure 10 is a circuit diagram showing a configuration example of an imaging pixel according to a first embodiment of the present technology;

[0044] Figure 11 is a plan view showing a configuration example of a pixel array section according to a first embodiment of the present technology;

[0045] Figure 12 is a block diagram showing a configuration example of a monitoring pixel, an imaging pixel, and a control section according to a first embodiment of the present technology;

[0046] Figure 13 is a circuit diagram showing a configuration example of a control section according to a first embodiment of the present technology;

[0047] Figure 14 is a diagram showing an example of changes in cathode potential and anode potential according to a first embodiment of the present technology;

[0048] Figure 15A is a diagram showing an example of changes in overbias VEX and anode potential VSPAD according to a first embodiment;

[0049] Figure 15B is a diagram showing an example of changes in overbias VEX in a comparative example, in which the anode potential VSPAD is not controlled;

[0050] Figure 16A is a timing diagram showing changes in cathode potential Vs obtained under relatively low light intensity;

[0051] Figure 16B is a timing diagram showing changes in cathode potential Vs obtained under relatively high light intensity;

[0052] Figure 17A is a timing diagram showing an example of fluctuations in bottom potential VBT obtained under low light intensity;

[0053] Figure 17B is a timing chart showing an example of fluctuations in the bottom potential VBT obtained under a large amount of light;

[0054] Figure 18 is a scatter plot showing an example of the variation range of the breakdown voltage according to the first embodiment of the present technology;

[0055] Figure 19 is a timing chart showing an example of the operation of the monitoring pixel and the control section according to the first embodiment of the present technology;

[0056] Figure 20 is a flowchart showing an example of the operation of the solid-state image sensor according to the first embodiment of the present technology;

[0057] Figure 21 is a block diagram showing an example of the configuration of the monitoring pixel of the first modification according to the first embodiment of the present technology;

[0058] Figure 22 is a block diagram showing an example of the configuration of the control section of the second modification according to the first embodiment of the present technology;

[0059] Figure 23 is a block diagram showing an example of the configuration of the inter-pixel average acquisition section of the third modification according to the first embodiment of the present technology;

[0060] Figure 24 is a block diagram showing an example of the configuration of the control section of the fourth modification according to the first embodiment of the present technology;

[0061] Figure 25 is a block diagram showing an example of the configuration of the control section of the fifth modification according to the first embodiment of the present technology;

[0062] Figure 26 is a circuit diagram showing an example of the configuration of the monitoring pixel of the sixth modification according to the first embodiment of the present technology;

[0063] Figure 27 is a circuit diagram showing an example of the configuration of the inter-pixel average acquisition section of the sixth modification according to the first embodiment of the present technology;

[0064] Figure 28 is a block diagram showing an example of the configuration of the monitoring pixel according to the second embodiment of the present technology;

[0065] Figure 29 is a circuit diagram showing an example of the configuration of the monitoring pixel according to the second embodiment of the present technology;

[0066] Figure 30is a timing chart showing an operation example of a monitoring pixel and a control section according to a second embodiment of the present technology;

[0067] Figure 31 is a circuit diagram showing a configuration example of a modified monitoring pixel according to a second embodiment of the present technology;

[0068] Figure 32 is a circuit diagram showing a configuration example of a modified buffer according to a second embodiment of the present technology;

[0069] Figure 33 is a block diagram showing an example of a schematic configuration of a vehicle control system;

[0070] Figure 34 is a diagram helping to explain an example of installation positions of an out-of-vehicle information detection section and an imaging section. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0071] Embodiments for implementing the present technology (hereinafter referred to as embodiments) will be described below. The description will be given in the following order.

[0072] 1. First Embodiment (Example of maintaining cathode potential during detection time)

[0073] 2. Second Embodiment (Example of omitting buffer but maintaining cathode potential during detection time)

[0074] 3. Application Example of Moving Object

[0075] <First Embodiment>

[0076] "Configuration Example of Distance Measurement Module"

[0077] Figure 1 is a block diagram showing a configuration example of a distance measurement module 100 according to a first embodiment of the present technology. The distance measurement module 100 is configured to measure the distance to an object. The distance measurement module 100 includes a light emitting section 110, a synchronization control section 120, and a solid-state image sensor (or light detection device) 200. The distance measurement module 100 is installed in a smart phone, a personal computer, a vehicle-mounted device, etc., and is used for measuring distance.

[0078] The synchronization control section 120 operates the light emitting section 110 and the solid-state image sensor 200 in synchronization with each other. The synchronization control section 120 supplies a clock signal having a predetermined frequency (for example, 10 to 20 MHz) to the light emitting section 110 and the solid-state image sensor 200 via signal lines 128 and 129 as a synchronization signal CLKp.

[0079] The light emitting section 110 supplies intermittent light as irradiation light in synchronization with the synchronization signal CLKp from the synchronization control section 120. For example, near-infrared light is used as the irradiation light.

[0080] The solid-state image sensor 200 is configured to receive the reflected light of the irradiated light, and measure the round-trip time between the light emission time indicated by the synchronization signal CLKp and the light reception time of the reflected light. The solid-state image sensor 200 calculates the distance to the object based on the round-trip time, generates distance data indicating the distance, and outputs the distance data.

[0081] Note that although the light-emitting part 110, the solid-state image sensor 200, and the synchronization control part 120 are mounted in the same distance measurement module 100, they may also be mounted in different devices. A system including the light-emitting part 110, the solid-state image sensor 200, and the synchronization control part 120 is an example of a distance measurement system according to an embodiment of the present technology.

[0082] "Configuration example of solid-state image sensor"

[0083] Figure 2 is a diagram showing an example of a stacked structure of the solid-state image sensor 200 according to the first embodiment of the present technology. The solid-state image sensor 200 includes a circuit chip 202 and a pixel chip 201 stacked above the circuit chip 202. These chips are electrically connected through connection parts such as vias. Note that these chips may also be connected by Cu-Cu bonding or bumps instead of vias.

[0084] Figure 3 is a plan view showing an example of the configuration of the pixel chip 201 according to the first embodiment of the present technology. The pixel chip 201 includes a rectangular light-receiving part 210. In the light-receiving part 210, a plurality of photoelectric conversion elements 211 and a plurality of photoelectric conversion elements 212 are arranged.

[0085] The photoelectric conversion elements 211 are linearly arranged along the boundary of the light-receiving part 210. For example, the photoelectric conversion elements 211 are arranged in a row at the upper end of the light-receiving part 210. On the other hand, the photoelectric conversion elements 212 are arranged in a two-dimensional dot matrix form. Among the photoelectric conversion elements 211 and 212, the photoelectric conversion elements 212 are used to generate pixel data of image data. On the other hand, the photoelectric conversion elements 211 are used to monitor the potential of either the cathode or the anode (for example, the potential of the cathode).

[0086] Figure 4 is a block diagram showing an example of the configuration of the circuit chip 202 according to the first embodiment of the present technology. The circuit chip 202 includes a time generation part 220, a circuit block 300, a histogram generation part 250, an output interface 260, multiplexers 231 and 232, and time-to-digital converters 241 and 242.

[0087] The time generation section 220 is configured to generate a control signal RCH in synchronization with the synchronization signal CLKp. The time generation section 220 supplies the control signal RCH to the circuit block 300.

[0088] In the circuit block 300, corresponding pixel circuits (not shown) of a plurality of monitoring pixels and a plurality of imaging pixels are arranged. Details of the respective circuit configurations of the monitoring pixels and the imaging pixels will be described later. The imaging pixel generates a pulse signal in response to the input of photons, and supplies the generated pulse signal to the multiplexer 231 or 232.

[0089] The multiplexer 231 sequentially selects the imaging pixels of odd-numbered rows, and supplies the pulse signals of the selected rows to the time-to-digital converter 241. The multiplexer 232 sequentially selects the imaging pixels of even-numbered rows, and supplies the pulse signals of the selected rows to the time-to-digital converter 242.

[0090] The time-to-digital converter 241 is configured to convert the time before the rise of the pulse signal in the odd-numbered rows into a digital signal. The digital signal represents the detection time of photons. The time-to-digital converter 241 supplies the digital signal to the histogram generation section 250. The time-to-digital converter 242 is configured to convert the time before the rise of the pulse signal in the even-numbered rows into a digital signal. The time-to-digital converter 242 supplies the digital signal to the histogram generation section 250.

[0091] The multiplexers 231 and 232 and the time-to-digital converters 241 and 242 enable the simultaneous processing of the pulse signals in two rows. Note that the solid-state image sensor 200 may also process the pulse signals row by row. In this case, the circuit chip includes one of the multiplexers 231 / 232 and one of the time-to-digital converters 241 / 242.

[0092] The histogram generation section 250 is configured to generate a histogram based on the digital signals from the time-to-digital converters 241 and 242. Here, the histogram is a graph showing the detection frequency of the respective detection times indicated by the digital signals as frequencies. The histogram generation section 250 generates a histogram for each imaging pixel, and calculates the time of each peak as the light reception time of the reflected light. Next, for each imaging pixel, the histogram generation section 250 converts the round-trip time between the emission time of the irradiation light indicated by the synchronization signal and the light reception time of the reflected light into the distance to the object. The histogram generation section 250 generates distance data indicating the calculated distance of each imaging pixel, and outputs the distance data to the outside via the output interface 260.

[0093] Figure 5It is a block diagram showing a configuration example of a circuit block 300 according to a first embodiment of the present technology. The circuit block 300 includes a plurality of monitoring pixel circuits 310, a plurality of imaging pixel circuits 380, and a control section (or control circuit) 500.

[0094] The monitoring pixel circuit 310 is provided for each photoelectric conversion element 211, and the monitoring pixel circuit is connected to the corresponding photoelectric conversion element 211. The photoelectric conversion element 211 and the monitoring pixel circuit 310 connected to the photoelectric conversion element 211 function as a single monitoring pixel. The monitoring pixel is a pixel for monitoring the potential (e.g., the potential of the cathode) of either the cathode or the anode of the photoelectric conversion elements 211 and 212.

[0095] The imaging pixel circuit 380 is provided for each photoelectric conversion element 212, and the imaging pixel circuit is connected to the corresponding photoelectric conversion element 212. The photoelectric conversion element 212 and the imaging pixel circuit 380 corresponding to the photoelectric conversion element 212 function as a single imaging pixel. The imaging pixel is a pixel for generating a pulse signal in response to the input of photons.

[0096] The control section 500 is configured to control the potential (e.g., the potential of the anode) of either the cathode or the anode of the photoelectric conversion elements 211 and 212 based on the target potential (e.g., the cathode) of the monitoring pixel.

[0097] "Configuration example of the monitoring pixel"

[0098] Figure 6 It is a block diagram showing a configuration example of a monitoring pixel (or first pixel circuit) 401 according to a first embodiment of the present technology. As described above, the circuit including the photoelectric conversion element 211 of the pixel chip 201 and the monitoring pixel circuit 310 of the circuit chip 202 functions as a single monitoring pixel 401. In addition, the monitoring pixel circuit 310 includes a p-channel metal oxide semiconductor (pMOS) transistor 311, a time detection circuit (or delay circuit) 320, a sampling and holding circuit (or holding circuit) 330, and buffers (or buffer circuits) 340 and 350.

[0099] The pMOS transistor 311 is interposed between the power supply potential VE and the photoelectric conversion element 211. In addition, the control signal RCH is input from the time generation section 220 to the gate of the pMOS transistor 311. When the low-level control signal RCH is input, the pMOS transistor 311 supplies the power supply potential VE to the photoelectric conversion element 211 to the connection node 312. Note that the power supply potential VE is an example of a predetermined potential according to an embodiment of the present technology, and the pMOS transistor 311 is an example of a potential supply element according to an embodiment of the present technology. In addition, the connection node 312 is an example of a predetermined node according to an embodiment of the present technology.

[0100] The photoelectric conversion element 211 is configured to output a photocurrent by photoelectric conversion in response to incident photons. For example, an SPAD is used as the photoelectric conversion element 211. The cathode of the photoelectric conversion element 211 is connected to the connection node 312, and the cathode potential Vs of the cathode is the potential to be monitored. On the other hand, the anode of the photoelectric conversion element 211 is connected to the control section 500, and the control section 500 controls the anode potential VSPAD of the anode.

[0101] The buffer 340 is interposed between the connection node 312 and the sample-and-hold circuit 330. Note that the buffer 340 is an example of the input-side buffer according to the embodiment of the present technology.

[0102] The time detection circuit 320 is configured to monitor the cathode potential Vs and detect the time when a predetermined period of time has elapsed since the cathode potential Vs started to decrease from the potential provided by the pMOS transistor 311 (i.e., the power supply potential VE). When the cathode potential Vs is the potential to be monitored, the cathode potential Vs becomes lower than the power supply potential VE when a photocurrent flows in response to incident photons. Note that, as described below, the monitoring pixel 401 can also monitor the anode potential. When monitoring the anode potential, the time detection circuit 320 detects the time when a predetermined period of time has elapsed since the anode potential started to increase.

[0103] The sample-and-hold circuit 330 is configured to capture and hold the cathode potential Vs based on the time detected by the time detection circuit 320. The sample-and-hold circuit 330 outputs the held potential as the held potential Vs_SH to the buffer 350.

[0104] The buffer 350 is interposed between the sample-and-hold circuit 330 and the control section 500. Note that the buffer 350 is an example of the output-side buffer according to the embodiment of the present technology. Note that the buffer 350 is not essential, and the buffer 350 can be omitted. In addition, two or more buffers 340 / 350 can also be installed.

[0105] Figure 7 is a circuit diagram showing an example of the configuration of the monitoring pixel 401 according to the first embodiment of the present technology. The time detection circuit 320 includes an inverter 321 and a pulse generation circuit 370. In addition, the sample-and-hold circuit 330 includes a sampling switch 331 and a capacitor 332. The buffer 350 includes an nMOS transistor 351 and a current source 352.

[0106] The inverter 321 in the time detection circuit 320 is configured to invert the signal of the cathode potential Vs and output the inverted signal to the pulse generation circuit 370. In addition, the pulse generation circuit 370 is configured to delay the inverted signal from the inverter 321 by a predetermined delay time and generate a pulse signal SW based on the delayed signal. The pulse generation circuit 370 supplies the pulse signal SW to the sampling switch 331.

[0107] The sampling switch 331 in the sample and hold circuit 330 is configured to capture (in other words, sample) the cathode potential Vs via the buffer 340 during the period of the pulse width of the pulse signal SW. The capacitor 332 is configured to hold the sampled cathode potential Vs as the hold potential Vs_SH.

[0108] In the buffer 350, the nMOS transistor 351 is interposed between the power supply potential and the current source 352. In addition, the hold potential Vs_SH is input from the sample and hold circuit 330 to the gate of the nMOS transistor 351. In addition, the back gate of the nMOS transistor 351 is connected to the connection node between the nMOS transistor 351 and the current source 352. The connection node is connected to the control section 500.

[0109] Note that the circuit configuration of the buffer 340 is similar to that of the buffer 350.

[0110] Figure 8 is a circuit diagram showing a configuration example of the pulse generation circuit 370 according to the first embodiment of the present technology. The pulse generation circuit 370 includes a delay circuit 371, an inverter 376, a delay circuit 377, a NAND gate 378, and an inverter 379. The delay circuit 371 includes a current source 372, a pMOS transistor 373, an n-channel metal oxide semiconductor (nMOS) transistor 374, and a capacitor 375.

[0111] The delay circuit 371 is configured to delay the inverted signal VA from the inverter 321 by a predetermined delay time. In the delay circuit 371, the pMOS transistor 373, the nMOS transistor 374, and the current source 372 are connected in series between the power supply potential and the ground potential. In addition, the gates of the pMOS transistor 373 and the nMOS transistor 374 are commonly connected to the output terminal of the inverter 321. The capacitor 375 is interposed between the ground potential and the connection node connecting the pMOS transistor 373 to the nMOS transistor 374. In addition, the connection node outputs the delayed signal VB obtained by delaying the inverted signal VA.

[0112] The inverter 376 is configured to invert the delayed signal VB. The inverter 376 outputs the inverted signal VC to the delay circuit 377 and the NAND gate 378.

[0113] The delay circuit 377 is configured to delay the inverted signal VC by a predetermined delay time. The circuit configuration of the delay circuit 377 is similar to that of the delay circuit 371. The delay circuit 377 outputs the delayed signal VD to the NAND gate 378.

[0114] The NAND gate 378 is configured to output, as an output signal, the NAND of the inverted signal VC and the delayed signal VD to the inverter 379.

[0115] The inverter 379 is configured to invert the output signal from the NAND gate 378. The inverter 379 outputs the inverted signal as the pulse signal SW to the sample and hold circuit 330.

[0116] Figure 9 is a timing chart showing an operation example of the pulse generation circuit 370 according to the first embodiment of the present technology.

[0117] Assume that at time T1, the inverted signal VA from the inverter 321 rises from a low level to a high level. The delay circuit 371 delays the inverted signal VA and outputs the delayed signal VB.

[0118] In addition, the inverter 376 inverts the delayed signal VB. The inverted signal VC rises at time T2. The delay circuit 377 delays the inverted signal VC and outputs the delayed signal VD.

[0119] In addition, at time T2, the inverter 379 inverts the NAND of the inverted signal VC and the delayed signal VD and generates the pulse signal SW. The pulse width of the pulse signal SW is the time period between time T2 and time T3.

[0120] "Configuration Example of Imaging Pixel"

[0121] Figure 10 is a circuit diagram showing a configuration example of the imaging pixel 402 according to the first embodiment of the present technology. As described above, the circuit of the imaging pixel circuit 380 including the photoelectric conversion element 212 and the circuit chip 202 of the pixel chip 201 functions as a single imaging pixel 402. The imaging pixel circuit 380 includes a pMOS transistor 381 and an inverter 382.

[0122] The connection structure between the pMOS transistor 381 and the photoelectric conversion element 212 is similar to the connection structure between the pMOS transistor 311 and the photoelectric conversion element 211 in the monitoring pixel 401.

[0123] The inverter 382 is configured to invert the signal of the cathode potential of the photoelectric conversion element 212 and provide the inverted signal as the pulse signal of the imaging pixel 402 to the multiplexer 231 (or the multiplexer 232).

[0124] Figure 11 It is a plan view showing a configuration example of a pixel array section 400 according to a first embodiment of the present technology. The pixel array section 400 includes a light receiving section 210 of a pixel chip 201 and a circuit block 300 of a circuit chip 202.

[0125] In the pixel array section 400, a plurality of monitoring pixels 401 and a plurality of imaging pixels 402 are arranged. The monitoring pixels 401 are linearly arranged along the boundary of the pixel array section 400. For example, the monitoring pixels 401 are arranged in a row at the upper end of the pixel array section 400. On the other hand, the imaging pixels 402 are arranged in a two-dimensional dot matrix form.

[0126] Figure 12 It is a block diagram showing a configuration example of the monitoring pixel 401, the imaging pixel 402, and the control section 500 according to a first embodiment of the present technology. The control section 500 includes an inter-pixel average acquisition section (or average circuit) 510, a temporal average acquisition section (or temporal average circuit) 520, and a potential control section (or potential controller) 530.

[0127] Each of the plurality of monitoring pixels 401 supplies a holding potential Vs_SH to the inter-pixel average acquisition section 510. The holding potential of the m-th monitoring pixel 401 is referred to as Vs_SHm (m is an integer).

[0128] The inter-pixel average acquisition section 510 is configured to calculate an average value of the respective holding potentials Vs_SHm of the plurality of monitoring pixels 401 as an inter-pixel average value Vs_SHAVp. The inter-pixel average acquisition section 510 supplies the inter-pixel average value Vs_SHAVp to the temporal average acquisition section 520.

[0129] The temporal average acquisition section 520 is configured to calculate a temporal average value Vs_SHAVt of the inter-pixel average value Vs_SHAVp. The temporal average acquisition section 520 supplies the temporal average value Vs_SHAVt to the potential control section 530.

[0130] The potential control section 530 is configured to control the anode potential VSPAD in such a manner that as the temporal average value Vs_SHAVt of the held cathode potential becomes higher, the anode potential VSPAD becomes lower. All the anodes of the plurality of monitoring pixels 401 and the plurality of imaging pixels 402 are commonly connected to the potential control section 530, and the potential control section 530 controls the potential of the anodes. Note that if the monitoring pixel 401 monitors the anode potential, the potential control section 530 controls the cathode potential.

[0131] In addition, in the monitoring pixel 401, one of the anode and cathode of the photoelectric conversion element 211 (for example, the cathode) is connected to the connection node 312. In response to the control signal RCH, the pMOS transistor 311 supplies the power supply potential VE to the connection node 312.

[0132] The time detection circuit 320 detects the time when a predetermined period of time has elapsed since the cathode potential Vs of the connection node 312 started to decrease from the power supply potential VE. This time corresponds to the time when a predetermined delay time has elapsed since the cathode potential dropped below the threshold of the inverter 321.

[0133] The sample and hold circuit 330 captures and holds the cathode potential Vs as the hold potential Vs_SH based on the time detected by the time detection circuit 320.

[0134] Next, the control section 500 controls the other of the anode and cathode of the photoelectric conversion element 211 (for example, the anode) such that the potential becomes lower as the hold potential Vs_SH becomes higher.

[0135] In addition, in the monitoring pixel 401, the buffer 340 is installed at a stage before the sample and hold circuit 330. This enables the capacitances of the corresponding connection nodes of the monitoring pixel 401 and the imaging pixel 402 to be monitored uniformly. This connection node is the connection node between the photoelectric conversion element and the pMOS transistor. This enables the breakdown voltages VBD of the corresponding monitoring pixel 401 and imaging pixel 402 to be monitored uniformly.

[0136] "Configuration Example of Control Section"

[0137] Figure 13 is a circuit diagram showing a configuration example of the control section 500 according to the first embodiment of the present technology. The inter-pixel averaging acquisition section 510 includes a capacitor 512 and a plurality of resistors 511. The resistors 511 are provided to the corresponding monitoring pixels 401. The time averaging acquisition section 520 includes a variable resistor 521 and a variable capacitor 522. The potential control section 530 includes an amplifier 531.

[0138] One end of the resistor 511 in the inter-pixel average acquisition section 510 is connected to the corresponding monitoring pixel 401, and the other end is connected to one end of the capacitor 512 and the time average acquisition section 520. In other words, a plurality of resistors 511 are connected in parallel between the plurality of monitoring pixels 401 and the capacitor 512. The other end of the capacitor 512 is connected to the ground potential. The resistor 511 makes it possible to generate an average potential of the holding potential Vs_SHm of the plurality of monitoring pixels 401 as the inter-pixel average value Vs_SHAvp, and the capacitor 512 holds the inter-pixel average value Vs_SHAvp. By acquiring the inter-pixel average value, adverse effects caused by variations in the holding potential Vs_SH between pixels can be suppressed.

[0139] In addition, one end of the variable resistor 521 in the time average acquisition section 520 is connected to the inter-pixel average acquisition section 510, and the other end is connected to one end of the variable capacitor 522 and the potential control section 530. The other end of the variable capacitor 522 is connected to the ground potential. The circuit including the variable resistor 521 and the variable capacitor 522 functions as an analog low-pass filter that generates a time average value Vs_SHAVt of the inter-pixel average value Vs_SHAVp. Note that the circuit including the variable resistor 521 and the variable capacitor 522 is an example of an analog filter according to an embodiment of the present technology.

[0140] The time average value Vs_SHAVt is input to the inverting input terminal (-) of the amplifier 531 in the potential control section 530, and a predetermined power supply potential is input to the non-inverting input terminal (+). The amplifier 531 generates a comparison result between the time average value Vs_SHAVt and the predetermined power supply potential as VSPAD by using the following expression, and supplies VSPAD to the anodes of the monitoring pixel 401 and the imaging pixel 402.

[0141] VSPAD = Av(VREF - Vs_SHAVt),

[0142] In the above expression, Av represents the gain of the amplifier 531, and VREF represents the target value of VSPAD.

[0143] Figure 14 is a diagram showing an example of changes in the cathode potential Vs and the anode potential VSPAD according to the first embodiment of the present technology. The pMOS transistor 311 supplies the power supply potential VE, and then the cathode potential Vs becomes the power supply potential VE. When photons enter, the cathode potential Vs drops to the bottom potential VBT and increases to the initial power supply potential VE by recharging.

[0144] Here, the voltage between the power supply potential VE and the bottom potential VBT is referred to as the overbias VEX. In addition, the voltage between the bottom potential VBT and the anode potential VSPAD is referred to as the breakdown voltage VBD. With the power supply potential VE and the anode potential VSPAD being constant, the overbias VEX varies according to changes in temperature and the breakdown voltage VBD.

[0145] In the case where the overbias VEX becomes smaller, when photons enter, the sensitivity of the photodiode in the imaging pixel 402 decreases. In this case, even when photons enter, a pulse signal of the imaging pixel 402 is not generated, and the photon detection efficiency (PDE) decreases. Therefore, when the cathode potential Vs decreases, as the holding potential becomes higher, the control section 500 decreases the anode potential VSPAD. This makes it possible to increase the breakdown voltage VBD, increase the overbias VEX, and improve the PDE.

[0146] Figure 15A and Figure 15B are diagrams showing examples of changes in the overbias VEX and the anode potential VSPAD according to the first embodiment of the present technology and a comparative example. Figure 15A is a diagram showing an example of changes in the overbias VEX and the anode potential VSPAD according to the first embodiment. Figure 15B is a diagram showing an example of changes in the overbias VEX according to a comparative example in which the anode potential VSPAD is not controlled. In Figure 15A and Figure 15B , the vertical axis represents the potential, and the horizontal axis represents the temperature. In addition, in Figure 15A and Figure 15B , it is assumed that the amount of incident light is constant, and the holding potential Vs_SH is substantially the same as the bottom potential VBT.

[0147] The holding potential (bottom potential VBT) increases as the temperature rises. Therefore, as shown in Figure 15A , the control section 500 decreases the anode potential VSPAD corresponding to the increased value. As a result, the overbias VEX can be maintained at a constant value regardless of temperature changes. This makes it possible to suppress a decrease in the PDE caused by temperature changes.

[0148] On the other hand, in the comparative example where the anode potential VSPAD is not controlled, as shown in Figure 15B , the bottom potential VBT increases as the temperature rises, so the overbias VEX decreases. This results in a decrease in the PDE.

[0149] As shown in Figure 15A and Figure 15BAs shown, under the control of the control section 500, a decrease in the PDE caused by temperature changes can be suppressed. However, the monitoring voltage (e.g., cathode potential) for observing the bottom potential VBT follows the change in the excessive bias caused by temperature, and the monitoring voltage also changes according to a decrease or increase in the incident light amount.

[0150] Figure 16A and Figure 16B are timing charts showing the change in the cathode potential Vs obtained in the case of a large light amount and the change in the cathode potential Vs obtained in the case of a small light amount according to the first embodiment of the present technology. Figure 16A is a timing chart showing the change in the cathode potential Vs obtained in the case of a relatively small light amount. Figure 16B is a timing chart showing the change in the cathode potential Vs obtained in the case of a relatively large light amount. In Figure 16A and Figure 16B it is assumed that the temperature is constant.

[0151] In the case of a small light amount as shown in Figure 16A recharging is performed at time T1, and the cathode potential Vs becomes the power supply potential VE. Next, when photons enter at time T10, the cathode potential Vs starts to decrease. After time T12, the cathode potential Vs becomes constant. The potential obtained at time T12 is the bottom potential VBT1.

[0152] On the other hand, in the case of a large light amount as shown in Figure 16B the cathode potential Vs has the same trajectory as Figure 16A until time T12. However, after time T12, the leakage current increases in response to the light amount, and the cathode potential Vs further decreases. Subsequently, the cathode potential Vs reaches the bottom potential VBT2 immediately before time T2 when recharging is performed again. The bottom potential VBT2 is lower than the bottom potential VBT1 obtained in the case of a small light amount.

[0153] As described above, even when the temperature is constant, the bottom potential VBT changes due to a decrease or increase in the incident light amount. Therefore, if the control section 500 controls the anode potential VSPAD based on the bottom potential VBT, this causes a change in the voltage value for suppressing the change in the excessive bias caused by a decrease or increase in the light amount.

[0154] Therefore, the time detection circuit 320 in the monitoring pixel 401 adjusts the delay time and the threshold VT, and detects time T12 in such a way that time T12 is the time when the delay time has elapsed from time T11. Next, the sample and hold circuit 330 captures the cathode potential Vs at time T12 and holds it as the hold potential Vs_SH. As shown in Figure 16A and Figure 16B before time T12Figure 16A the trajectory of the cathode potential Vs in Figure 16B is the same as the trajectory of the cathode potential Vs in

[0155] Figure 17A and Figure 17B is a timing chart showing an example of fluctuations in the bottom potential VBT obtained in the case of a large amount of light and an example of fluctuations in the bottom potential VBT obtained in the case of a small amount of light according to the first embodiment of the present technology. Figure 17A is a timing chart showing an example of fluctuations in the bottom potential VBT obtained in the case of a small amount of light. Figure 17B is a timing chart showing an example of fluctuations in the bottom potential VBT obtained in the case of a large amount of light. In addition, the dashed line indicates the time average of the bottom potential VBT.

[0156] Figure 18 is a scatter diagram showing an example of the change range of the breakdown voltage VBD according to the first embodiment of the present technology. In Figure 18 the vertical axis represents the voltage of the breakdown voltage VBD, and the horizontal axis represents the number of pixels (monitoring pixels and imaging pixels). In addition, each plotted point represents the breakdown voltage VBD of a single pixel, and the solid curve represents the boundary of a set of plotted points. As Figure 18 shown, the distribution of the breakdown voltage VBD is similar to a normal distribution.

[0157] Figure 19 is a timing chart showing an example of the operation of the monitoring pixel 401 and the control section 500 according to the first embodiment of the present technology. The monitoring pixel 401 is recharged at time T1, and the cathode potential Vs becomes the power supply potential VE. Next, when photons enter at time T10, the cathode potential Vs starts to decrease.

[0158] When the cathode potential Vs drops below the threshold VT of the inverter 321 at time T11, the inverted signal of the inverter 321 rises, and the pulse generation circuit 370 generates a pulse signal SW at time T12 after delaying the inverted signal by a delay time.

[0159] The sample and hold circuit 330 captures the cathode potential Vs during the pulse width period of the pulse signal SW and holds it as the hold potential Vs_SH.

[0160] In addition, at time T1, the connection node 312 transitions from a high impedance (Hi-Z) state to a low impedance (Low-Z) state through recharge. Subsequently, the connection node 312 transitions to the high impedance state before time T12.

[0161] The amount of decrease in the cathode potential Vs after time T12 varies according to the amount of light. However, at time T12, the sample and hold circuit 330 holds the cathode potential Vs. This enables the held potential Vs_SH to be maintained at a constant value regardless of the amount of light. Therefore, when the control section 500 controls the anode potential VSPAD in response to the held potential Vs_SH, changes in the excessive bias caused by a decrease or increase in the amount of light can be suppressed.

[0162] "Operation Example of Solid-State Image Sensor"

[0163] Figure 20 is a flowchart showing an operation example of the solid-state image sensor 200 according to the first embodiment of the present technology. For example, when a predetermined application for measuring distance is executed, this operation starts.

[0164] The monitoring pixel 401 detects the time when a delay time has elapsed since the cathode potential Vs has dropped below the threshold VT (step S901). Next, the monitoring pixel 401 captures and holds the cathode potential Vs based on the time (step S902). The control section 500 controls the anode potential VSPAD in such a manner that the anode potential VSPAD decreases as the held potential becomes higher (step S903). After step S903, the monitoring pixel 401 repeatedly executes step S901 and subsequent steps.

[0165] As described above, according to the first embodiment of the present technology, the monitoring pixel 401 detects the time when a predetermined period of time has elapsed since the cathode potential has dropped, and captures and holds the cathode potential at that time. This enables the potential to be maintained without depending on the amount of light. When the control section 500 controls the anode potential in response to the held potential, changes in the bias voltage caused by a decrease or increase in the amount of light can be suppressed.

[0166] "First Modification"

[0167] In the above-described first embodiment, the monitoring pixel 401 monitors the cathode potential Vs of the photoelectric conversion element 211 and controls the anode potential based on the cathode potential Vs. However, the monitoring pixel 401 may monitor the anode potential instead of the cathode potential. The monitoring pixel 401 according to the first modification of the first embodiment is different from the monitoring pixel 401 according to the first embodiment in that the monitoring pixel 401 according to the first modification monitors the anode potential of the photoelectric conversion element 211 and controls the cathode potential based on the anode potential.

[0168] Figure 21It is a block diagram showing a configuration example of a monitoring pixel 401 according to a first modification of the present technology. In the monitoring pixel 401 according to the first modification of the first embodiment, the anode of the photoelectric conversion element 211 is connected to the connection node 312, and the cathode is connected to the control section 500. Further, a pMOS transistor 311 is interposed between the connection node 312 and the ground potential VS.

[0169] Note that the connection structure between the photoelectric conversion element 212 and the pMOS transistor 381 in the imaging pixel 402 is similar to the connection structure of the monitoring pixel 401.

[0170] The time detection circuit 320 detects the time when a predetermined period of time has elapsed since the anode potential has become higher than the ground potential VS. In this case, for example, the time detection circuit 320 only needs to include two-stage inverters, or includes a buffer instead of an inverter.

[0171] As described above, according to the first modification of the first embodiment of the present technology, the monitoring pixel 401 detects the time when a predetermined period of time has elapsed since the anode potential increased, and captures and holds the anode potential at that time. This enables the potential to be held without depending on the amount of light. When the control section 500 controls the cathode potential in response to the held potential, changes in the bias voltage caused by a decrease or increase in the amount of light can be suppressed.

[0172] "Second modification"

[0173] In the above-described first embodiment, the function of the control section 500 is implemented by an analog circuit. However, generally, an analog circuit has a larger circuit size than a digital circuit. Therefore, this may lead to an increase in the occupied area. The control section 500 according to the second modification of the first embodiment is different from the control section 500 according to the first modification in that the control section 500 according to the second modification includes a digital circuit.

[0174] Figure 22 It is a block diagram showing a configuration example of the control section 500 according to the second modification of the first embodiment of the present technology. In the control section 500 according to the second modification of the first embodiment, the inter-pixel averaging acquisition section 510 includes an analog-to-digital conversion section 513 and an averaging filter 515. Further, the time averaging acquisition section 520 includes a digital low-pass filter 524. The potential control section 530 includes a power integrated circuit (IC) 533.

[0175] The analog-to-digital conversion section 513 is configured to convert the respective holding potentials of the plurality of monitoring pixels 401 into digital signals. The analog-to-digital conversion section 513 includes a plurality of analog-to-digital converters (ADCs) 514. An ADC 514 is provided for the respective monitoring pixels 401. The ADC 514 converts the holding potential Vs_SHm of the corresponding monitoring pixel 401 into a digital signal and provides the digital signal to the averaging filter 515.

[0176] The averaging filter 515 is a digital filter that calculates the average value of the respective digital signals of the plurality of monitoring pixels 401 as the inter-pixel average value Vs_SHAVp.

[0177] The digital low-pass filter 524 is a digital filter that passes low-frequency components. The low-frequency components are lower than a predetermined cut-off frequency. This makes it possible to obtain the time average value Vs_SHAVt of the inter-pixel average value Vs_SHAVp.

[0178] The power IC 533 is configured to control the anode potential VSPAD in such a way that the anode potential VSPAD becomes lower as the time average value Vs_SHAVt becomes higher. Note that the power IC 533 is an example of a power semiconductor according to an embodiment of the present technology.

[0179] As Figure 22 shown, when the function of the control section 500 is implemented by a digital circuit, the occupied area of the control section 500 can be reduced.

[0180] As described above, according to the second modification of the first embodiment of the present technology, the control section 500 includes a digital circuit. This makes it possible to reduce the occupied area as compared with the case of an analog circuit.

[0181] "Third Modification"

[0182] In the second modification of the above-described first embodiment, the inter-pixel average acquisition section 510 includes an ADC 514 corresponding to the respective monitoring pixels 401. However, in this case, as the number of monitoring pixels 401 becomes larger, the number of ADCs 514 increases. The inter-pixel average acquisition section 510 according to the third modification of the first embodiment is different from the inter-pixel average acquisition section 510 according to the second modification of the first embodiment in that a single ADC 514 is shared by the plurality of monitoring pixels 401 according to the third modification.

[0183] Figure 23FIG. is a block diagram showing a configuration example of an inter-pixel average acquisition section 510 according to a third modification of the first embodiment of the present technology. The inter-pixel average acquisition section 510 according to the third modification of the first embodiment is different from the inter-pixel average acquisition section 510 according to the second modification of the first embodiment in that the analog-to-digital conversion section 513 according to the third modification includes a single selector 516 and a single ADC 514.

[0184] The selector 516 is configured to sequentially select any one of the respective holding potentials Vs_SHm of the plurality of monitoring pixels 401. The selector 516 supplies the selected holding potential to the ADC 514. Each time a holding potential is selected, the ADC 514 converts the holding potential into a digital signal and supplies the digital signal to the averaging filter 515.

[0185] As Figure 23 shown, since the selector 516 is installed, the plurality of monitoring pixels 401 can share a single ADC 514. This makes it possible to reduce the circuit size compared to the case where an ADC 514 is provided for each of the corresponding monitoring pixels 401.

[0186] As described above, according to the third modification of the first embodiment of the present technology, the selector 516 is installed for selecting any one of the respective holding potentials Vs_SHm of the plurality of monitoring pixels 401. This allows the plurality of monitoring pixels 401 to share a single ADC 514.

[0187] "Fourth Modification"

[0188] In the above-described first embodiment, the function of the control section 500 is implemented by an analog circuit. However, generally, an analog circuit has a larger circuit size than a digital circuit. Therefore, this may cause an increase in the size of the occupied area. The control section 500 according to the fourth modification of the first embodiment is different from the control section 500 according to the first modification in that the control section 500 according to the fourth modification includes a digital circuit.

[0189] Figure 24 FIG. is a block diagram showing a configuration example of the control section 500 according to the fourth modification of the first embodiment of the present technology. In the control section 500 according to the fourth modification of the first embodiment, the time-average acquisition section 520 includes an ADC 523 and a digital low-pass filter 524, and the potential control section 530 includes a power IC 533. In addition, the circuit configuration of the inter-pixel average acquisition section 510 according to the fourth modification of the first embodiment is similar to the circuit configuration of the first embodiment.

[0190] The ADC 523 is configured to convert the analog inter-pixel average value Vs_SHAVp into a digital signal and supply the digital signal to the digital low-pass filter 524.

[0191] As described above, according to the fourth modification of the first embodiment of the present technology, the time-average acquisition section 520 and the potential control section 530 include digital circuits. This makes it possible to reduce the occupied area size compared to the case of analog circuits.

[0192] "Fifth Modification"

[0193] In the above-described first embodiment, the functions of the control section 500 are implemented by an analog circuit. However, generally, an analog circuit has a larger circuit size than a digital circuit. Therefore, this may lead to an increase in the occupied area size. The control section 500 according to the fifth modification of the first embodiment is different from the control section 500 according to the first modification in that the control section 500 according to the fifth modification includes a digital circuit.

[0194] Figure 25 FIG. is a block diagram showing a configuration example of the control section 500 according to the fifth modification of the first embodiment of the present technology. In the control section 500 according to the fifth modification of the first embodiment, the potential control section 530 includes an ADC 532 and a power IC 533. In addition, the circuit configurations of the inter-pixel average acquisition section 510 and the time-average acquisition section 520 according to the fifth modification of the first embodiment are similar to the circuit configuration of the first embodiment.

[0195] The ADC 532 is configured to convert the analog time average value Vs_SHAVt into a digital signal and provide the digital signal to the power IC 533.

[0196] As described above, according to the fifth modification of the first embodiment of the present technology, the potential control section 530 includes a digital circuit. This makes it possible to reduce the occupied area size compared to the case of analog circuits.

[0197] "Sixth Modification"

[0198] In the above-described first embodiment, the buffers 340 and 350 output single-ended signals. However, if the number of monitoring pixels 401 increases and, as a result, the signal lines for transmitting the single-ended signals have a longer wire length, the wiring resistance increases. This may lead to insufficient driving force of the buffers 340 and 350. The buffers 340 and 350 according to the sixth modification of the first embodiment are different from the buffers 340 and 350 according to the first embodiment in that the buffers 340 and 350 according to the sixth modification output differential signals.

[0199] Figure 26It is a circuit diagram showing a configuration example of a monitoring pixel 401 according to a sixth modification of the first embodiment of the present technology. In the monitoring pixel 401 according to the sixth modification of the first embodiment, the buffer 340 includes current sources 341 and 343 and pMOS transistors 342 and 344. In addition, the buffer 350 includes current sources 352 and 354 and nMOS transistors 351 and 353.

[0200] In the buffer 340, the current source 341 and the pMOS transistor 342 are connected in series between the power supply potential and the ground potential. The current source 341 is connected to the power supply side, and the gate of the pMOS transistor 342 is connected to the connection node 312. In addition, the connection node between the current source 341 and the pMOS transistor 342 is connected to the sampling switch 331.

[0201] The current source 343 and the pMOS transistor 344 are connected in series between the power supply potential and the ground potential. The current source 343 is connected to the power supply side, and the gate of the pMOS transistor 344 is connected to the ground potential. In addition, the connection node between the current source 343 and the pMOS transistor 344 is connected to the buffer 350.

[0202] In the buffer 350, the nMOS transistor 351 and the current source 352 are connected in series between the power supply potential and the ground potential. The current source 352 is connected to the ground side, and the gate of the nMOS transistor 351 is connected to the sampling switch 331. In addition, the connection node between the nMOS transistor 351 and the current source 352 is connected to the control section 500 via the signal line 358.

[0203] The nMOS transistor 353 and the current source 354 are connected in series between the power supply potential and the ground potential. The current source 354 is connected to the ground side, and the gate of the nMOS transistor 353 is connected to the buffer 340. In addition, the connection node between the nMOS transistor 353 and the current source 354 is connected to the control section 500 via the signal line 359.

[0204] Figure 26 The connection structure shown allows the buffer 340 to generate a differential signal based on the cathode potential Vs and output the generated differential signal, and allows the buffer 350 to generate a differential signal based on the holding potential Vs_SH and output the generated differential signal.

[0205] Figure 27 It is a circuit diagram showing a configuration example of an inter-pixel average acquisition section 510 according to a sixth modification of the first embodiment of the present technology. The inter-pixel average acquisition section 510 according to the sixth modification of the first embodiment includes capacitors 518 and 519 and an ADC 517.

[0206] The positive sides of the respective differential signals of a plurality of monitoring pixels 401 are commonly connected to the positive side input terminals of a capacitor 518 and an ADC 517. In addition, the negative sides of the respective differential signals of the plurality of monitoring pixels 401 are commonly connected to the positive side input terminals of a capacitor 519 and the ADC 517. The ADC 517 converts the differential signal into a digital signal and outputs the digital signal to a time averaging acquisition section 520.

[0207] As described above, in the sixth modification of the first embodiment of the present technology, buffers 340 and 350 output differential signals. This enables a more accurate output value to be obtained than in the case of outputting a single-ended signal.

[0208] <2. Second Embodiment>

[0209] In the above-described first embodiment, the monitoring pixel 401 includes two-stage buffers (340 and 350). However, compared with the case of including a single-stage buffer, such a monitoring pixel consumes more electric power and requires more response time. Here, the response time refers to the time from when a photon enters until the cathode potential is held. The monitoring pixel 401 according to the second embodiment is different from the monitoring pixel 401 according to the first embodiment in that the monitoring pixel 401 according to the second embodiment omits the buffer.

[0210] Figure 28 is a block diagram showing a configuration example of a monitoring pixel 401 according to a second embodiment of the present technology. The monitoring pixel 401 according to the second embodiment is different from the monitoring pixel 401 according to the first embodiment in that the monitoring pixel 401 according to the second embodiment does not include the buffer 340.

[0211] Figure 29 is a circuit diagram showing a configuration example of a monitoring pixel 401 according to a second embodiment of the present technology. In the monitoring pixel 401 according to the second embodiment, the time detection circuit 320 includes a delay circuit 371 instead of the pulse generation circuit 370. In addition, the buffer 350 includes a current source 355 and pMOS transistors 356 and 357.

[0212] The circuit configuration of the delay circuit 371 according to the second embodiment is similar to the circuit configuration of the first embodiment. The delay circuit 371 delays an inverted signal from an inverter 321 by a predetermined delay time and supplies the delayed signal SW’ to a sampling switch 331.

[0213] The sample and hold circuit 330 captures the cathode potential Vs when the delayed signal SW’ is at a high level and holds the captured potential when the delayed signal SW’ is at a low level.

[0214] In addition, in buffer 350, current source 355 and pMOS transistors 356 and 357 are connected in series between the power supply potential and the ground potential. The trigger signal Tr is input to the gate of pMOS transistor 356, and the holding potential Vs_SH of the sample and hold circuit 330 is input to the gate of pMOS transistor 357. The trigger signal Tr is the same signal as the delayed signal SW'. When the sample and hold circuit 330 is turned on, pMOS transistor 357 is turned off, and when the sample and hold circuit 330 is turned off, pMOS transistor 357 is turned on. In addition, the connection node between pMOS transistors 356 and 357 is connected to control section 500.

[0215] As Figure 29 shown, buffer 340 is omitted. Therefore, the power consumption can be reduced by the amount of power consumed by buffer 340, and the response time can be shortened by the amount of time consumed by buffer 340. In addition, compared with the case where the buffer is provided in two stages, a wider voltage range can be designed for the cathode potential Vs. This makes it possible to widen the dynamic range by the widened voltage range.

[0216] Figure 30 is a timing diagram showing an operation example of the monitoring pixel 401 and the control section 500 according to the second embodiment of the present technology.

[0217] In the time period from time T1 immediately after the recharge to time T12 after the delay time has elapsed, the time detection circuit 320 delays the inverted signal and outputs a high-level delayed signal SW'. In addition, in the time period from time T12 to time T2 of the next recharge, the time detection circuit 320 delays the inverted signal and outputs a low-level delayed signal SW'.

[0218] The sample and hold circuit 330 samples the cathode potential Vs in the case of the high-level delayed signal SW'. During this high level period, the cathode potential Vs decreases, and this change in the cathode potential Vs is tracked. On the other hand, in the case of the low-level delayed signal SW', the sample and hold circuit 330 holds the cathode potential Vs. The delayed signal SW' falls at time T12. Therefore, the potential at time T12 is held in a manner similar to the first embodiment.

[0219] Note that the first to fifth modifications of the first embodiment are applicable to the second embodiment.

[0220] As described above, in the second embodiment of the present technology, buffer 340 is omitted. Therefore, compared with the case where the buffer is provided in two stages, the power consumption can be reduced and the response time can be shortened.

[0221] "Modification"

[0222] In the second embodiment described above, the buffer 350 outputs a single-ended signal. However, if the number of monitoring pixels 401 increases, and thus the signal lines for transmitting the single-ended signal have a longer wire length, the wiring resistance increases. This may result in insufficient driving force of the buffer 350. The modified buffer 350 according to the second embodiment is different from the buffer 350 according to the first embodiment in that the modified buffer 350 outputs a differential signal.

[0223] Figure 31 FIG. is a circuit diagram showing a configuration example of a modified monitoring pixel 401 according to the second embodiment of the present technology. In the modified monitoring pixel 401 according to the second embodiment, the time detection circuit 320 further includes a D flip-flop 322.

[0224] The delayed signal from the delay circuit 371 is input to the clock terminal of the flip-flop 322. In addition, the inverted signal of the control signal RCH is input to the set terminal of the flip-flop 322, and a low level is input to the reset terminal. The output terminal of the flip-flop 322 is connected to the sampling switch 331 and the buffer 350.

[0225] Figure 32 FIG. is a circuit diagram showing a configuration example of a modified buffer 350 according to the second embodiment of the present technology. The modified buffer 350 according to the second embodiment is different from the buffer 350 according to the second embodiment in that the modified buffer 350 further includes a current source 361 and pMOS transistors 362 and 363.

[0226] The current source 361 and the pMOS transistors 362 and 363 are connected in series between the power supply potential and the ground potential. In addition, the gates of the pMOS transistors 356 and 362 are commonly connected to the time detection circuit 320. In addition, the gate of the pMOS transistor 357 is connected to the sampling switch 331, and the gate of the pMOS transistor 363 is connected to the ground potential.

[0227] The connection node between the pMOS transistors 356 and 357 and the connection node between the pMOS transistors 362 and 363 are connected to the control section 500 via signal lines 358 and 359.

[0228] Figure 32 The configuration shown in FIG. allows the buffer 350 to generate a differential signal based on the holding potential Vs_SH and output the generated differential signal to the control section 500.

[0229] As described above, according to the modification of the second embodiment of the present technology, the buffer 350 outputs a differential signal. This makes it possible to obtain a more accurate output value than in the case of outputting a single-ended signal.

[0230] <3. Application Example of a Moving Object>

[0231] The technology (this technology) according to an embodiment of the present disclosure can be applied to various products. For example, the technology according to an embodiment of the present disclosure can be implemented as a device installed on any type of moving object, such as a vehicle, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility device, an aircraft, a drone, a ship, or a robot.

[0232] Figure 33 is a block diagram showing an example of a schematic configuration of a vehicle control system, which is an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0233] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In Figure 33 the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and a vehicle-mounted network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0234] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device to control: a driving force generation device for generating the driving force of the vehicle, such as an internal combustion engine, a drive motor, etc., a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle, etc.

[0235] The body system control unit 12020 controls the operation of various types of devices configured in the body according to various programs. For example, the body system control unit 12020 serves as a control device to control the following: a keyless entry system, a smart key system, an electric window device, or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, the body system control unit 12020 can receive radio waves transmitted from a mobile device serving as an alternative key or signals from various switches as inputs. The body system control unit 12020 receives these input radio waves or signals to control the vehicle's door lock device, electric window device, lights, etc.

[0236] The vehicle exterior information detection unit 12030 detects information about the exterior of a vehicle equipped with a vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image an image of the vehicle exterior and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing for detecting objects (such as people, vehicles, obstacles, signs, symbols, etc. on the road surface), or perform processing for detecting the distance to the detected object.

[0237] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of the received light. The imaging unit 12031 can output an electrical signal as an image, or can output an electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared light.

[0238] The vehicle interior information detection unit 12040 detects information about the interior of the vehicle. The vehicle interior information detection unit 12040 may be connected to a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 can calculate the degree of fatigue of the driver or the degree of concentration of the driver's attention, or can determine whether the driver is dozing off.

[0239] The microcomputer 12051 can calculate control target values for a driving force generation device, a steering mechanism, or a braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for implementing functions of an advanced driver assistance system (ADAS), which includes collision avoidance or impact buffering for the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, alarms for vehicle collisions, alarms for vehicle lane departure, etc.

[0240] In addition, the microcomputer 12051 can perform cooperative control for automatic driving, etc. that does not depend on the driver's operation by controlling a driving force generation device, a steering mechanism, a braking device, etc. based on information about the exterior or interior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040.

[0241] In addition, the microcomputer 12051 can output a control command to the vehicle body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamp based on the position of the vehicle ahead or the oncoming vehicle detected by the vehicle outside information detection unit 12030, changing it from high beam to low beam, thereby performing cooperative control to prevent (reduce) glare.

[0242] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can notify information visually or auditorily to the passengers of the vehicle or the outside of the vehicle. In Figure 33 the example, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0243] Figure 34 is a diagram showing an example of the installation position of the imaging unit 12031.

[0244] In Figure 34 the example, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0245] The imaging units 12101, 12102, 12103, 12104, and 12105 can be arranged at positions such as the front nose of the vehicle 12100, the side mirror, the rear bumper, the rear door, and the upper part of the windshield inside the vehicle. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper part of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirror mainly obtain images on the side of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or the rear door mainly obtains images behind the vehicle 12100. The imaging unit 12105 arranged at the upper part of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0246] Incidentally, Figure 34An example of the shooting ranges of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 arranged at the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of imaging units 12102 and 12103 arranged at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104 arranged at the rear bumper or the rear door. For example, a bird's-eye view image of vehicle 12100 observed from above can be obtained by superimposing the image data imaged by imaging units 12101 to 12104.

[0247] At least one of imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of imaging units 12101 to 12104 can be a stereo camera composed of a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0248] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change of this distance (relative speed with respect to vehicle 12100) based on the distance information obtained from imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the preceding vehicle, which specifically exists on the driving path of vehicle 12100 and travels in substantially the same direction as vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). In addition, microcomputer 12051 can preset the following distance to be maintained from the preceding vehicle, and execute automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, cooperative control such as autonomous driving that does not depend on the driver's operation can be executed.

[0249] For example, the microcomputer 12051 can classify three-dimensional object data regarding a three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 discriminates whether an obstacle around the vehicle 12100 is an obstacle that can be visually recognized by the driver of the vehicle 12100 or an obstacle that is difficult to be visually recognized by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk, which indicates the risk of collision with each obstacle. When there is a possibility of collision where the collision risk is equal to or higher than a set value, the microcomputer 12051 outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid a collision.

[0250] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is performed by, for example, a program for extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras, and a program for determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the object contour. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus recognizes the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a square contour line superimposed on the recognized pedestrian to emphasize the recognized pedestrian. The sound / image output unit 12052 may also control the display unit 12062 to display an icon or the like representing the pedestrian at a desired position.

[0251] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been explained above. The technology according to an embodiment of the present disclosure can be applied to, for example, the out-vehicle information detection unit 12030 in the above configuration. Specifically, the Figure 1 ranging module 100 can be applied to the out-vehicle information detection unit 12030. Applying the technology according to an embodiment of the present disclosure to the out-vehicle information detection unit 12030 enables suppression of changes in excessive bias caused by a decrease or increase in the amount of light and acquisition of accurate distance information.

[0252] Note that the above embodiments are merely examples embodying the present technology, and the matters in the embodiments have a corresponding relationship with the corresponding technical specified matters in the claims. Similarly, the technical specified matters in the claims have a corresponding relationship with the corresponding matters in the embodiments of the present technology, and these matters have the same name as the technical specified matters in the claims. However, the present technology is not limited to the embodiments, and various modifications can be made to the embodiments without departing from the gist of the present technology to embody it.

[0253] Note that the effects described in this specification are merely illustrative, and the present technology is not limited thereto. In addition, there may be other effects.

[0254] Note that the present technology can also be configured as follows.

[0255] (1) A solid-state image sensor, comprising:

[0256] A photoelectric conversion element including an anode and a cathode, one of the anode and the cathode being connected to a predetermined node;

[0257] A potential supply element configured to supply a first potential to the predetermined node;

[0258] A time detection circuit configured to detect the time when a predetermined period of time has elapsed since the potential of the predetermined node starts to increase or decrease from the first potential;

[0259] A sample and hold circuit configured to capture the potential of the predetermined node based on an output from the time detection circuit and hold the potential as a second potential; and

[0260] A control section configured to control the potential of the other of the anode and the cathode based on the second potential.

[0261] (2) The solid-state image sensor according to (1),

[0262] wherein the time detection circuit includes an inverter configured to invert a signal of the potential of the predetermined node and output an inverted signal.

[0263] (3) The solid-state image sensor according to one or more of (1) to (2), wherein the time detection circuit further includes a pulse signal generation circuit configured to generate a pulse signal based on a signal obtained by delaying the inverted signal by a predetermined delay time, and

[0264] the sample and hold circuit captures the potential of the predetermined node within a period of the pulse width of the pulse signal.

[0265] (4) A solid-state image sensor according to one or more of (1) to (3), wherein the time detection circuit further includes a delay circuit configured to delay the inverted signal by a predetermined delay time and output a delayed signal, and the sample-and-hold circuit captures the potential of the predetermined node when the delayed signal is one of two different values, and holds the captured potential when the delayed signal is the other of the two values.

[0266] (5) A solid-state image sensor according to one or more of (1) to (4), wherein the photoelectric conversion element, the time detection circuit, and the sample-and-hold circuit are mounted in pixels, and the mounting is performed with respect to a plurality of pixels, and

[0267] the control section includes

[0268] an inter-pixel average acquisition section configured to calculate an average value of the respective second potentials of a plurality of pixels as an inter-pixel average value, and

[0269] a time average acquisition section configured to calculate a time average value of the inter-pixel average value, and

[0270] a potential control section configured to control the potential of the other of the anode and the cathode such that the potential becomes lower as the time average value becomes higher.

[0271] (6) A solid-state image sensor according to one or more of (1) to (5),

[0272] wherein the time average acquisition section includes an analog filter configured to generate the time average value.

[0273] (7) A solid-state image sensor according to one or more of (1) to (6), wherein the time average acquisition section includes a digital filter configured to generate a time average value.

[0274] (8) A solid-state image sensor according to one or more of (1) to (7),

[0275] wherein the potential control section includes an amplifier configured to compare the time average value with a predetermined power supply potential and output the comparison result to the other of the anode and the cathode.

[0276] (9) A solid-state image sensor according to one or more of (1) to (8),

[0277] Among them, the potential control part includes a power semiconductor, and the power semiconductor is configured to control the potential of the other one of the anode and the cathode in such a way that the potential becomes lower as the time-averaged value of the potential becomes higher.

[0278] (10) The solid-state image sensor according to one or more of (1) to (9),

[0279] Among them, the inter-pixel average acquisition part includes

[0280] a capacitor; and

[0281] a plurality of resistors, and the plurality of resistors are connected in parallel between the capacitor and the plurality of pixels.

[0282] (11) The solid-state image sensor according to one or more of (1) to (10),

[0283] Among them, the inter-pixel average acquisition part includes:

[0284] an analog-to-digital conversion part, and the analog-to-digital conversion part is configured to convert a second potential into a digital signal; and

[0285] an average filter, and the average filter is configured to calculate the average value of the digital signal as the inter-pixel average value.

[0286] (12) The solid-state image sensor according to one or more of (1) to (11),

[0287] Among them, the analog-to-digital conversion part includes a plurality of analog-to-digital converters, and the analog-to-digital converters are configured to convert the second potentials of different pixels into digital signals.

[0288] (13) The solid-state image sensor according to one or more of (1) to (12),

[0289] Among them, the analog-to-digital conversion part includes:

[0290] a selector, and the selector is configured to select any one of the corresponding second potentials of the plurality of pixels,

[0291] an analog-to-digital converter, and the analog-to-digital converter is configured to convert the selected second potential into a digital signal.

[0292] (14) The solid-state image sensor according to one or more of (1) to (13) further includes:

[0293] an output-side buffer, and the output-side buffer is inserted between the sampling and holding circuit and the control part.

[0294] A solid-state image sensor according to one or more of (1) to (14)

[0295] Wherein, the output-side buffer generates a differential signal based on the second potential and outputs the generated differential signal.

[0296] (16) A solid-state image sensor according to one or more of (1) to (15), further comprising:

[0297] An input-side buffer inserted between the predetermined node and the sample-and-hold circuit.

[0298] (17) A solid-state image sensor according to one or more of (1) to (16)

[0299] Wherein, the input-side buffer generates a differential signal based on the second potential and outputs the generated differential signal.

[0300] (18) A solid-state image sensor according to one or more of (1) to (17), wherein

[0301] The photoelectric conversion element and the potential supply element are installed in each of the imaging pixel circuit and the monitoring pixel circuit surrounding the imaging pixel circuit, and

[0302] The time detection circuit and the sample-and-hold circuit are installed in the monitoring pixel circuit.

[0303] (19) A solid-state image sensor according to one or more of (1) to (18), wherein

[0304] The cathode is connected to a predetermined node, and

[0305] The control section controls the potential of the anode.

[0306] (20) A solid-state image sensor according to one or more of (1) to (19), wherein

[0307] The anode is connected to the predetermined node, and

[0308] The control section controls the potential of the cathode.

[0309] (21) A ranging system, comprising:

[0310] A light-emitting part configured to provide illumination light; and

[0311] Solid-state image sensor, the solid-state image sensor comprising: a photoelectric conversion element including an anode and a cathode, one of the anode and the cathode being connected to a predetermined node; a potential supply element configured to supply a first potential to the predetermined node; a time detection circuit configured to detect the time when a predetermined period of time has elapsed since the potential of the predetermined node starts to increase or decrease from the first potential; a sampling and holding circuit configured to capture the potential of the predetermined node based on an output from the time detection circuit and hold the potential as a second potential; a control section configured to control the potential of the other of the anode and the cathode based on the second potential; and a ranging section configured to measure a distance based on a round-trip time between a light emission time of irradiated light and a light reception time of reflected light corresponding to the irradiated light.

[0312] (22) An optical detection device, comprising:

[0313] A first pixel circuit including a first avalanche photodiode;

[0314] A second pixel circuit, the second pixel circuit including:

[0315] A second avalanche photodiode;

[0316] A first delay circuit including an input coupled to the cathode of the second avalanche photodiode;

[0317] A first circuit including a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to the output of the first delay circuit; and

[0318] A control circuit coupled to the output of the first circuit and configured to control the potential of the anode of the first avalanche photodiode based on the output of the first circuit.

[0319] (23) The optical detection device according to (22), wherein the control circuit is configured to control the potential of the anode of the second avalanche photodiode based on the output of the first circuit.

[0320] (24) The optical detection device according to one or more of (22) to (23), further comprising:

[0321] A third pixel circuit, including:

[0322] A third avalanche photodiode;

[0323] A second delay circuit including an input of a potential coupled to the cathode of the third avalanche photodiode; and

[0324] A second circuit, the second circuit including a third input coupled to the cathode of a third avalanche photodiode and a fourth input coupled to the output of a second delay circuit.

[0325] (25) The optical detection device according to one or more of (22) to (24), wherein the control circuit includes an averaging circuit, the averaging circuit being coupled to the outputs of the first circuit and the second circuit and configured to average the outputs of the first circuit and the second circuit to output an inter-pixel average signal.

[0326] (26) The optical detection device according to one or more of (22) to (25), wherein the control circuit includes a time averaging circuit, the time averaging circuit including an input coupled to the output of the averaging circuit and configured to output a time average signal based on the inter-pixel average signal.

[0327] (27) The optical detection device according to one or more of (22) to (26), wherein the control circuit includes a potential controller coupled to the anode of the first avalanche photodiode.

[0328] (28) The optical detection device according to one or more of (22) to (27), wherein the potential controller is configured to control the potential of the anode of the first avalanche photodiode to be lower when the time average signal rises, and wherein the potential controller is configured to control the potential of the anode of the first avalanche photodiode to be higher when the time average signal falls.

[0329] (29) The optical detection device according to one or more of (22) to (28), the control circuit including an analog-to-digital converter configured to convert the time average signal into a digital signal, and wherein the potential controller includes a power electronic device configured to control the potential of the anode of the first avalanche photodiode based on the digital signal.

[0330] (30) The optical detection device according to one or more of (22) to (29), wherein the averaging circuit includes a capacitor, a first resistor coupled between the capacitor and the first delay circuit, and a second resistor coupled between the capacitor and the second delay circuit.

[0331] (31) The optical detection device according to one or more of (22) to (30), wherein the first circuit includes a holding circuit, the holding circuit including a switch and a capacitor.

[0332] A light detection device according to one or more of (22) to (31), wherein the first circuit includes a first buffer circuit and a second buffer circuit, wherein the first buffer circuit is coupled between the cathode of the second avalanche photodiode and the holding circuit, and wherein the holding circuit is coupled between the first buffer circuit and the second buffer circuit.

[0333] (33) A light detection device according to one or more of (22) to (32), wherein the first buffer circuit is configured to buffer the potential of the cathode of the second avalanche photodiode to output a first pair of differential signals including a first positive signal and a first negative signal, wherein the holding circuit is configured to output the first positive signal according to a first delay signal, and wherein the second buffer circuit is configured to buffer the first negative signal and the first positive signal to output a second pair of differential signals including a second positive signal and a second negative signal.

[0334] (34) A light detection device according to one or more of (22) to (33), wherein the control circuit includes an averaging circuit, and the averaging circuit includes:

[0335] An analog-to-digital converter (ADC), the analog-to-digital converter including a first input configured to receive the second positive signal, a second input configured to receive the second negative signal, and an output configured to output a digital signal based on the second positive signal and the second negative signal;

[0336] A first capacitor coupled to the first input of the ADC; and

[0337] A second capacitor coupled to the second input of the ADC.

[0338] (35) A light detection device according to one or more of (22) to (34), wherein the first buffer circuit includes a first current source and a first transistor coupled to the first current source, and a second current source and a second transistor coupled to the second current source.

[0339] (36) A light detection device according to one or more of (22) to (35), wherein the first transistor is coupled to a node configured to receive the potential of the cathode of the second avalanche photodiode and is configured to output a first positive signal according to the current from the first current source, and wherein the second transistor is coupled to a node configured to receive a ground signal and is configured to output a first negative signal according to the current from the second current source.

[0340] (37) A light detection device according to one or more of (22) to (36), wherein the second buffer circuit includes a third current source and a third transistor coupled to the third current source, and a fourth current source and a fourth transistor coupled to the fourth current source.

[0341] (38) A light detection device according to one or more of (22) to (37), wherein the third transistor is configured to receive a first positive signal and output a second positive signal according to a current from the third current source, and wherein the fourth transistor is configured to receive a first negative signal and output a second negative signal according to a current from the fourth current source.

[0342] (39) A light detection device, comprising:

[0343] A first pixel circuit, the first pixel circuit including a first avalanche photodiode;

[0344] A second pixel circuit, comprising:

[0345] A second avalanche photodiode;

[0346] A first delay circuit, the first delay circuit being configured to generate a first delay signal based on a first potential of the cathode of the second avalanche photodiode; and

[0347] A first circuit, the first circuit being configured to sample a second potential of the cathode of the second avalanche photodiode and output the sampled second potential based on the first delay signal; and

[0348] A control circuit, the control circuit being configured to control the potential of the anode of the first avalanche photodiode based on the sampled second potential output by the first circuit.

[0349] (40) A system, comprising:

[0350] A light source; and

[0351] A light detection device, comprising:

[0352] A first pixel circuit, the first pixel circuit including a first avalanche photodiode;

[0353] A second pixel circuit, the second pixel circuit comprising:

[0354] A second avalanche photodiode;

[0355] A first delay circuit, the first delay circuit including an input coupled to the cathode of the second avalanche photodiode;

[0356] A first circuit, the first circuit including a first input coupled to the cathode of a second avalanche photodiode and a second input coupled to the output of a first delay circuit; and a control circuit, the control circuit being coupled to the output of the first circuit and configured to control the potential of the anode of the first avalanche photodiode based on the output of the first circuit.

[0357] (41) An optical detection device, comprising:

[0358] A first pixel circuit, the first pixel circuit including a first avalanche photodiode;

[0359] A second pixel circuit, the second pixel circuit including:

[0360] A second avalanche photodiode;

[0361] A first delay circuit, the first delay circuit including an input coupled to the anode of the second avalanche photodiode;

[0362] A first circuit, the first circuit including a first input coupled to the anode of the second avalanche photodiode and a second input coupled to the output of the first delay circuit; and

[0363] A control circuit, the control circuit being coupled to the output of the first circuit and configured to control the potential of the cathode of the first avalanche photodiode based on the output of the first circuit.

[0364] Those skilled in the art should understand that various modifications, combinations, sub - combinations and alterations can be made according to design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

[0365] List of reference numerals

[0366] 100 Rangefinding module

[0367] 110 Light - emitting part

[0368] 120 Synchronization control part

[0369] 200 Solid - state image sensor

[0370] 201 Pixel chip

[0371] 202 Circuit chip

[0372] 210 Light - receiving part

[0373] 211, 212 Photoelectric conversion elements

[0374] 220 Time - generation part

[0375] 231 and 232 Multiplexers

[0376] 241 and 242 Time-to-Digital Converters

[0377] 250 Histogram Generation Section

[0378] 260 Output Interface

[0379] 300 Circuit Block

[0380] 310 Monitoring Pixel Circuit

[0381] 311, 342, 344, 356, 357, 362, 363, 373, 381 pMOS Transistors

[0382] 320 Time Detection Circuit

[0383] 321, 376, 379, 382 Inverters

[0384] 322 Flip-Flop

[0385] 330 Sample-and-Hold Circuit

[0386] 331 Sampling Switch

[0387] 332, 375, 512, 518, 519 Capacitors

[0388] 340 and 350 Buffers

[0389] 341, 343, 352, 354, 355, 361, 372 Current Sources

[0390] 370 Pulse Generation Circuit

[0391] 371 and 377 Delay Circuits

[0392] 351, 353, 374 nMOS Transistors

[0393] 378 NAND Gate

[0394] 380 Imaging Pixel Circuit

[0395] 400 Pixel Array Section

[0396] 401 Monitoring Pixel

[0397] 402 Imaging Pixel

[0398] 500 Control Section

[0399] 510 Inter-Pixel Average Acquisition Section

[0400] 511 Resistor

[0401] 513 Analog-to-digital conversion section

[0402] 514, 517, 523, 532 ADC

[0403] 515 Average filter

[0404] 516 Selector

[0405] 520 Time-average acquisition section

[0406] 521 Variable resistor

[0407] 522 Variable capacitor

[0408] 524 Digital low-pass filter

[0409] 530 Electric potential control section

[0410] 531 Amplifier

[0411] 533 Power IC

[0412] 12031 Imaging unit.

Claims

1. A light detection device, comprising: a first pixel circuit including a first avalanche photodiode; a second pixel circuit including: a second avalanche photodiode; a first delay circuit including an input coupled to the cathode of the second avalanche photodiode, the first delay circuit being configured to detect a timing at which a predetermined period of time has elapsed since the cathode potential of the second avalanche photodiode began to decrease from a power supply potential; a first circuit including a first input coupled to the cathode of the second avalanche photodiode, a second input coupled to the output of the first delay circuit, and a holding circuit including a switch and a capacitor, the first circuit being configured to acquire the cathode potential of the second avalanche photodiode based on the timing detected by the first delay circuit and hold it as a holding potential; and a control circuit including: a time averaging circuit including an input coupled to the output of the first circuit, and the time averaging circuit being configured to output a time average signal based on the output of the first circuit; and a potential controller coupled to the anode of the first avalanche photodiode, the potential controller being configured to control the potential of the anode of the first avalanche photodiode to decrease as the time average signal rises, and being configured to control the potential of the anode of the first avalanche photodiode to increase as the time average signal falls.

2. The light detection device according to claim 1, wherein, the control circuit is configured to control the potential of the anode of the second avalanche photodiode based on the output of the first circuit.

3. The light detection device according to claim 1, further comprising: a third pixel circuit including: a third avalanche photodiode; a second delay circuit including an input coupled to the potential of the cathode of the third avalanche photodiode; and a second circuit including a third input coupled to the cathode of the third avalanche photodiode and a fourth input coupled to the output of the second delay circuit.

4. The light detection device according to claim 3, wherein, the control circuit includes an averaging circuit coupled to the output of the first circuit and the output of the second circuit, and the averaging circuit is configured to average the outputs of the first circuit and the second circuit to output an inter-pixel average signal.

5. The light detection device according to claim 4, wherein, the control circuit includes a time averaging circuit including an input coupled to the output of the averaging circuit, and the time averaging circuit is configured to output a time average signal based on the inter-pixel average signal.

6. The light detection device according to claim 5, wherein, the control circuit includes a potential controller coupled to the anode of the first avalanche photodiode.

7. The light detection device according to claim 6, wherein, The potential controller is configured to control the potential of the anode of the first avalanche photodiode to decrease when the time-averaged signal rises, and wherein the potential controller is configured to control the potential of the anode of the first avalanche photodiode to increase when the time-averaged signal falls.

8. The optical detection device according to claim 6, wherein, the control circuit includes an analog-to-digital converter configured to convert the time-averaged signal into a digital signal, and wherein the potential controller includes a power electronic device configured to control the potential of the anode of the first avalanche photodiode based on the digital signal.

9. The optical detection device according to claim 6, wherein, the averaging circuit includes a capacitor, a first resistor coupled between the capacitor and the first delay circuit, and a second resistor coupled between the capacitor and the second delay circuit.

10. The optical detection device according to claim 1, wherein, the first circuit includes a first buffer circuit and a second buffer circuit, wherein the first buffer circuit is coupled between the cathode of the second avalanche photodiode and the holding circuit, and wherein the holding circuit is coupled between the first buffer circuit and the second buffer circuit.

11. The optical detection device according to claim 10, wherein, the first buffer circuit is configured to buffer the potential of the cathode of the second avalanche photodiode to output a first pair of differential signals including a first positive signal and a first negative signal, wherein the holding circuit is configured to output the first positive signal according to a first delay signal, and wherein the second buffer circuit is configured to buffer the first negative signal and the first positive signal to output a second pair of differential signals including a second positive signal and a second negative signal.

12. The optical detection device according to claim 11, wherein, the control circuit includes an averaging circuit, and the averaging circuit includes: an analog-to-digital converter ADC including a first input configured to receive the second positive signal, a second input configured to receive the second negative signal, and an output configured to output a digital signal based on the second positive signal and the second negative signal; a first capacitor coupled to the first input of the ADC; and a second capacitor coupled to the second input of the ADC.

13. The optical detection device according to claim 11, wherein, the first buffer circuit includes a first current source and a first transistor coupled to the first current source, and a second current source and a second transistor coupled to the second current source.

14. The optical detection device according to claim 13, wherein, The first transistor is coupled to a node configured to receive the potential of the cathode of the second avalanche photodiode, and the first transistor is configured to output the first positive signal according to the current from the first current source, and wherein, the second transistor is coupled to a node configured to receive a ground signal, and the second transistor is configured to output the first negative signal according to the current from the second current source.

15. The optical detection device according to claim 13, wherein, the second buffer circuit includes a third current source and a third transistor coupled to the third current source, and a fourth current source and a fourth transistor coupled to the fourth current source.

16. The optical detection device according to claim 15, wherein, the third transistor is configured to receive the first positive signal and output the second positive signal according to the current from the third current source, and wherein, the fourth transistor is configured to receive the first negative signal and output the second negative signal according to the current from the fourth current source.

17. An optical detection device, comprising: a first pixel circuit including a first avalanche photodiode; a second pixel circuit including: a second avalanche photodiode; a first delay circuit configured to generate a first delay signal based on a first potential of the cathode of the second avalanche photodiode, the first delay circuit being configured to detect a timing at which a predetermined period of time has elapsed since the cathode potential of the second avalanche photodiode began to decrease from a power supply potential; and a first circuit configured to sample a second potential of the cathode of the second avalanche photodiode and output the sampled second potential based on the first delay signal, the first circuit including a holding circuit, the holding circuit including a switch and a capacitor, the first circuit being configured to obtain the sampled second potential of the second avalanche photodiode and hold it as a holding potential based on the timing detected by the first delay circuit; and a control circuit including: a time averaging circuit configured to output a time averaging signal based on the sampled second potential output by the first circuit; and a potential controller coupled to the anode of the first avalanche photodiode, the potential controller being configured to control the potential of the anode of the first avalanche photodiode to decrease as the time averaging signal rises, and being configured to control the potential of the anode of the first avalanche photodiode to increase as the time averaging signal falls.

18. A system for measuring the distance to an object, comprising: a light source; and an optical detection device including: a first pixel circuit including a first avalanche photodiode; a second pixel circuit including: a second avalanche photodiode; a first delay circuit including an input coupled to the cathode of the second avalanche photodiode, the first delay circuit being configured to detect a timing at which a predetermined period of time has elapsed since the cathode potential of the second avalanche photodiode began to decrease from a power supply potential; A first circuit, comprising a first input coupled to the cathode of the second avalanche photodiode, a second input coupled to the output of the first delay circuit, and a holding circuit comprising a switch and a capacitor, the first circuit being configured to acquire the cathode potential of the second avalanche photodiode based on the timing detected by the first delay circuit and hold it as a holding potential; and A control circuit, comprising: A time averaging circuit, comprising an input coupled to the output of the first circuit, and the time averaging circuit being configured to output a time averaged signal based on the output of the first circuit; and A potential controller, coupled to the anode of the first avalanche photodiode, the potential controller being configured to control the potential of the anode of the first avalanche photodiode to decrease as the time averaged signal rises, and being configured to control the potential of the anode of the first avalanche photodiode to increase as the time averaged signal falls.

19. An optical detection device, comprising: A first pixel circuit, comprising a first avalanche photodiode; A second pixel circuit, comprising: A second avalanche photodiode; A first delay circuit, comprising an input coupled to the anode of the second avalanche photodiode, the first delay circuit being configured to detect the timing at which a predetermined period of time has elapsed since the anode potential of the second avalanche photodiode began to decrease from the supply potential; A first circuit, comprising a first input coupled to the anode of the second avalanche photodiode, a second input coupled to the output of the first delay circuit, and a holding circuit comprising a switch and a capacitor, the first circuit being configured to acquire the anode potential of the second avalanche photodiode based on the timing detected by the first delay circuit and hold it as a holding potential; and A control circuit, comprising: A time averaging circuit, comprising an input coupled to the output of the first circuit, and the time averaging circuit being configured to output a time averaged signal based on the output of the first circuit; and A potential controller, coupled to the cathode of the first avalanche photodiode, the potential controller being configured to control the potential of the cathode of the first avalanche photodiode to increase as the time averaged signal rises, and being configured to control the potential of the cathode of the first avalanche photodiode to decrease as the time averaged signal falls.

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