A gate oxide reinforcement method for improving the total dose resistance of MOS devices

Abstract

The present invention discloses a gate oxide reinforcement method for improving the total dose resistance of MOS devices, and belongs to the field of microelectronic process manufacturing. The present invention adopts a special CVD or ALD deposition method, and the deposition temperature is less than 800 degrees Celsius to prepare a high-quality gate oxide layer SiO2 medium of the MOS device; before CVD or ALD deposition of the gate oxide layer of the MOS device, the traditional hot gate oxide process is used to grow SiO2 with a thickness less than #imgabs0# on the surface of the silicon substrate, thereby reducing the interface state density and improving the device parameter stability. The present invention can reduce the thermal budget in the manufacturing process of the device gate oxide layer SiO2, increase the boron doping concentration of P-type Si at the interface of the STI isolation region, and improve the device's total ionizing dose radiation resistance, without increasing the number of photolithography times and the manufacturing cost.

Description

Technical Field

[0001] The invention relates to the technical field of microelectronic process manufacturing, and in particular to a gate oxide reinforcement method for improving the total dose resistance capability of MOS devices. Background Art

[0002] MOS devices are the basic components of modern large-scale integrated circuits. They are mainly divided into N-type MOS devices and P-type MOS devices. The carriers of N-type MOS devices are electrons, and the carriers of P-type MOS devices are holes. In integrated circuits, N-type MOS devices and P-type MOS devices are often combined to design the structure of inverters, registers, and SRAM storage units.

[0003] When MOS devices work in an ionizing radiation environment, the SiO 2 The isolation medium will be ionized to form electron-hole pairs. The electrons will quickly leave the medium area under the action of the electric field. At the same time, the holes generated have a large mass, move slowly, and are easily captured by traps in the medium to form a fixed positive charge center. As the total dose of ionizing radiation increases, SiO 2 The more positive charges are trapped in the medium, the more positive charges it will eventually carry, which will cause the SiO 2 The P-type Si in contact is prone to depletion and inversion. 2 The surface area of ​​the NMOS transistor forms an N-type conductive channel. The leakage between the source and drain electrodes of the NMOS tube increases, and the drain electrode of the NMOS tube is conductive with the body electrode of the PMOS tube, which leads to an increase in the off-state current of the NMOS device, thereby increasing the power consumption of the integrated circuit or even causing failure. In an ionizing radiation environment, the main failure phenomena of MOS devices are: threshold voltage drift, increased off-state leakage, etc. The main reason for the threshold voltage drift is the accumulation of positive charge in the gate oxide dielectric, which leads to a decrease in the threshold voltage of the NMOS device and an increase in the threshold voltage of the PMOS device. The main reason for the increase in the off-state leakage is the SiO 2 The dielectric accumulates a large amount of positive charge, causing the P-type silicon in the STI isolation region to be depleted and inverted, resulting in the drain of the NMOS device flowing to the source and the body electrode of the PMOS device when the gate electrode is turned off, generating off-state leakage current.

[0004] As the gate oxide thickness of MOS devices decreases (<20nm), the positive charge accumulated in the gate oxide layer under ionizing radiation is very small and can be ignored, which means that the threshold voltage drift of the device is small. 2The dielectric is thicker than 400nm, so the positive charge accumulated in this area cannot be ignored. Without reinforcement, a total radiation dose of 50Krad (Si) can cause the source and drain electrodes of the NMOS device to conduct through. Therefore, radiation reinforcement of the STI isolation area is the focus.

[0005] At present, the radiation hardening methods of STI isolation area mainly include:

[0006] (1) Modify the STI isolation region dielectric to increase the electron traps of the dielectric material, capture more electrons to neutralize the positive charge brought by the holes, and reduce the positive charge accumulation of the STI isolation region material after ionizing radiation. However, this involves material modification and the compatibility of the modified material with the CMOS process, which is difficult.

[0007] (2) Increasing the boron doping concentration of P-type silicon at the isolation region interface, increasing the inversion voltage, and reducing the positive charge concentration in the STI isolation region.

[0008] The P-type silicon doping concentration at the STI isolation region interface is affected by the well implant concentration and the total thermal budget during device manufacturing. The boron concentration in the P-type silicon at the interface will be 2 During the growth process (high temperature, >800℃), the dielectric SiO 2 Due to the boron absorption and phosphorus removal effect, the boron concentration decreases with the increase of thermal budget in the device manufacturing process, making leakage more likely to occur in an ionizing radiation environment. Summary of the invention

[0009] The object of the present invention is to provide a gate oxide reinforcement method for improving the total dose resistance capability of MOS devices, so as to solve the problems in the background technology.

[0010] In order to solve the above technical problems, the present invention provides a gate oxide reinforcement method for improving the total dose resistance of MOS devices, comprising:

[0011] Providing a substrate, and sequentially forming a buffer oxide layer and an active area photolithography mask layer on the surface of the substrate;

[0012] Etching the active area to form an STI isolation groove; depositing an STI isolation medium on the surface of the mask layer and in the STI isolation groove;

[0013] Perform CMP grinding on the STI isolation medium, remove the masking layer, and perform P-well impurity implantation to form a low-voltage P-well and a high-voltage P-well;

[0014] The surface of the low-voltage P-well and high-voltage P-well is processed, and SiO2 is deposited on the high-voltage MOS device by CVD or ALD method. 2 Gate oxide layer;

[0015] Removal of SiO in low voltage NMOS area2 Gate oxide layer, exposing the substrate; SiO is deposited by CVD or ALD 2 Gate oxide layer; polysilicon is deposited on the entire surface;

[0016] Perform photolithography and etching to form a polycrystalline gate electrode of the MOS device, and perform LDD implantation; deposit the sidewall dielectric of the polycrystalline gate electrode for subsequent formation of source and drain electrodes;

[0017] Anisotropic etching method is adopted to form the gate electrode spacer sidewall; source and drain impurities are implanted to form the source and drain regions of the MOS device.

[0018] Optionally, the buffer oxide layer is SiO 2 , with a thickness of 50 to 200 nm; the masking layer is SiN, with a thickness of 50 to 200 nm.

[0019] Optionally, the STI isolation dielectric is SiO deposited by HDPCVD process. 2 , used as an isolation medium between MOS devices.

[0020] Optionally, the low-voltage P-well is formed by high-concentration boron implantation and is used to manufacture low-voltage NMOS devices; the high-voltage P-well is formed by low-concentration boron implantation and is used to manufacture high-voltage NMOS devices.

[0021] Optionally, processing the surface of the low-pressure P-well and the high-pressure P-well includes: growing a layer with a thickness of SiO 2 .

[0022] Optionally, deposit high voltage MOS device SiO 2 The temperature of the gate oxide layer is 300-800°C, and the thickness of the gate oxide layer is

[0023] Optionally, the thickness of the polysilicon is 100-300 nm.

[0024] Optionally, the thickness of the substrate is SEMI standard thickness.

[0025] In the gate oxide reinforcement method for improving the total dose resistance of MOS devices provided by the present invention, a special CVD or ALD deposition method is used, and the deposition temperature is less than 800 degrees Celsius to prepare a high-quality gate oxide layer SiO2 of the MOS device. 2 Before CVD or ALD deposition of the MOS device gate oxide layer, a conventional hot gate oxide process is used to grow a layer with a thickness less than The present invention can reduce the SiO2 of the gate oxide layer of the device, reduce the interface state density, and improve the stability of device parameters. 2The thermal budget in the manufacturing process increases the boron doping concentration of P-type Si at the interface of the STI isolation region, and improves the device's ability to resist total ionizing dose radiation without increasing the number of photolithography times and the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic flow chart of a gate oxide reinforcement method for improving the total dose resistance capability of a MOS device provided by the present invention;

[0027] Figure 2 is a schematic diagram of providing a substrate and growing a buffer oxide layer and a masking layer on the surface thereof;

[0028] Figure 3 It is a schematic diagram of etching the active area to form the STI isolation groove;

[0029] Figure 4 It is a schematic diagram of depositing STI isolation dielectric on the surface of the masking layer and in the STI isolation groove;

[0030] Figure 5 CMP grinding is performed on the STI isolation medium to remove excess SiO 2 Schematic diagram of the medium;

[0031] Figure 6 is a schematic diagram of removing the masking layer and performing P-well impurity injection;

[0032] Figure 7 is a schematic diagram of forming a low-pressure P-well f and a high-pressure P-well g;

[0033] Figure 8 Is the growth of SiO 2 Schematic diagram of surface treatment before gate oxide dielectric deposition for high voltage devices;

[0034] Fig. 9 It is the deposition of SiO2 for high voltage MOS devices. 2 Schematic diagram of the gate oxide layer;

[0035] Fig.10 Photolithography is used to remove SiO2 in the low voltage NMOS area. 2 Schematic diagram of

[0036] Fig.11 SiO is deposited by CVD or ALD 2 Schematic diagram of the gate oxide layer;

[0037] Fig.12 is a schematic diagram of depositing polysilicon on a surface;

[0038] Fig.13 It is a schematic diagram of forming a polycrystalline gate electrode of a MOS device and performing LDD implantation;

[0039] Fig.14 It is a schematic diagram of depositing a sidewall dielectric of a polycrystalline gate electrode;

[0040] Fig.15 It is a schematic diagram of forming a gate electrode spacer sidewall;

[0041] Fig.16 It is a schematic diagram of performing source-drain impurity implantation to form the source-drain region of a MOS device. DETAILED DESCRIPTION

[0042] The following is a further detailed description of a gate oxide reinforcement method for improving the total dose resistance of MOS devices proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] The present invention provides a gate oxide reinforcement method for improving the total dose resistance of MOS devices, the process of which is as follows: Figure 1 As shown, the specific process steps are as follows:

[0044] Step 1: If Figure 2 As shown, a bulk silicon, epitaxial material or SOI material substrate a is provided, and its thickness is the SEMI standard thickness; a buffer oxide layer b is grown on its surface, and a mask layer c for active area photolithography is deposited on the surface of the buffer oxide layer b;

[0045] The buffer oxide layer b is SiO 2 , with a thickness of 50 to 200 nm, and is used to reduce the stress of the lattice mismatch between the mask layer c and the substrate a; the mask layer c is SiN, with a thickness of 50 to 200 nm, and is used as an anti-reflection layer for photolithography and an endpoint signal for the subsequent CMP process;

[0046] Step 2: If Figure 3 As shown, active area etching is performed to form STI isolation grooves d;

[0047] Step 3: If Figure 4 As shown, an STI isolation dielectric e is deposited on the surface of the mask layer c and in the STI isolation groove d. The STI isolation dielectric e is SiO deposited by HDPCVD process. 2 , used as an isolation medium between MOS devices;

[0048] Step 4: If Figure 5 As shown, the STI isolation dielectric e is CMP polished to remove excess SiO 2 medium;

[0049] Step 5: If Figure 6 As shown, the masking layer c is removed, and P-well impurity injection is performed;

[0050] Step 6: Form Figure 7 The low-pressure P-well f and the high-pressure P-well g shown;

[0051] The low voltage P well f is formed by high concentration boron implantation and is used to manufacture low voltage NMOS devices; the high voltage P well g is formed by low concentration boron implantation and is used to manufacture high voltage NMOS devices;

[0052] Step 7: If Figure 8 As shown, the thermal oxidation method is used to grow the growth thickness SiO 2 h, used as surface treatment before gate oxide dielectric deposition of high voltage devices;

[0053] Step 8: If Fig. 9 As shown, the SiO2 layer of the high-voltage MOS device is deposited by CVD or ALD. 2 The gate oxide layer i has a deposition temperature of 300-800°C and a thickness of

[0054] Step 9: If Fig.10 As shown, photolithography etching is performed to remove the SiO2 in the low voltage NMOS area. 2 , exposing the substrate a.

[0055] Step 10: Fig.11 As shown, the thickness of the grown SiO 2 According to the gate oxide thickness requirements of low-voltage MOS devices, SiO2 is deposited by CVD or ALD to a specific thickness. 2 Gate oxide layer j;

[0056] Step 11: Fig.12 As shown, polysilicon k is deposited on the surface by CVD method with a thickness of 100 to 300 nm;

[0057] Step 12: Fig.13 As shown, photolithography etching is performed to form a polycrystalline gate electrode of a MOS device, and LDD implantation is performed;

[0058] Step 13: Fig.14 As shown, a sidewall dielectric l of a polycrystalline gate electrode is deposited for subsequent formation of a source electrode and a drain electrode;

[0059] Step 14: Fig.15 As shown, an anisotropic etching method is used to form a gate electrode Spacer sidewall;

[0060] Step 15: Fig.16As shown, source and drain impurities are implanted, and high-concentration P or As is implanted to form source and drain regions m of the MOS device, namely, N-type heavily doped source electrodes and drain electrodes.

[0061] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A gate oxide reinforcement method for improving the total dose resistance of a MOS device, characterized in that: include: Providing a substrate, and sequentially forming a buffer oxide layer and an active area photolithography mask layer on the surface of the substrate; Etching the active area to form STI isolation grooves; Depositing an STI isolation dielectric on the surface of the masking layer and in the STI isolation trench; Perform CMP grinding on the STI isolation medium, remove the masking layer, and perform P-well impurity implantation to form a low-voltage P-well and a high-voltage P-well; The surfaces of the low-voltage P-well and the high-voltage P-well are processed, and a SiO2 gate oxide layer of a high-voltage MOS device is deposited by a CVD or ALD method; Remove the SiO2 gate oxide layer in the low-voltage NMOS area to expose the substrate; deposit the SiO2 gate oxide layer on the entire surface by CVD or ALD; and then deposit polysilicon on the entire surface; Perform photolithography and etching to form a polycrystalline gate electrode of the MOS device, and perform LDD implantation; deposit the sidewall dielectric of the polycrystalline gate electrode for subsequent formation of source and drain electrodes; An anisotropic etching method is used to form a gate electrode sidewall; Performing source-drain impurity implantation to form source-drain regions of a MOS device; The surface of the low-pressure P-well and the high-pressure P-well is processed by: growing SiO2 with a thickness of 10-20Å on the surface of the low-pressure P-well and the high-pressure P-well by a thermal oxidation method; The temperature for depositing the SiO2 gate oxide layer of the high-voltage MOS device is 300~800℃, and the thickness of the gate oxide layer is 15~400Å.

2. The gate oxide reinforcement method for improving the total dose resistance of MOS devices according to claim 1, characterized in that: The buffer oxide layer is SiO2 with a thickness of 50-200 nm; the masking layer is SiN with a thickness of 50-200 nm.

3. The gate oxide reinforcement method for improving the total dose resistance of MOS devices according to claim 1, characterized in that: The STI isolation medium is SiO2 deposited by HDPCVD process and is used as an isolation medium between MOS devices.

4. The gate oxide reinforcement method for improving the total dose resistance of MOS devices according to claim 1, characterized in that: The low voltage P well is formed by high concentration boron implantation and is used to manufacture low voltage NMOS devices; the high voltage P well is formed by low concentration boron implantation and is used to manufacture high voltage NMOS devices.

5. The gate oxide reinforcement method for improving the total dose resistance of MOS devices according to claim 1, characterized in that: The thickness of the polysilicon is 100-300 nm.

6. The gate oxide reinforcement method for improving the total dose resistance of MOS devices according to claim 1, characterized in that: The thickness of the substrate is SEMI standard thickness.

Images