A hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation

Abstract

The present invention discloses a hyperchaotic self-regulating waveform generator based on dual-memristor feedback amplitude modulation, which relates to the technical fields of electronics, communications and information engineering. The present invention introduces hyperchaos using nonlinear feedback with a multiplier as the core, memristor parameters to achieve signal amplitude regulation, and a DC power supply to achieve bias control and signal polarity control. The dual-memristor hyperchaotic circuit designed by the present invention outputs a self-regulating hyperchaotic signal, which can be used for confidential communications and information encryption, and can also generate pseudo-random numbers.

Description

Technical Field

[0001] The present invention relates to the technical field of electronics, communication and information engineering, and in particular to a hyperchaotic self-regulating waveform generator based on dual-memristor feedback amplitude modulation. Background Art

[0002] As a broadband random signal, hyperchaotic signals are widely used in fluid mixing, search and prediction, instrumentation, communication, radar and other fields. In engineering applications, the amplification or attenuation of the amplitude of hyperchaotic signals, the change of bias and polarity are the needs of signal conditioning. The design of self-regulating hyperchaotic circuits can reduce redundant circuit elements or additional systems and simplify the circuit.

[0003] Regarding the amplitude control of chaotic signals, relevant patents have given implementation plans. The invention with application number 200910183379.3 proposes a switchable third-order constant Lyapunov exponent spectrum chaotic circuit, which realizes nonlinear effects through absolute value terms and realizes amplitude adjustment of chaotic signals through DC power supply voltage. This adjustment does not change the dynamic characteristics and Lyapunov exponent spectrum of the system, but cannot perform polarity control. The invention with application number 201210395656.9 provides a four-wing chaotic signal source circuit, which realizes nonlinearity through cross-product terms, outputs complex four-wing chaotic phase orbits, and realizes local amplitude control by adjusting the feedback strength of the cross-product terms, but the complexity of the chaotic model is much weaker than that of the hyperchaotic signal. The patent application with application number 202010199862.7 proposes a dual-scroll memristor hyperchaotic signal source circuit, but the signal source circuit cannot achieve amplitude control and polarity control. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation. The present invention realizes amplitude control through memristor parameters and realizes bias and polarity control of hyperchaotic signals through a DC power supply.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] A hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation according to the present invention comprises a first memristor, a second memristor, a first product operation unit, a first inverting integration circuit, a second product operation unit, a second inverting integration circuit, a first inverting proportional circuit, a second inverting proportional circuit, first to fourth resistors, an adjustable current source, a capacitor, and an inverting summing integration operation unit; wherein,

[0007] One end of the first memristor is connected to the input end of the first product operation unit, and the output end of the first product operation unit is connected to the first inverting integration circuit;

[0008] One end of the second memristor is connected to the input end of the second product operation unit, the output end of the second product operation unit is connected to the input end of the second inverting integration circuit, and the output end of the second inverting integration circuit is connected to the first inverting proportional circuit;

[0009] One end of the first to fourth resistors is connected to one end of the capacitor respectively, one end of the capacitor is connected to the inverting input end of the inverting summing integral operation unit, one end of the adjustable current source is connected to the other end of the fourth resistor, the other end of the adjustable current source is grounded, the non-inverting input end of the inverting summing integral operation unit is grounded, and the output end of the inverting summing integral operation unit is connected to the other end of the capacitor and the second inverting proportional circuit respectively.

[0010] As a further optimization scheme of the hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation described in the present invention, the first inverting integration circuit includes fifth to sixth resistors, a first capacitor and a first inverting summing and integrating operation unit, wherein:

[0011] One end of the fifth resistor is connected to the output end of the first product operation unit, the other end of the fifth resistor is respectively connected to one end of the sixth resistor, one end of the first capacitor, and the inverting input end of the first inverting summation integral operation unit, the non-inverting input end of the first inverting summation integral operation unit is grounded, and the other end of the first capacitor is connected to the output end of the first inverting summation integral operation unit.

[0012] As a further optimization scheme of the hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation described in the present invention, the second inverting integration circuit includes seventh to eighth resistors, a second capacitor and a second inverting summing and integrating operation unit, wherein:

[0013] One end of the seventh resistor is connected to the output end of the second product operation unit, the other end of the seventh resistor is connected to one end of the eighth resistor, one end of the second capacitor, and the inverting input end of the second inverting summation integral operation unit respectively, the non-inverting input end of the second inverting summation integral operation unit is grounded, and the other end of the second capacitor is connected to the output end of the second inverting summation integral operation unit.

[0014] As a further optimization scheme of a hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation described in the present invention, the first memristor includes a first variable module, first to second absolute value operation units, a first inverting ratio operation unit, a first inverting summation operation unit, ninth to eighteenth resistors, a first diode, a second diode and a first AC voltage source; wherein,

[0015] The output end of the first variable module is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the tenth resistor, one end of the eleventh resistor, and the inverting input end of the first absolute value operation unit respectively, the non-inverting input end of the first absolute value operation unit is grounded, the output end of the first absolute value operation unit is connected to the cathode of the first diode and the anode of the second diode respectively, the anode of the first diode is connected to the other end of the tenth resistor and one end of the twelfth resistor respectively, the cathode of the second diode is connected to the other end of the eleventh resistor and the non-inverting input end of the second absolute value operation unit respectively, the other end of the twelfth resistor is connected to one end of the thirteenth resistor and the inverting input end of the second absolute value operation unit respectively, and the output end of the second absolute value operation unit is connected to the thirteenth resistor. The other end of the resistor and one end of the fourteenth resistor are respectively connected, the other end of the fourteenth resistor is respectively connected to one end of the fifteenth resistor and the inverting input end of the first inverting proportional operation unit, the non-inverting input end of the first inverting proportional operation unit is grounded, the output end of the first inverting proportional operation unit is respectively connected to the other end of the fifteenth resistor and one end of the sixteenth resistor, the other end of the sixteenth resistor is respectively connected to one end of the seventeenth resistor, one end of the eighteenth resistor, and the inverting input end of the first inverting summation operation unit, the other end of the seventeenth resistor is connected to the positive electrode of the first AC voltage source, the negative electrode of the first AC voltage source is grounded, the other end of the eighteenth resistor is connected to the output end of the first inverting summation operation unit, and the non-inverting input end of the first inverting summation operation unit is grounded;

[0016] The second memristor includes a second variable module, a second inverting proportional operation unit, a second inverting summation operation unit, a third product operation unit, a second AC voltage source, and nineteenth to twenty-third resistors, wherein:

[0017] The output end of the second variable module is connected to one end of the nineteenth resistor, the other end of the nineteenth resistor is connected to one end of the twentieth resistor and the inverting input end of the second inverting proportional operation unit respectively, the positive input end of the second inverting proportional operation unit is grounded, the other end of the twentieth resistor is connected to the output end of the second inverting proportional operation unit and the input end of the third product operation unit respectively, the output end of the third product operation unit is connected to one end of the twenty-second resistor, the other end of the twenty-second resistor is connected to one end of the twenty-first resistor, one end of the twenty-third resistor, and the inverting input end of the second inverting summation operation unit respectively, the positive input end of the second inverting summation operation unit is grounded, the output end of the second inverting summation operation unit is connected to the other end of the twenty-third resistor, the other end of the twenty-first resistor is connected to the positive electrode of the second AC voltage source, and the negative electrode of the second AC voltage source is grounded;

[0018] The first variable module and the second variable module have the same structure. The first variable module includes fourth to fifth product operation units, a third capacitor, a twenty-fourth resistor, an adjustable resistor and a third inverting summation integral operation unit, wherein the fifth product operation unit is connected to one end of the twenty-fourth resistor, the other end of the twenty-fourth resistor is respectively connected to one end of the third capacitor, one end of the adjustable resistor, and the inverting input end of the third inverting summation integral operation unit, the other end of the adjustable resistor is connected to the fourth product operation unit, and the output end of the third inverting summation integral operation unit is connected to the other end of the third capacitor.

[0019] As a further optimization scheme of the hyperchaotic self-regulating waveform generator based on dual-memristor feedback amplitude modulation described in the present invention, in the first memristor, the output end of the third inverting sum-integral operation unit is connected to one end of the ninth resistor.

[0020] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0021] The present invention uses a four-way integral summation operation circuit, six multiplier circuits and two inverting operation units to output a hyperchaotic signal with controllable amplitude, bias and polarity; the adjustable resistance, capacitance and adjustable DC power supply of the memristor branch are used to change the value and polarity of the amplitude change of the output hyperchaotic signal to achieve amplitude regulation and polarity control, thereby increasing the flexibility of the hardware circuit and providing convenience for the application of hyperchaotic signals in electronic and information engineering such as information transmission and encryption. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is the phase trajectory diagram of the numerical simulation of the hyperchaotic self-regulating waveform generator with dual memristor feedback amplitude modulation: where (a) is the xy plane diagram, (b) is the yz plane diagram;

[0023] Figure 2 This is the simulated x signal waveform of the hyperchaotic self-regulating waveform generator with dual memristor feedback amplitude modulation: (a) is when n = 0, the change of f adjusts the amplitude, (b) is when f = 1, the change of n adjusts the bias and polarity;

[0024] Figure 3 is the circuit schematic diagram of the hyperchaotic self-regulating waveform generator with dual memristor feedback amplitude modulation; wherein, (a) is the system simulation circuit, (b) is the memristor W1(u) simulation circuit, and (c) is the memristor W2(u) simulation circuit;

[0025] Figure 4 It is the experimental simulation phase trajectory diagram of the hyperchaotic self-regulating waveform generator with dual memristor feedback amplitude modulation; wherein, (a) is the xy plane diagram, and (b) is the yz plane diagram;

[0026] Figure 5is the waveform diagram of the signal amplitude control of the hyperchaotic self-regulating waveform transmitter x with dual memristor feedback amplitude modulation; where (a) is R 14 =200kΩ x signal waveform, (b) is R 14 =100kΩ x signal waveform, (c) is R 14 = x signal waveform when 50kΩ;

[0027] Figure 6 It is the x signal polarity control waveform diagram of the hyperchaotic self-regulating waveform transmitter with dual memristor feedback amplitude modulation; among them, (a) is the x signal waveform diagram when V1=-5V, (b) is the x signal waveform diagram when V1=0V, and (c) is the x signal waveform diagram when V1=5V. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings:

[0029] The present invention belongs to the field of electronics, communications and information engineering, and relates to a memristor hyperchaotic circuit design with adjustable amplitude. Hyperchaos is introduced by nonlinear feedback with a multiplier as the core. The memristor parameter realizes signal amplitude adjustment, and the DC power supply realizes bias control and signal polarity control. The dual memristor hyperchaotic circuit designed by the present invention outputs a self-regulating hyperchaotic signal, which can be used for confidential communication and information encryption, and can also generate pseudo-random numbers.

[0030] Memristor, as a new type of nonlinear element, has become a new type of circuit module commonly used in hyperchaotic systems due to the introduction of nonlinear feedback. Many circuits introduce memristors to obtain hyperchaos. In recent years, with the deepening of memristor research, some classical systems and other systems have been successfully transformed into hyperchaotic memristor systems. The present invention introduces two memristors in the jerk system and appropriately increases the feedback term to realize a dual-memristor hyperchaotic circuit. The circuit controls the amplitude of the hyperchaotic signal through the resistance of a branch and directly controls the bias and polarity of the hyperchaotic signal through a DC power supply.

[0031] The hyperchaotic memristor circuit of the present invention uses the integral summation circuit of four branches as the framework, and outputs four hyperchaotic signals through six multipliers and twelve operational amplifiers, combined with a number of resistors and four capacitors. The amplitude of the hyperchaotic signal output by the system is controlled by adjusting the resistor or capacitor on the nonlinear feedback branch in the memristor branch. The bias and polarity of the hyperchaotic signal are controlled by changing the DC power supply or capacitor size of the third branch.

[0032] A hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation, comprising a first memristor W1(u), a second memristor W2(u), a first product operation unit M1, a first inverting integration circuit, a second product operation unit M2, a second inverting integration circuit, a first inverting proportional circuit, a second inverting proportional circuit, first to fourth resistors R7-R 10 , adjustable current source V1, capacitor C3, inverting summing and integrating operation unit U3; wherein,

[0033] One end of the first memristor is connected to the input end of the first product operation unit, and the output end of the first product operation unit is connected to the first inverting integration circuit;

[0034] One end of the second memristor is connected to the input end of the second product operation unit, the output end of the second product operation unit is connected to the input end of the second inverting integration circuit, and the output end of the second inverting integration circuit is connected to the first inverting proportional circuit;

[0035] One end of the first to fourth resistors is connected to one end of the capacitor respectively, one end of the capacitor is connected to the inverting input end of the inverting summing integral operation unit, one end of the adjustable current source is connected to the other end of the fourth resistor, the other end of the adjustable current source is grounded, the non-inverting input end of the inverting summing integral operation unit is grounded, and the output end of the inverting summing integral operation unit is connected to the other end of the capacitor and the second inverting proportional circuit respectively.

[0036] The first inverting integration circuit includes fifth to sixth resistors R1, R2, a first capacitor C1 and a first inverting summing integration operation unit U1, wherein:

[0037] One end of the fifth resistor is connected to the output end of the first product operation unit, the other end of the fifth resistor is respectively connected to one end of the sixth resistor, one end of the first capacitor, and the inverting input end of the first inverting summation integral operation unit, the non-inverting input end of the first inverting summation integral operation unit is grounded, and the other end of the first capacitor is connected to the output end of the first inverting summation integral operation unit.

[0038] The second inverting integration circuit includes seventh to eighth resistors R3, R4, a second capacitor C2 and a second inverting summing integration operation unit U2, wherein:

[0039] One end of the seventh resistor is connected to the output end of the second product operation unit, the other end of the seventh resistor is connected to one end of the eighth resistor, one end of the second capacitor, and the inverting input end of the second inverting summation integral operation unit respectively, the non-inverting input end of the second inverting summation integral operation unit is grounded, and the other end of the second capacitor is connected to the output end of the second inverting summation integral operation unit.

[0040] The first memristor W1(u) includes a first variable module, first to second absolute value operation units U7, U8, a first inverting proportional operation unit U9, a first inverting summation operation unit U 10 , the ninth to eighteenth resistors R 15 -R 23 , a first diode D1, a second diode D2 and a first AC voltage source V2; wherein,

[0041] The output end of the first variable module is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the tenth resistor, one end of the eleventh resistor, and the inverting input end of the first absolute value operation unit respectively, the non-inverting input end of the first absolute value operation unit is grounded, the output end of the first absolute value operation unit is connected to the cathode of the first diode and the anode of the second diode respectively, the anode of the first diode is connected to the other end of the tenth resistor and one end of the twelfth resistor respectively, the cathode of the second diode is connected to the other end of the eleventh resistor and the non-inverting input end of the second absolute value operation unit respectively, the other end of the twelfth resistor is connected to one end of the thirteenth resistor and the inverting input end of the second absolute value operation unit respectively, and the output end of the second absolute value operation unit is connected to the thirteenth resistor. The other end of the resistor and one end of the fourteenth resistor are respectively connected, the other end of the fourteenth resistor is respectively connected to one end of the fifteenth resistor and the inverting input end of the first inverting proportional operation unit, the non-inverting input end of the first inverting proportional operation unit is grounded, the output end of the first inverting proportional operation unit is respectively connected to the other end of the fifteenth resistor and one end of the sixteenth resistor, the other end of the sixteenth resistor is respectively connected to one end of the seventeenth resistor, one end of the eighteenth resistor, and the inverting input end of the first inverting summation operation unit, the other end of the seventeenth resistor is connected to the positive electrode of the first AC voltage source, the negative electrode of the first AC voltage source is grounded, the other end of the eighteenth resistor is connected to the output end of the first inverting summation operation unit, and the non-inverting input end of the first inverting summation operation unit is grounded;

[0042] The second memristor W2(u) includes a second variable module, a second inverting proportional operation unit U 11 , the second inverting summing operation unit U 12 , a third product operation unit M7, a second AC voltage source V3, nineteenth to twenty-third resistors R 25 -R 29 ,in,

[0043] The output end of the second variable module is connected to one end of the nineteenth resistor, the other end of the nineteenth resistor is connected to one end of the twentieth resistor and the inverting input end of the second inverting proportional operation unit respectively, the positive input end of the second inverting proportional operation unit is grounded, the other end of the twentieth resistor is connected to the output end of the second inverting proportional operation unit and the input end of the third product operation unit respectively, the output end of the third product operation unit is connected to one end of the twenty-second resistor, the other end of the twenty-second resistor is connected to one end of the twenty-first resistor, one end of the twenty-third resistor, and the inverting input end of the second inverting summation operation unit respectively, the positive input end of the second inverting summation operation unit is grounded, the output end of the second inverting summation operation unit is connected to the other end of the twenty-third resistor, the other end of the twenty-first resistor is connected to the positive electrode of the second AC voltage source, and the negative electrode of the second AC voltage source is grounded;

[0044] The first variable module and the second variable module have the same structure. The first variable module includes the fourth to fifth product operation units M3, M4, the third capacitor C4, the twenty-fourth resistor R 13 , adjustable resistor R 14 And a third inverting summation integral operation unit U6, wherein the fifth product operation unit is connected to one end of the twenty-fourth resistor, the other end of the twenty-fourth resistor is respectively connected to one end of the third capacitor, one end of the adjustable resistor, and the inverting input end of the third inverting summation integral operation unit, the other end of the adjustable resistor is connected to the fourth product operation unit, and the output end of the third inverting summation integral operation unit is connected to the other end of the third capacitor.

[0045] In the first memristor, an output end of the third inverting summing integral operation unit is connected to one end of the ninth resistor.

[0046] The amplitude controllable hyperchaotic memristor circuit includes four branches, wherein the first branch includes three input terminals, wherein the input signals y, z and -z are connected to the input terminal of the integral operation unit U1 through resistors R1 and R2 respectively; the input terminal z is connected to the memristor W1(u), and the output z W1(u) item is connected; the input terminals -z and z W1(u) are connected to R1 through the product operation unit M1 and then to the input terminal of the integral operation unit U1. The input terminal y is connected to R2 and then to the input terminal of the operation unit U1, and the in-phase input terminal of the summing integral operation unit U1 is grounded. The inverting input terminal of the summing integral operation unit U1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the output terminal x of the summing integral operation unit U1.

[0047] In the above-mentioned hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation, the input signal z in the first branch is connected to the memristor W1(u), and W1(u) includes a resistor R 13 , resistor R 14 , resistor R 15 , resistor R16 , resistor R 17 , resistor R 18 , resistor R 19 , resistor R 20 , resistor R 21 , resistor R 22 , resistor R 23 , resistor R 24 , capacitor C4, op amp U6, op amp U7, op amp U8, op amp U9, op amp U 10 , product operation units M3 and M4, diode D1, diode D2, AC voltage source V2.

[0048] The above-mentioned hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation, the second branch includes three input terminals, wherein the input terminals z, -z and y are connected to the input terminal of the integral operation unit U2 through resistors R3 and R4 respectively; the input terminal z is connected to the memristor W2(u), and the output z W2(u) item is connected, and the input terminals -z and z W2(u) are connected to R3 through the product operation unit M2 and then to the input terminal of the integral operation unit U2. The input terminal y is connected to R4 and then to the inverting input terminal of the operation unit U2. The inverting input terminal of the summing integral operation unit U2 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the output terminal y of the summing integral operation unit U2. The in-phase input terminal of the operation unit U2 is grounded. The output end of the operation unit U2 is connected to the inverting input end of the inverting amplifier unit U4 via the resistor R5, the non-inverting input end of the inverting amplifier unit U4 is grounded, the inverting input end of the inverting amplifier unit U4 is connected to one end of the resistor R6, and the other end of the resistor R6 and the output end of the inverting amplifier unit U4 are connected to the output end -y of the second branch.

[0049] In the above-mentioned hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation, the input signal z in the second branch is connected to the memristor W2(u), and W2(u) includes a resistor R 13 , resistor R 14 , resistor R 25 , resistor R 26 , resistor R 27 , resistor R 28 , resistor R 29 , capacitor C4, op amp U6, op amp U 11 , op amp U 12 , product operation units M5, M6 and M7, AC voltage source V3.

[0050] The above-mentioned hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation, the third branch includes an integral summing unit U3 and an inverting unit U5, a resistor R7, a resistor R8, a resistor R9 and a resistor R 10and capacitor C3, wherein the input terminal -z is connected to the inverting input terminal of the operation unit U3 through the resistor R7, the input terminal y is connected to the inverting input terminal of the operation unit U3 through the resistor R8, the input terminal x is connected to the resistor R9 and connected to the inverting input terminal of the operation unit U3, and the DC power supply V1 is connected to the resistor R 10 The inverting input terminal of the summing operation unit U3 is connected to the inverting input terminal of the operation unit U3. The non-inverting input terminal of the summing operation unit is grounded. The inverting input terminal of the summing and integrating operation unit U3 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the output terminal z of the summing and integrating operation unit U3. The output terminal of the operation unit U3 is connected to the output terminal z of the summing and integrating operation unit U3 through the resistor R 11 The inverting input terminal of the inverting amplifier unit U5 is connected to the ground, and the non-inverting input terminal of the inverting amplifier unit U5 is connected to the ground. 12 One end is connected to the resistor R 12 The other end of and the output end of the inverting amplifier unit U4 are connected to the output end -z of the third branch.

[0051] The amplitude of the hyperchaotic signal output by the hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation can be changed by adjusting the resistance R in the memristors W1(u) and W2(u). 14 The polarity of the chaotic signal can be controlled by adjusting the adjustable DC power supply voltage V1 of the third branch.

[0052] Dynamic equation and circuit structure of hyperchaotic self-regulating waveform generator with dual memristor feedback amplitude modulation

[0053] The dual-memristor feedback amplitude modulation hyperchaotic self-regulating waveform generator of the present invention can be described by the following dynamic system equation:

[0054]

[0055] Its memristor equation is:

[0056]

[0057]

[0058] From a formal point of view, the equation contains seven first-order linear feedbacks, two second-order nonlinear feedbacks, one third-order nonlinear feedback and one internal nonlinear feedback. When a=-1, b=0.4, c=-10, d=130, e=6, f=1, g=11, h=1, IC=(0,0,1,1), the system outputs the hyperchaotic attractor as follows: Figure 1 As shown, Figure 1This is the phase trajectory diagram of the numerical simulation of the hyperchaotic self-regulating waveform generator with dual memristor feedback amplitude modulation: Figure 1 (a) is the xy plane graph, Figure 1 (b) is the yz plane graph; the Lyapunov index of the system is (1.10684, 0.11299, 0, -28.455), and D KY =3.0429. By jointly regulating the parameters f and n, the amplitude, bias and polarity of the hyperchaotic signal x(t) can be controlled, as shown in Figure 2 As shown, Figure 2 This is the simulated x signal waveform of the hyperchaotic self-regulating waveform generator with dual memristor feedback amplitude modulation: Figure 2 (a) is when n = 0, the change of f adjusts the amplitude, Figure 2 (b) is when f = 1, the change of n adjusts the bias and polarity. This system can be realized by a closed feedback system consisting of three branches. When a three-way integral summation operation loop is used to realize it, the circuit diagram is as follows Figure 3 As shown, Figure 3 (a) is the system simulation circuit. Figure 3 (b) in the figure is the analog circuit of memristor W1(u). Figure 3 (c) in the figure is the analog circuit of memristor W2(u); the above mathematical equation is transformed into a more specific circuit equation:

[0059]

[0060] in The circuit equation is consistent with the system dynamics equation. Here, the coefficients of each feedback term in the system are realized by the joint setting of resistance and capacitance, while the linear term coefficient f can realize the amplitude control of the signal, which can be controlled by the variable resistor R 14 The bias and polarity of the x signal can be controlled by adjusting the adjustable DC power supply V1.

[0061] The first branch of the dual-memristor feedback amplitude modulation hyperchaotic self-regulating waveform generator includes an inverting summing integral operation unit U1, a resistor R1, a resistor R2, a capacitor C1, and a product unit M1, wherein the input terminals y, z, and -z are connected to the input terminal of the integral operation unit U1 through resistors R1 and R2 respectively; the input terminal z is connected to the memristor W1(u), and the output z W1(u) item is connected to R1 through the product operation unit M1, and then to the input terminal of the integral operation unit U1. The input terminal y is connected to R2 and then to the input terminal of the operation unit U1, and the in-phase input terminal of the summing integral operation unit U1 is grounded. The inverting input terminal of the summing integral operation unit U1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the output terminal x of the summing integral operation unit U1.

[0062] The second branch of the dual-memristor feedback amplitude modulation hyperchaotic self-regulating waveform generator includes an inverting summing integral operation unit U2, an inverting proportional operation unit U4, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a capacitor C2, wherein the in-phase input end of the integral summing operation unit U2 is grounded, the inverting input end of the summing integral operation unit U2 is connected to one end of the capacitor C2, the other end of the capacitor C2 and the output end of the summing integral operation unit U2 are connected to the inverting input end of the inverting proportional operation unit U4 via the resistor R5, the in-phase input end of the inverting proportional operation unit U4 is grounded, the inverting input end of the inverting proportional operation unit U4 is connected to one end of the resistor R6, and one end of the resistor R6 in the second branch is connected to the output end of the inverting proportional operation unit U4. The input branch of the operation unit U2 includes three input terminals, the input terminal z is connected to the memristor W2(u), the output z W2(u) item, the input terminals -z and zW2(u) are connected to R3 through the product operation unit M2 and then connected to the input terminal of the integral operation unit U2, the output terminal y of the integral operation unit U2 is connected to the reverse proportional operation unit U4, and the output terminal -y of the reverse proportional operation unit U4 is connected.

[0063] The third branch of the dual-memristor feedback amplitude modulation hyperchaotic self-regulating waveform generator includes an inverting summing integral operation unit U3, an inverting proportional operation unit U5, a resistor R7, a resistor R8, a resistor R9, a resistor R 10 , resistor R 11 , resistor R 12 The in-phase input terminal of the integral summing operation unit U3 is grounded, the inverting input terminal of the summing integral operation unit U3 is connected to one end of the capacitor C3, and the other end of the capacitor C3 and the output end of the summing integral operation unit U3 are connected via a resistor R 10 The inverting input terminal of the inverting proportional operation unit U5 is connected to the ground. The inverting input terminal of the inverting proportional operation unit U5 is connected to the resistor R 11 and the resistor R in the second branch 11 The input branch of the operation unit U3 includes three input terminals. The input terminals -z, y and x are connected to the input terminal of the integral operation unit U3 through resistors R7, R8 and R9 respectively. The adjustable current source V1 is connected to the output terminal of the inverting proportional operation unit U5 through resistor R 10 It is connected to the input end of the integral operation unit U3, the output end z of the integral operation unit U3 is connected to the reverse proportional operation unit U5, and the output end -z of the reverse proportional operation unit U5.

[0064] The memristor W1(u) branch of the dual memristor feedback amplitude modulation hyperchaotic self-regulating waveform generator includes an inverting summing integral operation unit U6, absolute value operation units U7 and U8, an inverting proportional operation unit U9, an inverting summing operation unit U10, and an inverting proportional operation unit U11.10 , resistor R 13 , resistor R 14 , resistor R 15 , resistor R 16 , resistor R 17 , resistor R 18 , resistor R 19 , resistor R 20 , resistor R 21 , resistor R 22 , resistor R 23 , resistor R 24 And capacitor C4, DC power supply V2, diodes D1 and D2, wherein the in-phase input terminal of the integral summing operation unit U6 is grounded, the inverting input terminal of the summing integral operation unit U6 is connected to one end of the capacitor C4, and the other end of the capacitor C4 and the output end of the summing integral operation unit U6 are connected via a resistor R 15 The inverting input terminal of the absolute value operation unit U7 is connected to the ground, and the inverting output terminal of the absolute value operation unit U8 is connected to the resistor R 20 One end is connected to the resistor R 20 The other end passes through the inverting proportional operation unit U9 and the DC power supply V2 and the reverse summing operation unit U 10 The input branch of the operation unit U6 includes two input terminals, input terminal -z, and input terminal z connected to the multiplier M4 and the product of u and u respectively through the resistor R 13 and resistor R 14 Connected to the input terminal of the integral operation unit U6, where R 14 It is an adjustable resistor that can control the amplitude of x, y and z signals. The output end of the operation unit U6 is u.

[0065] The dual-memristor feedback amplitude modulation hyperchaotic self-regulating waveform generator memristor W2(u) branch includes an inverting summing integral operation unit U6, an inverting proportional operation unit U 11 , inverting summation unit U 12 , resistor R 13 , resistor R 14 , resistor R 25 , resistor R 26 , resistor R 27 , resistor R 28 , resistor R 29 The in-phase input terminal of the integral and summing operation unit U6 is grounded, the inverting input terminal of the summing and integral operation unit U6 is connected to one end of the capacitor C4, and the other end of the capacitor C4 and the output end of the summing and integral operation unit U6 are connected via a resistor R 25 Connect to the inverting proportional unit U 11The inverting input terminal of the inverting proportional operation unit U 11 The non-inverting input terminal is grounded, and the inverting output terminal is multiplied by u and passes through the resistor R 28 And the inverting summation unit U 12 The DC power supply V3 passes through the resistor R 27 And the inverting summation unit U 12 The input branch of the operation unit U6 includes two input terminals, input terminal -z, and input terminal z connected to the multiplier M4 and the product of u and u respectively through the resistor R 13 and resistor R 14 Connected to the input terminal of the integral operation unit U6, where R 14 It is an adjustable resistor that can control the amplitude of x, y and z signals. The output end of the operation unit U6 is u.

[0066] Amplitude, bias and polarity control methods

[0067] The dual-memristor feedback amplitude modulation hyperchaotic self-regulating waveform generator is characterized in that the amplitude of the output hyperchaotic signal can be changed by the variable resistor R 14 It can be realized by adjusting. From equation (5), when the coefficient m is introduced, the amplitude of the output chaotic signals x, y and z changes with the change of m, which can be obtained by x→mx, y→my, z→mz, u→u, t→t (m>0), which only leaves an extra coefficient in the four-dimensional equation:

[0068]

[0069] The invariance of the system expression (1) (compared to the case of m = 1) is proved. It can be seen that when the variable resistor R 14 When it changes, it causes changes of different scales, such as Figure 5 The polarity control of the chaotic signal x can be achieved by adjusting the adjustable DC power supply voltage V1 of the third branch, as shown in Figure 6 shown. Figure 5 is a waveform diagram of the signal amplitude control of the hyperchaotic self-regulating waveform transmitter x with dual memristor feedback amplitude modulation; wherein, Figure 5 (a) in the equation is R 14 =200kΩ x signal waveform, Figure 5 (b) in the equation is R 14 =100kΩ x signal waveform, Figure 5 (c) in the equation is R 14 = x signal waveform when 50kΩ; Figure 6 is the waveform diagram of the x signal polarity control of the hyperchaotic self-regulating waveform transmitter with dual memristor feedback amplitude modulation; wherein, Figure 6(a) is the waveform of the x signal when V1 = -5V. Figure 6 (b) is the waveform of the x signal when V1 = 0V. Figure 6 (c) in the figure is the waveform of the x signal when V1=5V. Figure 4 This is the experimental simulation phase trajectory diagram of the hyperchaotic self-regulating waveform generator with dual memristor feedback amplitude modulation; among them, Figure 4 (a) is the xy plane graph, Figure 4 (b) in the figure is the yz plane diagram.

[0070] The above description is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation, characterized in that: It includes a first memristor, a second memristor, a first product operation unit, a first inverting integration circuit, a second product operation unit, a second inverting integration circuit, a first inverting proportional circuit, a second inverting proportional circuit, first to fourth resistors, an adjustable current source, a capacitor, and an inverting summing integration operation unit; wherein, One end of the first memristor is connected to the input end of the first product operation unit, and the output end of the first product operation unit is connected to the first inverting integration circuit; One end of the second memristor is connected to the input end of the second product operation unit, the output end of the second product operation unit is connected to the input end of the second inverting integration circuit, and the output end of the second inverting integration circuit is connected to the first inverting proportional circuit; One end of the first to fourth resistors is connected to one end of the capacitor respectively, one end of the capacitor is connected to the inverting input end of the inverting summing integral operation unit, one end of the adjustable current source is connected to the other end of the fourth resistor, the other end of the adjustable current source is grounded, the non-inverting input end of the inverting summing integral operation unit is grounded, and the output end of the inverting summing integral operation unit is connected to the other end of the capacitor and the second inverting proportional circuit respectively.

2. The hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation according to claim 1, characterized in that: The first inverting integration circuit includes fifth to sixth resistors, a first capacitor and a first inverting summing integration operation unit, wherein: One end of the fifth resistor is connected to the output end of the first product operation unit, the other end of the fifth resistor is respectively connected to one end of the sixth resistor, one end of the first capacitor, and the inverting input end of the first inverting summation integral operation unit, the non-inverting input end of the first inverting summation integral operation unit is grounded, and the other end of the first capacitor is connected to the output end of the first inverting summation integral operation unit.

3. The hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation according to claim 1, characterized in that: The second inverting integration circuit includes seventh to eighth resistors, a second capacitor and a second inverting summing integration operation unit, wherein: One end of the seventh resistor is connected to the output end of the second product operation unit, the other end of the seventh resistor is connected to one end of the eighth resistor, one end of the second capacitor, and the inverting input end of the second inverting summation integral operation unit respectively, the non-inverting input end of the second inverting summation integral operation unit is grounded, and the other end of the second capacitor is connected to the output end of the second inverting summation integral operation unit.

4. The hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation according to claim 1, characterized in that: The first memristor includes a first variable module, first to second absolute value operation units, a first inverting ratio operation unit, a first inverting summation operation unit, ninth to eighteenth resistors, a first diode, a second diode and a first AC voltage source; wherein, The output end of the first variable module is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the tenth resistor, one end of the eleventh resistor, and the inverting input end of the first absolute value operation unit respectively, the non-inverting input end of the first absolute value operation unit is grounded, the output end of the first absolute value operation unit is connected to the cathode of the first diode and the anode of the second diode respectively, the anode of the first diode is connected to the other end of the tenth resistor and one end of the twelfth resistor respectively, the cathode of the second diode is connected to the other end of the eleventh resistor and the non-inverting input end of the second absolute value operation unit respectively, the other end of the twelfth resistor is connected to one end of the thirteenth resistor and the inverting input end of the second absolute value operation unit respectively, and the output end of the second absolute value operation unit is connected to the thirteenth resistor. The other end of the resistor and one end of the fourteenth resistor are respectively connected, the other end of the fourteenth resistor is respectively connected to one end of the fifteenth resistor and the inverting input end of the first inverting proportional operation unit, the non-inverting input end of the first inverting proportional operation unit is grounded, the output end of the first inverting proportional operation unit is respectively connected to the other end of the fifteenth resistor and one end of the sixteenth resistor, the other end of the sixteenth resistor is respectively connected to one end of the seventeenth resistor, one end of the eighteenth resistor, and the inverting input end of the first inverting summation operation unit, the other end of the seventeenth resistor is connected to the positive electrode of the first AC voltage source, the negative electrode of the first AC voltage source is grounded, the other end of the eighteenth resistor is connected to the output end of the first inverting summation operation unit, and the non-inverting input end of the first inverting summation operation unit is grounded; The second memristor includes a second variable module, a second inverting proportional operation unit, a second inverting summation operation unit, a third product operation unit, a second AC voltage source, and nineteenth to twenty-third resistors, wherein: The output end of the second variable module is connected to one end of the nineteenth resistor, the other end of the nineteenth resistor is connected to one end of the twentieth resistor and the inverting input end of the second inverting proportional operation unit respectively, the positive input end of the second inverting proportional operation unit is grounded, the other end of the twentieth resistor is connected to the output end of the second inverting proportional operation unit and the input end of the third product operation unit respectively, the output end of the third product operation unit is connected to one end of the twenty-second resistor, the other end of the twenty-second resistor is connected to one end of the twenty-first resistor, one end of the twenty-third resistor, and the inverting input end of the second inverting summation operation unit respectively, the positive input end of the second inverting summation operation unit is grounded, the output end of the second inverting summation operation unit is connected to the other end of the twenty-third resistor, the other end of the twenty-first resistor is connected to the positive electrode of the second AC voltage source, and the negative electrode of the second AC voltage source is grounded; The first variable module and the second variable module have the same structure. The first variable module includes fourth to fifth product operation units, a third capacitor, a twenty-fourth resistor, an adjustable resistor and a third inverting summation integral operation unit, wherein the fifth product operation unit is connected to one end of the twenty-fourth resistor, the other end of the twenty-fourth resistor is respectively connected to one end of the third capacitor, one end of the adjustable resistor, and the inverting input end of the third inverting summation integral operation unit, the other end of the adjustable resistor is connected to the fourth product operation unit, and the output end of the third inverting summation integral operation unit is connected to the other end of the third capacitor.

5. The hyperchaotic self-regulating waveform generator based on dual memristor feedback amplitude modulation according to claim 4, characterized in that: In the first memristor, an output end of the third inverting summing integral operation unit is connected to one end of the ninth resistor.

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