Semiconductor device and method for manufacturing the same

Abstract

An embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, an integrated circuit region formed in the semiconductor substrate, and one or more sealing rings. The one or more sealing rings are provided in the semiconductor substrate and arranged around the periphery of the integrated circuit region to protect the integrated circuit region; wherein the sealing ring has a wavy structure.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. As the size of semiconductor devices continues to decrease, the requirements for the sealing rings around the chip to prevent moisture and ions from entering the chip and to prevent cracks from propagating into the chip are getting higher and higher. However, the protection effect of the sealing rings in the prior art is not ideal. Summary of the invention

[0003] The semiconductor device and the manufacturing method thereof provided by the embodiments of the present invention have a stronger protective effect of the sealing ring.

[0004] A semiconductor device according to an embodiment of the present invention comprises a semiconductor substrate, an integrated circuit region formed in the semiconductor substrate, and one or more sealing rings, wherein the one or more sealing rings are provided in the semiconductor substrate and arranged around the periphery of the integrated circuit region to protect the integrated circuit region; wherein the sealing ring has a wavy structure.

[0005] In one embodiment, the sealing ring includes a plurality of crests and a plurality of troughs, the plurality of crests and the plurality of troughs are alternately arranged, each of the crests protrudes toward the integrated circuit region, and each of the troughs protrudes away from the integrated circuit region.

[0006] In one embodiment, the curvatures of the plurality of crest portions are the same, and the curvatures of the plurality of trough portions are the same.

[0007] In one embodiment, the curvature of each of the crest portions and each of the trough portions is the same.

[0008] In one embodiment, the number of the sealing rings is at least two.

[0009] In one embodiment, the plurality of wave crests of one of the two adjacent sealing rings are arranged corresponding to the plurality of wave crests of the other sealing ring;

[0010] The plurality of troughs of one of the two adjacent sealing rings are arranged corresponding to the plurality of troughs of the other sealing ring.

[0011] In one embodiment, the plurality of wave crests of one of the two adjacent sealing rings are arranged corresponding to the plurality of wave troughs of the other sealing ring;

[0012] The plurality of trough portions of one of the two adjacent sealing rings are arranged correspondingly to the plurality of peak portions of the other sealing ring.

[0013] In one embodiment, the number of the sealing rings is at least two, and one of the two adjacent sealing rings includes a plurality of finger-shaped portions, and the finger-shaped portions extend toward the other sealing ring.

[0014] In one embodiment, the finger portion is connected to two adjacent sealing rings, so that at least two sealing rings form a mesh structure.

[0015] In one embodiment, the finger portion has an arcuate surface, and the arcuate surface faces the other sealing ring.

[0016] In one embodiment, the semiconductor device further includes a barrier layer disposed between the semiconductor substrate and the sealing ring.

[0017] The method for manufacturing a semiconductor device according to an embodiment of the present invention comprises the following steps:

[0018] Providing a semiconductor substrate having an integrated circuit region;

[0019] forming one or more trenches on the semiconductor substrate, the trenches being arranged around the periphery of the integrated circuit region; and

[0020] One or more sealing rings are formed in the one or more grooves, and the sealing rings have a wavy structure.

[0021] In one embodiment, before forming one or more sealing rings in the one or more grooves, the method further includes:

[0022] A barrier layer is formed conformally to the surface of the trench.

[0023] In one embodiment, the sealing ring includes a plurality of crests and a plurality of troughs, the plurality of crests and the plurality of troughs are alternately arranged, each of the crests protrudes toward the integrated circuit region, and each of the troughs protrudes away from the integrated circuit region.

[0024] In one embodiment, the curvatures of the plurality of crest portions are the same, and the curvatures of the plurality of trough portions are the same.

[0025] In one embodiment, the curvature of each of the crest portions and each of the trough portions is the same.

[0026] In one embodiment, the number of the sealing rings is at least two.

[0027] In one embodiment, the plurality of wave crests of one of the two adjacent sealing rings are arranged corresponding to the plurality of wave crests of the other sealing ring;

[0028] The plurality of troughs of one of the two adjacent sealing rings are arranged corresponding to the plurality of troughs of the other sealing ring.

[0029] In one embodiment, the plurality of wave crests of one of the two adjacent sealing rings are arranged corresponding to the plurality of wave troughs of the other sealing ring;

[0030] The plurality of trough portions of one of the two adjacent sealing rings are arranged correspondingly to the plurality of peak portions of the other sealing ring.

[0031] In one embodiment, the number of the sealing rings is at least two, and one of the two adjacent sealing rings includes a plurality of finger-shaped portions, and the finger-shaped portions extend toward the other sealing ring.

[0032] In one embodiment, the finger portion is connected to two adjacent sealing rings, so that at least two sealing rings form a mesh structure.

[0033] In one embodiment, the finger portion has an arcuate surface, and the arcuate surface faces the other sealing ring.

[0034] One embodiment of the above invention has the following advantages or beneficial effects:

[0035] The sealing ring of the embodiment of the present invention has a wavy structure, which makes the surface of the sealing ring facing the integrated circuit area and the surface away from the integrated circuit area both arc-shaped. The arc-shaped surface has a larger interception area than the flat surface, so that the sealing ring of the embodiment of the present invention can more effectively prevent moisture and ions from entering the integrated circuit area and prevent cracks from propagating toward the integrated circuit area, thereby significantly improving the protective effect of the sealing ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0037] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0038] Figure 2 It shows Figure 1 A partial enlarged view of the first embodiment at K in FIG.

[0039] Figure 3 It shows Figure 1 A partial enlarged view of the second embodiment at K in FIG.

[0040] Figure 4 It shows Figure 3 A partial enlarged view of one embodiment of the finger-shaped portion at the middle L.

[0041] Figure 5 It shows Figure 1 A partial enlarged view of the third embodiment at K in the figure.

[0042] Figure 6 It shows Figure 1 A partial enlarged view of the fourth embodiment at K in the figure.

[0043] Figures 7 to 13 FIG. 1 shows a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention at different process stages. Figures 7 to 11 It shows Figure 2 The cross-sectional view along AA, Fig.12 and Fig.13 It shows Figure 5 Cross-sectional view along BB.

[0044] The reference numerals are described as follows:

[0045] 100, semiconductor substrate 110, integrated circuit region

[0046] 120, groove 200, sealing ring

[0047] 201, space 210, finger-shaped part

[0048] 211, curved surface 220, crest part

[0049] 230, valley portion 300, mask layer

[0050] 400, barrier layer 500, metal layer DETAILED DESCRIPTION

[0051] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0052] Semiconductor devices are typically provided with a seal ring that extends around the periphery of an integrated circuit region of the semiconductor device. The seal ring is typically a continuous ring of one or more metal layers. In one or more example embodiments, the seal ring may have one or more of the following functions: providing protection to prevent external moisture from entering an integrated circuit component formed in the semiconductor device. Providing protection to prevent ions from invading an integrated circuit component formed in a substrate, and providing a protective structure to prevent cracks from propagating in the substrate toward the region where the integrated circuit component is located inwardly of the seal ring.

[0053] Embodiments of the present invention may be used in any suitable semiconductor device using a seal ring, such as a complementary metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor device, a p-type metal oxide semiconductor device, an n-type metal oxide semiconductor device, a fin field effect transistor, a fully wound gate metal oxide semiconductor field effect transistor such as a nanowire device or a nanosheet device, or other multi-gate field effect transistor. The semiconductor device may be fabricated during the processing of an integrated circuit or a portion thereof (which may include static random access memory and / or logic circuits, passive components such as resistors, capacitors, or inductors, and active components such as p-type field effect transistors, n-type field effect transistors, fin field effect transistors, complementary metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, or combinations thereof).

[0054] like Figure 1 As shown, Figure 1 The figure shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor device according to the embodiment of the present invention comprises a semiconductor substrate 100, an integrated circuit region 110 formed in the semiconductor substrate 100, and a plurality of sealing rings 200, wherein the plurality of sealing rings 200 are disposed in the semiconductor substrate 100 and arranged around the periphery of the integrated circuit region 110 to protect the integrated circuit region 110. The sealing rings 200 have a wavy structure.

[0055] One or more active devices (eg, transistors, diodes, photodiodes, etc.), one or more passive devices (eg, resistors, capacitors, inductors, etc.), or a combination thereof may be disposed in the integrated circuit region 110 .

[0056] A plurality of sealing rings 200 surround the periphery of the integrated circuit region 110 and achieve at least one of the following functions: preventing moisture from entering the integrated circuit elements formed in the substrate of the integrated circuit region 110, preventing ions from entering the integrated circuit elements formed in the substrate, and preventing cracks in the substrate from propagating toward the inner area of ​​the sealing ring 200 where the integrated circuit elements are located.

[0057] Compared with the shape of the sealing ring in the prior art, the sealing ring 200 in the embodiment of the present invention has a wavy structure. The wavy structure makes the surface of the sealing ring 200 facing the integrated circuit area 110 and the surface away from the integrated circuit area 110 both have arc-shaped surfaces. The arc-shaped surface has a larger interception area than the flat surface, so that the sealing ring 200 in the embodiment of the present invention can more effectively prevent moisture and ions from entering the integrated circuit area 110 and prevent cracks from propagating toward the integrated circuit area 110, thereby significantly improving the protective effect of the sealing ring 200.

[0058] like Figure 2 As shown, Figure 2 It shows Figure 1 The semiconductor device of the embodiment of the present invention comprises four sealing rings 200 which are sequentially arranged around the periphery of the integrated circuit region 110 .

[0059] The sealing ring 200 of the embodiment of the present invention includes a plurality of crests 220 and a plurality of troughs 230, which are alternately arranged, each crest 220 is convexly arranged toward the integrated circuit region 110, and each trough 230 is convexly arranged away from the integrated circuit region 110. The curvatures of the plurality of crests 220 are the same, and the curvatures of the plurality of troughs 230 are the same. The curvatures of each crest 220 and each trough 230 are the same.

[0060] By designing that the plurality of crests 220 and the plurality of troughs 230 of the sealing ring 200 have the same shape and the same curvature, the interception area of ​​each crest 220 and each trough 230 of each sealing ring 200 is substantially the same and uniform, thereby avoiding the occurrence of different interception areas and sudden changes that cause different structural strengths, which ultimately lead to easy damage at the sudden changes. In addition, the identical and uniform structure of the sealing ring 200 is also convenient for processing.

[0061] Of course, it is understandable that the plurality of crest portions 220 and the plurality of trough portions 230 of the sealing ring 200 may also adopt the following deformation structures, for example:

[0062] The curvatures of the multiple peaks 220 on a sealing ring 200 may be different, and the curvatures of the multiple troughs 230 on a sealing ring 200 may be different; or, the curvatures of the multiple peaks 220 on a sealing ring 200 are the same, while the curvature of the peaks 220 is different from the curvature of the troughs 230.

[0063] Of course, the sealing ring 200 mentioned above may also at least partially have a wavy structure.

[0064] like Figure 2As shown, the semiconductor device according to the embodiment of the present invention has four sealing rings 200. The four sealing rings 200 may be arranged at equal intervals or at unequal intervals.

[0065] Of course, it should be understood that the number of the sealing rings 200 in the embodiment of the present invention is not limited to the above four, for example, it can also be one, two, three, or more than five.

[0066] The multiple peaks 220 of one of the two adjacent sealing rings 200 are arranged correspondingly to the multiple peaks 220 of the other sealing ring 200. The multiple troughs 230 of one of the two adjacent sealing rings 200 are arranged correspondingly to the multiple troughs 230 of the other sealing ring 200.

[0067] By the design that the multiple peaks 220 of one sealing ring 200 are arranged correspondingly with the multiple peaks 220 of another sealing ring 200 and the multiple troughs 230 of one sealing ring 200 are arranged correspondingly with the multiple troughs 230 of another sealing ring 200, when multiple sealing rings 200 are arranged side by side, more space can be saved, which is conducive to reducing the size of the semiconductor device.

[0068] like Figure 3 As shown, Figure 3 It shows Figure 1 A partial enlarged view of the second embodiment at K in the figure. In the embodiment of the present invention, one of the two adjacent sealing rings 200 includes a plurality of finger-shaped portions 210 , and the finger-shaped portions 210 extend toward the other sealing ring 200 and are not connected to the other sealing ring 200 .

[0069] The number of the multiple finger-shaped portions 210 on a sealing ring 200 may be the same as the number of the crest portions 220, and the multiple finger-shaped portions 210 may be respectively arranged at the vertices of the multiple crest portions 220. Through the design of the finger-shaped portions 210, the interception area of ​​the sealing ring 200 may be further increased, which helps to improve the protection effect of the sealing ring 200.

[0070] Of course, it is understandable that the above-mentioned multiple finger-shaped portions 210 may not be arranged at the apexes of the multiple peak portions 220, but may be arranged at other areas of the peak portions 220; or, the multiple finger-shaped portions 210 may be arranged at the bottom points of the multiple trough portions 230 respectively; or, the multiple finger-shaped portions 210 may be arranged at other areas of the multiple trough portions 230 except the bottom points.

[0071] like Figure 4 As shown, Figure 4 It shows Figure 3A partial enlarged view of an embodiment of the finger-shaped portion 210 at L in the middle. The finger-shaped portion 210 of the embodiment of the present invention has an arc surface 211, and the arc surface 211 faces another sealing ring 200. Since the surface area of ​​the arc surface 211 is larger than that of the plane, the interception area of ​​the sealing ring 200 is further increased, and the protection effect of the sealing ring 200 is further improved.

[0072] Of course, in other embodiments, the finger-shaped portion 210 may also have a surface of other shapes.

[0073] like Figure 5 As shown, Figure 5 It shows Figure 1 A partial enlarged view of the third embodiment at K in the middle. Two adjacent sealing rings 200 of the embodiment of the present invention are connected by a plurality of finger-shaped portions 210. The plurality of finger-shaped portions 210 between two adjacent sealing rings 200 are arranged at intervals around the periphery of the integrated circuit region 110.

[0074] The design of connecting two adjacent sealing rings 200 with a plurality of finger-shaped portions 210 makes it possible for the plurality of sealing rings 200 to form a mesh structure rather than being independently arranged. The sealing rings 200 with the mesh structure are more solid and have a stronger protective effect.

[0075] like Figure 6 As shown, Figure 6 It shows Figure 1 A partial enlarged view of the fourth embodiment at K in the middle. The multiple peaks 220 of one of the two adjacent sealing rings 200 of the embodiment of the present invention are arranged correspondingly with the multiple troughs 230 of the other sealing ring 200. The multiple troughs 230 of one of the two adjacent sealing rings 200 are arranged correspondingly with the multiple peaks 220 of the other sealing ring 200.

[0076] In this way, in the cross section perpendicular to the plurality of sealing rings 200, the crests 220 and the troughs 230 are arranged alternately. When the crack propagates into the integrated circuit region 110, the space 201 between the crest 220 of one sealing ring 200 and the trough 230 of another sealing ring 200 becomes larger due to the alternating arrangement of the convex surface of the crest 220 and the concave surface of the trough 230. When the crack propagates inward, it needs to pass through the crest 220 / space 201 / trough 230 / crest 220 / space 201 in sequence. This structural design is more helpful in preventing cracks, ions or moisture from propagating inward.

[0077] Of course, it is understandable that the two adjacent sealing rings 200 may also be staggered in addition to the corresponding arrangement of the crests 220 and troughs 230 , for example, one sealing ring 200 and the other adjacent sealing ring 200 are staggered up and down by a certain distance.

[0078] In addition, it is understandable that Figure 6 The embodiment shown may also be provided with a plurality of finger-shaped portions 210. The finger-shaped portion 210 may extend from one sealing ring 200 to another sealing ring 200 without being connected to the other sealing ring 200. Alternatively, the finger-shaped portion 210 may be connected to two adjacent sealing rings 200. The structure and advantages of the finger-shaped portion 210 are similar to those described above. Figure 4 and Figure 6 The embodiments shown are the same and will not be described again here.

[0079] Combine the following Figures 7 to 13 , a method for manufacturing a semiconductor device according to an embodiment of the present invention is described in detail. Figures 7 to 13 FIG. 1 shows a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention at different process stages. Figures 7 to 11 It shows Figure 2 The cross-sectional view along AA, Fig.12 and Fig.13 It shows Figure 5 Cross-sectional view along BB.

[0080] like Figure 7 As shown, a semiconductor substrate 100 having an integrated circuit region 110 is provided, and one or more trenches 120 are formed on the semiconductor substrate 100 . The trenches 120 are arranged around the periphery of the integrated circuit region 110 .

[0081] In one embodiment, the semiconductor substrate 100 may include a semiconductor material such as base silicon or single crystal silicon. In other embodiments or additional embodiments, the semiconductor substrate 100 may include another semiconductor element such as germanium in a crystalline structure. The semiconductor substrate 100 may also include a semiconductor compound such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof. The semiconductor substrate 100 may also include a semiconductor substrate on an insulating layer 100 such as a silicon substrate on an insulating layer, a silicon germanium substrate on an insulating layer, or a germanium substrate on an insulating layer.

[0082] In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the semiconductor substrate 100 includes silicon or other elemental semiconductor materials, such as germanium. The semiconductor substrate 100 may be doped (e.g., P-type, N-type, or a combination thereof) or undoped. In some embodiments, the semiconductor substrate 100 includes a semiconductor layer epitaxially grown on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0083] In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V compound semiconductors having a structure of Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The composition defined as follows, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions. Each of them is greater than or equal to 0, and the sum of the whole is equal to 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors or a combination of the foregoing. Other suitable substrates containing II-VI compound semiconductors may also be used.

[0084] In some embodiments, the semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor-on-insulator substrate can be manufactured using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other suitable processes, or a combination thereof. In some other embodiments, the semiconductor substrate 100 includes a multilayer structure. For example, the semiconductor substrate 100 includes a silicon germanium layer formed on a bulk silicon layer.

[0085] The method of forming one or more trenches 120 may include depositing a mask layer 300 on the semiconductor substrate 100, wherein the mask layer 300 defines the one or more trenches 120. In one embodiment, the mask layer 300 may be a photoresist.

[0086] like Figure 8As shown, after a mask layer 300 is deposited on the semiconductor substrate 100, etching is performed to form the above-mentioned trench 120. In one embodiment, etching can be performed by any currently known or later developed technology suitable for removing materials, including but not limited to: dry etching process (e.g., plasma etching, plasma-free gas etching, sputtering etching, ion milling, reactive ion etching (RIE); or wet etching process (e.g., applying acid, alkali, or solvent to dissolve a part of the structure, or using an abrasive formulation to grind away a part of the structure).

[0087] like Fig. 9 As shown, after the trench 120 is formed, a barrier layer 400 conforming to the surface of the trench 120 is formed on the surface of the trench 120. In one embodiment, the barrier layer 400 may be formed by using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, a plasma-assisted chemical vapor deposition process, an electroplating process, an electroless plating process, a spin coating process, one or more other suitable processes, or a combination thereof.

[0088] In one embodiment, the barrier layer 400 may include titanium nitride (TiN) or other suitable materials.

[0089] like Fig.10 As shown, after forming the barrier layer 400, a metal layer 500 is formed on the barrier layer 400. In one embodiment, the metal layer 500 may include tungsten or aluminum.

[0090] In one embodiment, the metal layer 500 may be formed using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, a plasma-assisted chemical vapor deposition process, an electroplating process, an electroless plating process, a spin coating process, one or more other suitable processes, or a combination of the foregoing.

[0091] like Fig.11 As shown, after the metal layer 500 is formed, a portion of the metal layer 500 and a portion of the barrier layer 400 are removed to form the sealing ring 200. In one embodiment, the removal of a portion of the metal layer 500 and a portion of the barrier layer 400 may be performed by a chemical mechanical polishing process, a grinding process, an etching process, a dry polishing process, a wet cleaning process, one or more other suitable processes, or a combination of the foregoing.

[0092] like Fig.12 and Fig.13 As shown, Fig.12 and Fig.13 It shows Figure 5 The cross-sectional view along the middle line BB. Fig.12It is shown that after the trench 120 is formed on the semiconductor substrate 100 , a barrier layer 400 and a metal layer 500 are formed in sequence. Fig.13 FIG. 2 shows the formation of the sealing ring 200 after removing part of the barrier layer 400 and the metal layer 500. Since the two adjacent sealing rings 200 at the BB are connected by the finger portion 210, the metal layer 500 formed on the barrier layer 400 only shows two sealing rings 200, and compared with FIG. Fig.11 The width of the sealing ring 200 is wider.

[0093] In summary, the advantages and beneficial effects of the semiconductor device and the manufacturing method thereof according to the embodiments of the present invention are:

[0094] The sealing ring 200 of the embodiment of the present invention has a wavy structure, which makes the surface of the sealing ring 200 facing the integrated circuit area 110 and the surface away from the integrated circuit area 110 both have arc-shaped surfaces. The arc-shaped surface has a larger interception area than the flat surface, so that the sealing ring 200 of the embodiment of the present invention can more effectively prevent moisture and ions from entering the integrated circuit area 110 and prevent cracks from propagating toward the integrated circuit area 110, thereby significantly improving the protective effect of the sealing ring 200.

[0095] It should be noted that the semiconductor device and the method for making the same shown in the drawings and described in this specification are only an example of the principles of the present invention. It should be clearly understood by those skilled in the art that the principles of the present invention are not limited to any details or any components of the devices shown in the drawings or described in the specification.

[0096] It should be understood that the present invention is not limited in its application to the detailed structure and arrangement of the components proposed in this specification. The present invention can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present invention. It should be understood that the present invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for implementing the present invention and will enable those skilled in the art to utilize the present invention.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor substrate; an integrated circuit region formed in the semiconductor substrate; as well as A sealing ring is provided in the semiconductor substrate and arranged around the periphery of the integrated circuit region to protect the integrated circuit region; wherein the sealing ring has a wavy structure; The sealing ring comprises a plurality of wave crests and a plurality of wave troughs, wherein the plurality of wave crests and the plurality of wave troughs are arranged alternately; The number of the sealing rings is at least two, and one of the two adjacent sealing rings comprises a plurality of finger-shaped portions, and the finger-shaped portions extend toward the direction of the other sealing ring; The plurality of finger-shaped portions are respectively arranged at the apexes of the plurality of wave crest portions, or the plurality of finger-shaped portions are respectively arranged at the bottom points of the plurality of wave trough portions.

2. The semiconductor device according to claim 1, wherein: The finger-shaped portion is connected to two adjacent sealing rings, so that at least two sealing rings form a mesh structure.

3. The semiconductor device according to claim 1, wherein: The finger portion has an arcuate surface, and the arcuate surface faces the other sealing ring.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a barrier layer disposed between the semiconductor substrate and the sealing ring.

5. A method for manufacturing a semiconductor device, characterized in that: The steps include: providing a semiconductor substrate having an integrated circuit region; forming a groove on the semiconductor substrate, wherein the groove is arranged around the periphery of the integrated circuit region; as well as forming a sealing ring in the groove, wherein the sealing ring has a wavy structure; The sealing ring comprises a plurality of wave crests and a plurality of wave troughs, wherein the plurality of wave crests and the plurality of wave troughs are arranged alternately; The number of the sealing rings is at least two, and one of the two adjacent sealing rings comprises a plurality of finger-shaped portions, and the finger-shaped portions extend toward the direction of the other sealing ring; The plurality of finger-shaped portions are respectively arranged at the apexes of the plurality of wave crest portions, or the plurality of finger-shaped portions are respectively arranged at the bottom points of the plurality of wave trough portions.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: Before forming a sealing ring in the groove, the method further includes: A barrier layer is formed conformally to the surface of the trench.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The finger-shaped portion is connected to two adjacent sealing rings, so that at least two sealing rings form a mesh structure.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The finger portion has an arcuate surface, and the arcuate surface faces the other sealing ring.

Images