Monitoring methods for solar cells

Abstract

The present application provides a monitoring method for solar cells, comprising selecting a test piece, preparing a doped polysilicon layer on the surface of the test piece, wherein the doped polysilicon layer has the same doping type as the test piece; and then using a four-probe method to measure the square resistance R total , combined with the test piece's own square resistance R Si The square resistance R of the doped polysilicon layer is calculated as poly‑Si The present application adopts a four-probe method to test the square resistance of the doped polysilicon layer, and the on-site feedback is more timely; and by selecting a suitable test piece to monitor the doping concentration and preparation process of the doped polysilicon layer, the uneven resistivity distribution of the silicon wafer itself is avoided to affect the test results, which can effectively improve the test accuracy.

Description

Technical Field

[0001] The present application relates to the technical field of solar cell production and testing, and in particular to a monitoring method for solar cells. Background Art

[0002] Crystalline silicon solar cells still occupy an important position in the photovoltaic market. With the rapid development of the photovoltaic industry, the domestic and foreign markets have higher and higher requirements for battery efficiency, which has also prompted many manufacturers to actively develop and research high-efficiency batteries. As we all know, the surface recombination loss of the battery is a key factor restricting the improvement of battery efficiency. For example, PERC batteries increase the battery conversion efficiency by adding a passivation film on the back of the battery to reduce the recombination of surface carriers. The TOPCon (Tunnel Oxide Passivated Contact) battery launched in recent years in the industry is a super-thin tunnel oxide layer and a doped polysilicon layer on the back of the battery, which together form a passivation contact structure, which can greatly reduce the surface recombination and metal recombination on the back, thereby greatly improving the open circuit voltage Voc and conversion efficiency of the battery.

[0003] During the preparation of the TOPCon battery, the doped polysilicon layer can be prepared by thermal diffusion or ion implantation, among which the doping concentration of phosphorus atoms and the degree of damage to the tunneling oxide layer determine the back passivation effect and directly affect the battery efficiency. Therefore, in actual production, it is necessary to monitor the doping concentration of the phosphorus-doped polysilicon layer on the back of the battery in real time. There are currently two main methods for detecting the doping concentration of the doped polysilicon layer: one is to use the four-probe method to directly test the square resistance of the back of the doped silicon wafer; the other is to clean and remove the phosphorus silicon glass (PSG) on the back of the silicon wafer, and then use the electrochemical capacitance voltage method (ECV) to test and obtain the phosphorus doping curve.

[0004] However, the above methods all have shortcomings. The former forms a high-low junction between the doped polysilicon layer and the N-type silicon wafer, and the back side resistance tested by the four-probe method is actually the test result of the doped polysilicon layer and the silicon substrate in parallel; and the body resistivity distribution of the N-type silicon wafer is relatively scattered, and the test results are difficult to accurately reflect the severity of phosphorus doping. The latter takes too long, and it is difficult to timely feedback the actual status of the production line during actual mass production, so it is not very realistic to apply it on site.

[0005] In view of this, it is necessary to provide a new monitoring method for solar cells. Summary of the invention

[0006] The purpose of the present application is to provide a monitoring method for solar cells, which can provide timely feedback and monitoring of the doping concentration and preparation process of a doped polysilicon layer and ensure the accuracy of the test results.

[0007] To achieve the above-mentioned purpose of the invention, the embodiment of the present application provides a method for monitoring a solar cell, which mainly includes:

[0008] Select the test piece;

[0009] Prepare a doped polysilicon layer on the surface of the test piece, wherein the doped polysilicon layer has the same doping type as the test piece;

[0010] The square resistance R of the test piece was measured by the four-probe method. total ;

[0011] According to the formula The square resistance R of the doped polysilicon layer is calculated poly-Si , R Si is the square resistance of the test piece itself.

[0012] As a further improvement of the embodiment of the present application, the step of “selecting a test piece” includes providing a silicon piece;

[0013] Set up several test areas;

[0014] The resistivity ρ of several different test areas was obtained through testing;

[0015] When the resistivity ρ of each of the test areas is within a predetermined threshold range, the silicon wafer can be used as a test wafer;

[0016] If the resistivity ρ of any of the test areas exceeds the threshold range, the silicon wafer cannot be used as a test wafer.

[0017] As a further improvement of the embodiment of the present application, the threshold range of the resistivity ρ of the test area in the step of “selecting a test piece” is set to 1.0 to 1.1 Ω·cm.

[0018] As a further improvement of the embodiment of the present application, the resistivity ρ of the test area is measured by a four-probe method, and the number of the test areas of the silicon wafer is set to be no less than 5.

[0019] As a further improvement of the embodiment of the present application, the square resistance R of different test areas of the silicon wafer used as the test piece is measured by a four-probe method. □ Carry out testing; obtain the square resistance R of different test areas □ The average value is taken as the test piece's own square resistance R Si ;or,

[0020] The resistivity ρ of different test areas of the silicon wafer used as the test piece is detected by a four-probe method; the average value ρ' of the resistivity ρ of different test areas is obtained; and the self-square resistance R of the test piece is calculated according to the thickness w of the silicon wafer. Si , R Si =ρ' / w.

[0021] As a further improvement of the embodiment of the present application, the square resistance R total Cleaning the test piece to be tested to remove the doped polysilicon layer on the surface of the test piece;

[0022] The four-probe method is then used to measure the self-square resistance R of the test piece. Si .

[0023] As a further improvement of the embodiment of the present application, the monitoring method further includes preparing a tunneling layer on the surface of the test piece, and the tunneling layer is located between the test piece and the doped polysilicon layer.

[0024] As a further improvement of the embodiment of the present application, the monitoring method further includes setting the square resistance R of the doped polysilicon layer according to the thickness of the doped polysilicon layer. poly-Si The monitoring scope;

[0025] If the square resistance R poly-Si The preparation process of the doped polysilicon layer is normal if the layer is within the monitoring range;

[0026] If the square resistance R poly-Si It is beyond the monitoring range and the preparation process of the doped polysilicon layer is abnormal.

[0027] As a further improvement of the embodiment of the present application, the thickness of the doped polysilicon layer is between 140 and 150 μm; the sheet resistance R poly-Si The monitoring range is set to 60~70ohm / sq.

[0028] As a further improvement of the embodiment of the present application, the square resistance of at least two different positions of the test piece is measured, and then the average value of the square resistance of at least two different positions of the test piece is calculated as the square resistance R total .

[0029] As a further improvement of the embodiment of the present application, the test wafer is an N-type silicon wafer; and the doped polysilicon layer is a phosphorus-doped polysilicon layer.

[0030] The beneficial effects of the present invention are as follows: by adopting the monitoring method of the present application and using a four-probe method to test the square resistance of the doped polysilicon layer, it is possible to quickly determine whether the doping concentration and the preparation process of the doped polysilicon layer are normal, thereby achieving rapid on-site feedback; and by selecting a suitable test piece for monitoring, it is possible to avoid the uneven resistivity distribution of the silicon wafer itself affecting the test results, thereby effectively improving the test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the main process of the monitoring method of the solar cell of the present invention. DETAILED DESCRIPTION

[0032] The present application will be described in detail below in conjunction with the implementation shown in the accompanying drawings. However, the implementation does not limit the present application, and any structural, methodological, or functional changes made by a person of ordinary skill in the art based on the implementation are all included in the protection scope of the present application.

[0033] Ginseng Figure 1 As shown, the solar cell monitoring method provided by the present application includes:

[0034] Select the test piece;

[0035] Placing the test piece at a predetermined position, and preparing a doped polysilicon layer on the surface of the test piece, wherein the doped polysilicon layer has the same doping type as the test piece;

[0036] The square resistance R of the test piece was measured by the four-probe method. total ;

[0037] According to the formula The square resistance R of the doped polysilicon layer is calculated poly-Si , R Si is the square resistance of the test piece itself.

[0038] In this embodiment, the test piece is an N-type silicon piece, and the doped polysilicon layer is a phosphorus-doped polysilicon layer. total It can be regarded as the test result of the doped polysilicon layer and the N-type silicon wafer being connected in parallel, thus satisfying That is, when the square resistance R is measured total After that, combined with the test piece’s own square resistance R Si The square resistance R of the doped polysilicon layer can be calculated. poly-Si ; Then through the square resistance R of the doped polysilicon layer poly-Si Of course, the predetermined position refers to the process position for preparing the doped polysilicon layer, which can be adjusted and determined according to different production equipment and temperature zone settings.

[0039] The step of "selecting a test piece" specifically includes:

[0040] Provide silicon wafers;

[0041] Setting a plurality of test areas on the silicon wafer, wherein the number of the test areas is set to be no less than 5;

[0042] The resistivity ρ of several different test areas was obtained by using the four-probe method;

[0043] When the resistivity ρ of each of the test areas is within a predetermined threshold range, the silicon wafer can be used as a test wafer;

[0044] If the resistivity ρ of any of the test areas exceeds the threshold range, the silicon wafer cannot be used as a test wafer.

[0045] Wherein, in the step of "selecting a test piece", the threshold range of the resistivity ρ of the test area is set to 1.0 to 1.1 Ω·cm.

[0046] In order to ensure that the surface morphology of the test piece is consistent with that of the actual produced cell, the silicon wafer used as the test piece can usually be surface treated with an acid / alkali solution, and then a tunneling layer is prepared on the back of the test piece. The tunneling layer is located between the test piece and the doped polysilicon layer. The tunneling layer is usually set as a SiO2 film layer or SiO x N y The thickness of the tunneling layer is set to 0.5-3 nm, and the specific preparation process is not described here any more.

[0047] The test piece's own square resistance R Si Obtained by the following method:

[0048] The four-probe method is used to measure the square resistance R of different test areas of the silicon wafer used as a test piece. □ Carry out testing; obtain the square resistance R of different test areas □ The average value is taken as the test piece's own square resistance R Si ;or,

[0049] The resistivity ρ of different test areas of the silicon wafer used as the test piece is detected by a four-probe method; the average value ρ' of the resistivity ρ of different test areas is obtained; and the self-square resistance R of the test piece is calculated according to the thickness w of the silicon wafer. Si , R Si =ρ' / w.

[0050] In other embodiments of the present application, the square resistance R total The tested test piece is cleaned to remove the doped polysilicon layer on the surface of the test piece; and the square resistance R of the test piece itself is measured by the four-probe method. Si That is to say, the square resistance of the test piece itself is R Si The test can be performed before preparing the doped polysilicon layer, or the test can be performed after preparing the doped polysilicon layer and then cleaning and testing.

[0051] In addition, the square resistance R total It can also be obtained by detecting the square resistances of at least two different positions on the test piece, and then calculating the average value of the square resistances of at least two different positions on the test piece.

[0052] The monitoring method further includes setting the square resistance R of the doped polysilicon layer according to the thickness of the doped polysilicon layer poly-Si The monitoring scope;

[0053] If the square resistance R poly-Si If the doping concentration and the preparation process of the doped polysilicon layer are within the monitoring range, it is determined that the doping concentration and the preparation process of the doped polysilicon layer are normal;

[0054] If the square resistance R poly-Si If the doping concentration and the preparation process of the doped polysilicon layer are beyond the monitoring range, it is determined that there is an abnormality.

[0055] As an example, when the thickness of the doped polysilicon layer is between 140 μm and 150 μm, the square resistance R of the doped polysilicon layer is poly-Si The monitoring range is set to 60-70 ohm / sq. That is, the square resistance R poly-Si Whether the doping concentration and process of the doped polysilicon layer are abnormal can be quickly determined on site by taking whether the doping concentration and process of the doped polysilicon layer are abnormal.

[0056] To summarize, the monitoring method of the present application uses a four-probe method to test the square resistance of the doped polysilicon layer, which can quickly determine whether the doping concentration and preparation process of the doped polysilicon layer are normal, and realize rapid on-site feedback; and by selecting appropriate test pieces for monitoring, it can avoid the uneven resistivity distribution of the silicon wafer itself affecting the test results, thereby better ensuring the test accuracy.

[0057] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0058] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present application. They are not intended to limit the scope of protection of the present application. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present application should be included in the scope of protection of the present application.

Claims

1. A method for monitoring a solar cell, characterized in that: Select the test piece; A doped polysilicon layer and a tunneling layer are prepared on the surface of the test piece, wherein the doped polysilicon layer has the same doping type as the test piece, and the tunneling layer is located between the test piece and the doped polysilicon layer; and the square resistance R of the test piece is measured by a four-probe method. total ; According to the formula The square resistance Rpoly-Si of the doped polysilicon layer is calculated, where RSi is the square resistance of the test piece itself; Wherein, the step of "selecting a test piece" includes providing a silicon piece; Set up several test areas; The resistivity ρ of several different test areas was obtained by testing; When the resistivity ρ of each of the test areas is within a predetermined threshold range, the silicon wafer can be used as a test wafer; If the resistivity ρ of any of the test areas exceeds the threshold range, the silicon wafer cannot be used as a test wafer.

2. The monitoring method according to claim 1, characterized in that: The threshold range of the resistivity ρ of the test area in the step of "selecting a test piece" is set to 1.0 to 1.1 Ω·cm.

3. The monitoring method according to claim 1, characterized in that: The resistivity ρ of the test area is measured by a four-probe method, and the number of the test areas of the silicon wafer is set to be no less than 5.

4. The monitoring method according to any one of claims 1 to 3, characterized in that: Using a four-probe method to detect the square resistance R□ of different test areas of the silicon wafer used as a test piece; calculating the average value of the square resistance R□ of different test areas as the square resistance RSi of the test piece itself; or, The resistivity ρ of different test areas of the silicon wafer used as a test piece is detected by a four-probe method; the average value ρ' of the resistivity ρ of different test areas is calculated; and the self-square resistance RSi of the test piece is calculated according to the thickness w of the silicon wafer, RSi = ρ' / w.

5. The monitoring method according to claim 1, characterized in that: Cleaning the test piece after the square resistance Rtotal test to remove the doped polysilicon layer on the surface of the test piece; The four-probe method is then used to measure the self-square resistance RSi of the test piece.

6. The monitoring method according to claim 1, characterized in that: The monitoring method further comprises setting a monitoring range of the square resistance Rpoly-Si of the doped polysilicon layer according to the thickness of the doped polysilicon layer; If the square resistance Rpoly-Si of the doped polysilicon layer is within the monitoring range, the preparation process of the doped polysilicon layer is normal; If the square resistance Rpoly-Si of the doped polysilicon layer exceeds the monitoring range, the preparation process of the doped polysilicon layer is abnormal.

7. The monitoring method according to claim 6, characterized in that: The thickness of the doped polysilicon layer is between 140 and 150 μm; the monitoring range of the square resistance Rpoly-Si of the doped polysilicon layer is set to 60 to 70 ohm / sq.

8. The monitoring method according to claim 1, characterized in that: The sheet resistances of at least two different positions of the test piece are measured, and then the average value of the sheet resistances of at least two different positions of the test piece is calculated as the sheet resistance Rtotal.

9. The monitoring method according to claim 1, characterized in that: The test piece is an N-type silicon piece; the doped polysilicon layer is a phosphorus-doped polysilicon layer.

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