Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate having a fin, the fin including a device region and an isolation region; forming an isolation layer on the substrate; forming a first gate structure on the substrate, the first gate structure including a first region and a second region located on the first region; removing the second region to form an initial first opening; removing the isolation region to form a second opening; removing the first region to form a first opening; forming an isolation structure in the first opening and the second opening. In the process of forming the first opening and the second opening, the isolation layer is not etched to remove, so that the stress of the fin located in the device region will not change, and thus the performance of the transistor structure located in the device region will not be reduced. In addition, in the process of etching to remove the isolation region, the isolation layer is covered by the first region, so that the isolation layer can be prevented from being etched and damaged, and thus the stress of the device region will not change, thereby improving the performance of the semiconductor structure finally formed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As the integration of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, as the size of transistors decreases dramatically, the thickness of the gate dielectric layer and the operating voltage cannot change accordingly, making it more difficult to suppress the short channel effect and increasing the channel leakage current of the transistor.

[0003] The gate of the Fin Field-Effect Transistor (FinFET) is a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewalls of the fin, so that an inversion layer is formed on each side of the channel, which can control the connection and disconnection of the circuit on both sides of the fin. This design can increase the control of the gate over the channel region, thereby effectively suppressing the short channel effect of the transistor. However, the Fin Field-Effect Transistor still has a short channel effect.

[0004] In addition, in order to further reduce the impact of the short channel effect on semiconductor devices and reduce channel leakage current, strained silicon technology has been introduced into the field of semiconductor technology. The method of strained silicon technology includes: forming grooves in the fins on both sides of the gate structure; and forming source and drain doping layers in the grooves by an epitaxial growth process.

[0005] In order to prevent the source and drain doping layers of different transistors from being connected to each other, an isolation layer needs to be formed in the fin, and in order to reduce the area of ​​the isolation layer and improve the integration of the formed semiconductor structure, the prior art introduces SDB (Single Diffusion Break) technology.

[0006] However, the semiconductor structure formed by the SDB technology introduced in the prior art has poor performance. Summary of the invention

[0007] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.

[0008] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a plurality of fins arranged in parallel along a first direction, the fins comprising a plurality of device regions and an isolation region located between adjacent device regions, the isolation region and the device region being arranged along a second direction, the first direction being perpendicular to the second direction; forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the fins, and a top surface of the isolation layer being lower than a top surface of the fins; forming a first gate structure on the substrate, the first gate structure spanning the isolation region, and the first gate structure covering a portion of the sidewalls and top surface of the isolation region, and the The invention relates to a method for forming a first gate structure comprising a first region located on the isolation layer and a second region located on the first region, wherein the top surface of the first region is lower than the top surface of the fin; forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the sidewalls of the first gate structure; removing the second region, forming an initial first opening in the first dielectric layer to expose the top of the isolation region; removing the isolation region exposed by the initial first opening, and forming a second opening in the isolation layer; after forming the second opening, removing the first region, forming a first opening in the first dielectric layer; and forming an isolation structure in the first opening and the second opening.

[0009] Optionally, before forming the initial first opening, the method further includes: forming a second dielectric layer on the first dielectric layer and the first gate structure.

[0010] Optionally, after removing the first region, the method further includes: etching back a portion of the isolation layer.

[0011] Optionally, a top surface of the first gate structure is lower than a top surface of the first dielectric layer.

[0012] Optionally, the process of forming the first gate structure also includes: forming a plurality of second gate structures on the substrate, the second gate structures spanning the device region, and the second gate structures covering part of the side walls and top surface of the device region, and part of the top surface of the isolation layer.

[0013] Optionally, before forming the first gate structure and the second gate structure, it also includes: forming a plurality of source-drain doped layers in the fin, the source-drain doped layers having source-drain ions, and the source-drain doped layers being located between the adjacent second gate structures, or between the adjacent first gate structures and the second gate structures.

[0014] Optionally, the source and drain ions include N-type ions or P-type ions.

[0015] Optionally, before forming the first gate structure and the second gate structure, it also includes: forming a first dummy gate structure and several second dummy gate structures on the substrate, the first dummy gate structure spans the isolation region, the second dummy gate structure spans the device region, and the first dielectric layer covers the side walls of the first dummy gate structure and the second dummy gate structure.

[0016] Optionally, the method for forming the source-drain doped layer includes: etching the fin using the first dummy gate structure and the second dummy gate structure as masks to form a plurality of source-drain openings in the fin; and forming the source-drain doped layer in the source-drain openings.

[0017] Optionally, the method for forming the source-drain doped layer in the source-drain opening includes: forming an epitaxial layer in the source-drain opening using an epitaxial growth process; and during the formation of the epitaxial layer, doping the source-drain ions into the epitaxial layer using an in-situ doping process to form the source-drain doped layer.

[0018] Optionally, the method for forming the first dielectric layer includes: forming an initial first dielectric layer on the substrate, the initial first dielectric layer covering the first pseudo gate structure and the second pseudo gate structure; and flattening the initial first dielectric layer until the top surfaces of the first pseudo gate structure and the second pseudo gate structure are exposed to form the first dielectric layer.

[0019] Optionally, the process of planarizing the initial first dielectric layer includes: a chemical mechanical polishing process, a wet etching process or a dry etching process.

[0020] Optionally, the method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening and a second gate opening in the first dielectric layer; forming the first gate structure in the first gate opening, and forming the second gate structure in the second gate opening.

[0021] Optionally, the method for forming the isolation structure includes: forming an initial isolation structure in the first opening and the second opening, and on the top surface of the second dielectric layer; and flattening the initial isolation structure until the top surface of the second dielectric layer is exposed to form the isolation structure.

[0022] Optionally, the material of the isolation structure includes silicon oxide or silicon nitride.

[0023] Optionally, the material of the isolation layer includes silicon oxide or silicon nitride.

[0024] Optionally, the first gate structure includes: a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

[0025] Optionally, the second gate structure includes: a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the technical solution formation method of the present invention, the first gate structure is removed to form a first opening in the first dielectric layer; the isolation region is removed to form a second opening in the first dielectric layer. Since the isolation layer is not etched and removed in the process of forming the first opening and the second opening, the stress of the fin located in the device region will not change, and the performance of the transistor structure located in the device region will not be reduced, thereby improving the performance of the semiconductor structure finally formed. Moreover, the process of forming the first opening and the second opening is: first removing the second region to form an initial first opening in the first dielectric layer; after forming the initial first opening, removing the isolation region to form a second opening in the isolation layer; after forming the second opening, removing the first region to form the first opening in the first dielectric layer. Since the isolation layer is covered by the first region in the process of etching and removing the isolation region, it is possible to avoid the isolation layer from being etched and damaged, and the stress of the device region will not change, thereby improving the performance of the semiconductor structure finally formed.

[0028] Furthermore, after removing the first region, the method further includes: etching back a portion of the isolation layer. By etching back a portion of the isolation layer, the stress in the device region is partially released, thereby adjusting the stress in the device region to make it more consistent with the stress requirements of the transistor structure, thereby improving the performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 3 It is a schematic diagram of the structure of a semiconductor structure;

[0030] Figures 4 to 19 It is a schematic diagram of the structures of the steps of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, the semiconductor structure formed by the SDB technology introduced in the prior art has poor performance, which will be described in detail below with reference to the accompanying drawings.

[0032] Please refer to Figure 1 and Figure 2 , Figure 1is a top view of the semiconductor structure. Figure 2 yes Figure 1 A cross-sectional schematic diagram along the AA direction provides a substrate 100, the substrate 100 includes a plurality of device regions A1 and an isolation region B1 located between adjacent device regions A1, the isolation region B1 and the device region A1 are arranged along a first direction X; a plurality of fins 101 arranged in parallel along a second direction Y are formed on the device region A1, the first direction X is perpendicular to the second direction Y, and the fins 101 also span across the isolation region B1; an isolation layer 102 is formed on the substrate 100, the isolation layer 102 covers a portion of the sidewalls of the fins 101, and the top surface of the isolation layer 102 is lower than the top surface of the fins 101; a first gate structure 103 spanning the fins 101 is formed on the isolation region B1, the first gate structure 103 covers a portion of the sidewalls and the top surface of the fins 101; a dielectric layer 104 is formed on the substrate 100, the dielectric layer 104 covers the sidewalls of the first gate structure 103.

[0033] Please refer to Figure 3 , Figure 3 and Figure 2 In the same viewing direction, the first gate structure 103, the isolation layer 102 located on the isolation region B1, and the fin 101 located on the isolation region B1 are removed to form an isolation opening (not marked) in the dielectric layer 104; and an isolation structure 105 is formed in the isolation opening.

[0034] In this embodiment, the isolation structure 105 is used to prevent the subsequently formed source and drain doping layers from being connected to each other, thereby achieving an isolation effect. By removing the first gate structure 103 to form the isolation structure 105, the area occupied by the device structure can be effectively reduced, thereby improving the integration of the semiconductor device.

[0035] In the present embodiment, when the isolation opening is formed, it is necessary to remove the fin 101 located on the isolation area B1. Since in the process of etching and removing the fin 101 on the isolation area B1, the etching process is limited by the aspect ratio of the etching opening, the fin 101 located on the isolation area B1 is not easy to be completely removed. Therefore, in the present embodiment, in the process of removing the fin 101 located in the isolation area B1, the isolation layer located on the isolation area B1 is also removed at the same time, which can effectively increase the aspect ratio of the etching opening, so that the fin 101 located on the isolation area B1 can be completely removed.

[0036] However, when the isolation layer 102 located on the isolation region B1 is removed, the stress of the fin 101 in the device region A1 will change. When a PMOS transistor structure is formed in the device region A1, the PMOS transistor structure requires the fin 101 to provide a certain compressive stress. When the isolation layer 102 located on the isolation region B1 is removed, the compressive stress of the fin 101 in the PMOS transistor structure will be partially released, so that the compressive stress of the fin 101 in the PMOS transistor structure is reduced, thereby affecting the performance of the PMOS transistor structure, and thereby reducing the performance of the finally formed semiconductor structure.

[0037] On this basis, the present invention provides a method for forming a semiconductor structure, wherein a first opening is formed in the first dielectric layer by removing the first gate structure; and a second opening is formed in the first dielectric layer by removing the fin located on the isolation region. Since the isolation layer is not etched and removed in the process of forming the first opening and the second opening, the stress of the fin located in the device region will not change, and the performance of the transistor structure located in the device region will not be reduced, thereby improving the performance of the semiconductor structure finally formed. Moreover, the process of forming the first opening and the second opening is: first removing the second region to form an initial first opening in the first dielectric layer; after forming the initial first opening, removing the isolation region to form a second opening in the isolation layer; after forming the second opening, removing the first region to form the first opening in the first dielectric layer. Since the isolation layer is covered by the first region in the process of etching and removing the isolation region, it is possible to avoid the isolation layer from being etched and damaged, and the stress of the device region will not change, thereby improving the performance of the semiconductor structure finally formed.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 19 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 4 and Figure 5 , Figure 4 is a top view of the semiconductor structure. Figure 5 yes Figure 4A cross-sectional schematic diagram along the BB direction provides a substrate 200, on which a plurality of fins 201 arranged in parallel along a first direction X are provided, wherein the fins 201 include a plurality of device regions A1 and an isolation region B1 located between adjacent device regions A1, wherein the isolation region B1 and the device region A1 are arranged along a second direction Y, and the first direction X and the second direction Y are perpendicular.

[0041] In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, wherein the patterned layer exposes a portion of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200 and the fin 201; after forming the substrate 200 and the fin 201, removing the patterned layer.

[0042] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0043] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0044] Please refer to Figure 6 , Figure 6 and Figure 5 In accordance with the viewing direction, an isolation layer 202 is formed on the substrate 200 , the isolation layer 202 covers a portion of the sidewall of the fin 201 , and the top surface of the isolation layer 202 is lower than the top surface of the fin 201 .

[0045] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200, wherein the initial isolation layer covers the side walls and the top of the fin 201; performing a planarization process on the initial isolation layer until the top surface of the fin 201 is exposed; after the planarization process, etching away a portion of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0046] The material of the isolation layer 202 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation layer 202 is silicon oxide.

[0047] After forming the isolation layer 202, it also includes: forming a first gate structure on the substrate 200, the first gate structure spanning the isolation region B1, and the first gate structure covering part of the sidewalls and top surface of the isolation region B1, and part of the top surface of the isolation layer 202, the first gate structure including a first region located on the isolation layer 202 and a second region located on the first region, the top surface of the first region is lower than the top surface of the fin 201; forming a plurality of second gate structures on the substrate 200, the second gate structures spanning the device region A1, and the second gate structures covering part of the sidewalls and top surface of the device region A1, and part of the top surface of the isolation layer 202; forming a first dielectric layer on the substrate 200, the first dielectric layer covering the sidewalls of the first gate structure and the second gate structure. For the specific formation process, please refer to Figures 7 to 13 .

[0048] Please refer to Figure 7 and Figure 8 , Figure 7 is a top view of the semiconductor structure. Figure 8 yes Figure 7 In the cross-sectional view along the CC direction, a first dummy gate structure 203 and a plurality of second dummy gate structures 204 are formed on the substrate 200 . The first dummy gate structure 203 spans across the isolation region B1 , and the second dummy gate structure 204 spans across the device region A1 .

[0049] In this embodiment, the first dummy gate structure 203 includes a first dummy gate dielectric layer and a first dummy gate layer (not labeled) located on the first dummy gate dielectric layer; the second dummy gate structure includes a second dummy gate dielectric layer and a second dummy gate layer (not labeled) located on the second dummy gate dielectric layer.

[0050] In this embodiment, the material of the first dummy gate dielectric layer and the second dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer and the second dummy gate dielectric layer may also be silicon oxynitride.

[0051] In this embodiment, the material of the first dummy gate layer and the second dummy gate layer is silicon.

[0052] In the present embodiment, the first dummy gate structure 203 and the second dummy gate structure 204 are formed simultaneously. The first dummy gate structure 203 and the second dummy gate structure 204 are formed simultaneously through a global process, which can effectively improve production efficiency.

[0053] In this embodiment, please continue to refer to Figure 7After forming the first dummy gate structure 203 and the second dummy gate structure 204 , a first spacer 205 is formed on the sidewall of the first dummy gate structure 203 ; and a second spacer 206 is formed on the sidewall of the second dummy gate structure 204 .

[0054] In this embodiment, the first sidewall spacer 205 and the second sidewall spacer 206 are made of silicon nitride.

[0055] Please refer to Fig. 9 , Fig. 9 and Figure 7 The viewing direction is consistent, and the fin 201 is etched using the first dummy gate structure 203 and the second dummy gate structure 204 as masks to form a plurality of source and drain openings (not shown) in the fin 201; a source and drain doping layer 207 is formed in the source and drain openings, and the source and drain doping layer 207 has source and drain ions, and the source and drain doping layer 207 is located between the adjacent second dummy gate structures 204, or between the adjacent first dummy gate structures 203 and the second dummy gate structures 204.

[0056] The source and drain ions include N-type ions or P-type ions. In this embodiment, the source and drain ions are P-type ions.

[0057] In this embodiment, the method for forming the source-drain doped layer 207 in the source-drain opening includes: forming an epitaxial layer (not shown) in the source-drain opening by using an epitaxial growth process; and during the process of forming the epitaxial layer, doping the source-drain ions into the epitaxial layer by using an in-situ doping process to form the source-drain doped layer 207.

[0058] Please refer to Fig.10 After forming the source-drain doping layer 207, an initial first dielectric layer (not shown) is formed on the substrate 200, and the initial first dielectric layer covers the first dummy gate structure 203 and the second dummy gate structure 204; the initial first dielectric layer is planarized until the top surfaces of the first dummy gate structure 203 and the second dummy gate structure 204 are exposed, so as to form the first dielectric layer 208.

[0059] In this embodiment, the material of the first dielectric layer 208 is silicon oxide; in other embodiments, the material of the first dielectric layer may also be a low-K dielectric material (a low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (an ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0060] In this embodiment, the process of planarizing the initial first dielectric layer adopts a chemical mechanical polishing process. In other embodiments, the process of planarizing the initial first dielectric layer may also adopt a wet etching process or a dry etching process.

[0061] Please refer to Figures 11 to 13 , Fig.11 is a top view of the semiconductor structure. Fig.12 yes Fig.11 Schematic diagram of the cross section along the DD direction, Fig.13 yes Fig.11 A cross-sectional schematic diagram along the EE direction shows that after forming the first dielectric layer 208, the first dummy gate structure 203 and the second dummy gate structure 204 are removed, and a first gate opening and a second gate opening (not marked) are formed in the first dielectric layer 208; the first gate structure 209 is formed in the first gate opening, the first gate structure 209 spans the isolation region B1, and the first gate structure 209 covers a portion of the sidewall and top surface of the isolation region B1, and a portion of the top surface of the isolation layer 202, the first gate structure 209 includes a first region I located on the isolation layer 202 and a second region II located on the first region I, and the top surface of the first region I is lower than the top surface of the fin 201; the second gate structure 210 is formed in the second gate opening, the second gate structure 210 spans the device region A1, and the second gate structure 210 covers a portion of the sidewall and top surface of the device region A1, and a portion of the top surface of the isolation layer 202.

[0062] In this embodiment, top surfaces of the first gate structure 209 and the second gate structure 210 are lower than a top surface of the first dielectric layer 208 .

[0063] In this embodiment, the first gate structure 209 includes: a first gate dielectric layer and a first gate layer (not labeled) located on the first gate dielectric layer; the second gate structure 210 includes: a second gate dielectric layer and a second gate layer (not labeled) located on the second gate dielectric layer.

[0064] In this embodiment, the material of the first gate dielectric layer and the second gate dielectric layer includes a high-K dielectric material.

[0065] The material of the first gate layer and the second gate layer includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the first gate layer and the second gate layer is tungsten.

[0066] Please refer to Fig.14 , Fig.14 and Fig.12 In accordance with the viewing direction, after forming the first gate structure 209 and the second gate structure 210 , a second dielectric layer 211 is formed on the first dielectric layer 208 , the first gate structure 209 and the second gate structure 210 .

[0067] In this embodiment, the material of the second dielectric layer 211 is silicon oxide; in other embodiments, the material of the second dielectric layer may also be a low-K dielectric material or an ultra-low-K dielectric material.

[0068] Please refer to Fig.15 , Fig.15 and Fig.13 In the same viewing direction, after forming the second dielectric layer 211, the second region II is removed, and an initial first opening 212 exposing the top of the isolation region B1 is formed in the first dielectric layer 208.

[0069] In this embodiment, the second region II is removed first and the first region I is retained. The purpose is to protect the isolation layer 202 through the first region I, avoid damaging the isolation layer 202 when the isolation region B1 is removed later, and thus avoid changing the stress of the device region A1, thereby improving the performance of the semiconductor structure finally formed.

[0070] In this embodiment, the process of removing the second region II adopts a dry etching process; in other embodiments, the process of removing the second region may also adopt a wet etching process.

[0071] Please refer to Fig.16 , the isolation region B1 exposed by the initial first opening 212 is removed, and a second opening 213 is formed in the isolation layer 202 .

[0072] In this embodiment, since the material of the retained first region I has a greater etching selectivity ratio with the material of the isolation region B1 , the isolation region B1 can be removed by using a self-alignment process.

[0073] In this embodiment, the process of removing the isolation region B1 adopts a dry etching process; in other embodiments, the process of removing the isolation region may also adopt a wet etching process.

[0074] Please refer to Fig.17 After forming the second opening 213 , the first region I is removed to form a first opening 214 in the first dielectric layer 208 .

[0075] In this embodiment, the first gate structure 209 is removed to form a first opening 214 in the first dielectric layer 208; the isolation region B1 is removed to form a second opening 213 in the first dielectric layer 208. Since the isolation layer 202 is not etched and removed during the process of forming the first opening 213 and the second opening 214, the stress of the fin 201 in the device region A1 will not change, and the performance of the transistor structure in the device region A1 will not be reduced, thereby improving the performance of the semiconductor structure finally formed.

[0076] In this embodiment, the process of removing the first region I adopts a dry etching process; in other embodiments, the process of removing the first region may also adopt a wet etching process.

[0077] Please refer to Fig.18 After removing the first region I, the method further includes: etching back a portion of the isolation layer 202.

[0078] In this embodiment, the stress in the device area A1 is partially released by etching back part of the isolation layer 202, thereby adjusting the stress in the device area A1 to better meet the stress requirements of the transistor structure, thereby improving the performance of the semiconductor structure finally formed.

[0079] Please refer to Fig.19 After the first opening 213 and the second opening 214 are formed, an isolation structure 215 is formed in the first opening 213 and the second opening 214 .

[0080] In this embodiment, the isolation structure 215 is used to prevent the subsequently formed source-drain doping layers 207 from being connected to each other, thereby achieving an isolation effect. By removing the first gate structure 209 to form the isolation structure 215, the area occupied by the device structure can be effectively reduced, thereby improving the integration of the semiconductor device.

[0081] In this embodiment, the method for forming the isolation structure 215 includes: forming an initial isolation structure (not shown) in the first opening 213 and the second opening 214, and on the top surface of the second dielectric layer 211; and flattening the initial isolation structure until the top surface of the second dielectric layer 211 is exposed, thereby forming the isolation structure 215.

[0082] The material of the isolation structure 215 includes silicon oxide or silicon nitride. In this embodiment, the material of the isolation structure 215 is silicon nitride.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a plurality of fins arranged in parallel along a first direction, the fins comprising a plurality of device regions and an isolation region located between adjacent device regions, the isolation region and the device region being arranged along a second direction, the first direction being perpendicular to the second direction; forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall of the fin, and a top surface of the isolation layer is lower than a top surface of the fin; forming a first gate structure on the substrate, the first gate structure spanning the isolation region and covering a portion of the sidewall and top surface of the isolation region and a portion of the top surface of the isolation layer, the first gate structure comprising a first region located on the isolation layer and a second region located on the first region, the top surface of the first region being lower than the top surface of the fin; forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the sidewalls of the first gate structure; removing the second region and forming an initial first opening in the first dielectric layer to expose the top of the isolation region; removing the isolation region exposed by the initial first opening, and forming a second opening in the isolation layer; After forming the second opening, removing the first region to form a first opening in the first dielectric layer; An isolation structure is formed in the first opening and the second opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the initial first opening, the method further includes: forming a second dielectric layer on the first dielectric layer and the first gate structure.

3. The method for forming a semiconductor structure according to claim 1, wherein: After removing the first region, the method further includes: etching back a portion of the isolation layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: A top surface of the first gate structure is lower than a top surface of the first dielectric layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the first gate structure also includes: forming a plurality of second gate structures on the substrate, the second gate structures spanning the device region, and the second gate structures covering part of the sidewalls and top surface of the device region and part of the top surface of the isolation layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: Before forming the first gate structure and the second gate structure, it also includes: forming a plurality of source-drain doped layers in the fin, the source-drain doped layers having source-drain ions, and the source-drain doped layers are located between adjacent second gate structures, or between adjacent first gate structures and second gate structures.

7. The method for forming a semiconductor structure according to claim 6, wherein: The source and drain ions include N-type ions or P-type ions.

8. The method for forming a semiconductor structure according to claim 6, wherein: Before forming the first gate structure and the second gate structure, it also includes: forming a first dummy gate structure and several second dummy gate structures on the substrate, the first dummy gate structure spans the isolation region, the second dummy gate structure spans the device region, and the first dielectric layer covers the side walls of the first dummy gate structure and the second dummy gate structure.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the source-drain doped layer comprises: etching the fin portion using the first dummy gate structure and the second dummy gate structure as masks to form a plurality of source-drain openings in the fin portion; and forming the source-drain doped layer in the source-drain openings.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the source-drain doped layer in the source-drain opening comprises: forming an epitaxial layer in the source-drain opening by adopting an epitaxial growth process; and doping the source-drain ions into the epitaxial layer by adopting an in-situ doping process during the formation of the epitaxial layer to form the source-drain doped layer.

11. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first dielectric layer includes: forming an initial first dielectric layer on the substrate, the initial first dielectric layer covering the first dummy gate structure and the second dummy gate structure; and flattening the initial first dielectric layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed to form the first dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of planarizing the initial first dielectric layer includes: a chemical mechanical polishing process, a wet etching process or a dry etching process.

13. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening and a second gate opening in the first dielectric layer; forming the first gate structure in the first gate opening, and forming the second gate structure in the second gate opening.

14. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the isolation structure includes: forming an initial isolation structure in the first opening and the second opening and on the top surface of the second dielectric layer; and flattening the initial isolation structure until the top surface of the second dielectric layer is exposed to form the isolation structure.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the isolation structure includes silicon oxide or silicon nitride.

16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the isolation layer includes silicon oxide or silicon nitride.

17. The method for forming a semiconductor structure according to claim 1, wherein: The first gate structure includes: a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

18. The method for forming a semiconductor structure according to claim 5, wherein: The second gate structure includes: a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

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