Prominent memory device with reduced minimum conductance state

Abstract

A memory device can be provided that implements a reduced minimum conductance state. The device includes a first electrode, a second electrode, and a phase change material between the first electrode and the second electrode, where the phase change material implements a plurality of conductance states depending on a ratio between crystalline and amorphous phases of the phase change material. The memory device additionally includes a protruding layer portion in a region between the first electrode and the second electrode. As such, an area directly covered by the phase change material in an amorphous phase in a reset state of the memory device is greater than an area directed to the protruding layer portion of the phase change material, such that a discontinuity in a conductance state of the memory device is created and a reduced minimum conductance state of the memory device in the reset state is implemented.

Description

Technical Field

[0001] This invention generally relates to phase-change memories, and more specifically, to memory devices that achieve a reduced minimum conductance state. Background Technology

[0002] Universities and industry research have been exploring new materials and methods to increase storage density in semiconductor devices while reducing power consumption per unit of stored information. In this context, resistive memory devices such as phase-change memories and conductive bridge memristors, which can switch inversely between multiple conductance states, are becoming increasingly popular for multi-level data storage and for in-memory and neuromorphic computing hardware.

[0003] Several key challenges exist in achieving multilevel, efficiency, drift, and noise. Regarding cell efficiency, the ability to program and read devices at various levels with very low current / power consumption is addressed. Regarding drift and noise, the inherent material physics that negatively impacts resistive readouts must be addressed.

[0004] Recently, these challenges have been addressed using a novel memory cell concept represented as a protruding phase-change memory, in which a phase-change material is adhered to a conductive material called a protruding component. In the protruding memory cell, the physical mechanism of resistive storage is essentially decoupled from the information retrieval process. The read current bypasses the amorphous phase-change material, thus flowing through the drift-free, low-noise, and highly conductive protruding material.

[0005] While the reduced drift and readout noise are highly beneficial, the device concept also has drawbacks. The minimum conductance of the device can be significantly increased. During readout, the device dynamic range can decrease, and idle devices (G-0) can carry more current. Therefore, array energy efficiency may decrease during readout, and network functionality may be compromised if the device cannot be programmed to the proper OFF state (G = 0). Summary of the Invention

[0006] Additional aspects and / or advantages will be set forth in part in the description which follows, and will also be apparent in part from the description, or may be learned by practice of the invention.

[0007] According to one aspect of the invention, a memory device can be provided that achieves a reduced minimum conductivity state. The device may include a first electrode, a second electrode, and a phase change material between the first and second electrodes. Therefore, the phase change material can achieve multiple conductivity states depending on the ratio between the crystalline and amorphous phases of the phase change material.

[0008] The memory device may also include a protruding layer portion in the region between the first electrode and the second electrode. Therefore, in the reset state of the memory device, the region directly covered by the phase change material in the amorphous phase can be larger than the region of the protruding layer portion oriented to the phase change material. This allows for discontinuities in the electrical conductance state of the memory device and enables the realization of a reduced minimum electrical conductance state in the reset state. Attached Figure Description

[0009] From the following description taken in conjunction with the accompanying drawings, the above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will become more apparent, wherein:

[0010] Figure 1 A block diagram illustrating an embodiment of the memory device of the present invention that achieves a reduced minimum conductance state is shown.

[0011] Figure 2 The conductivity diagram presented here, compared to patterned protrusions, is for traditional protrusion linings.

[0012] Figure 3A Showcases outstanding memory device designs.

[0013] Figure 3B This is a table showing the current I that depends on the voltage supplied to the phase change memory cell.

[0014] Figure 4 The cross switches of a neural network unit are shown, which can be used as the basis for programming weights.

[0015] Figure 5 The lateral cell design on the dielectric layer is shown.

[0016] Figure 6 A constrained design of a phase-change memory cell, as another embodiment, is shown.

[0017] Figure 7A and 7B A side-by-side comparison of locally delimited protrusion portions and protrusions with dopant gradients is shown.

[0018] Figure 7C and Figure 7D It shows the relationship with Figure 7A and Figure 7B The resistance of the lining.

[0019] Figure 7E and Figure 7F It shows the relationship with Figure 7A and Figure 7B Different characteristics of the reading current. Detailed Implementation

[0020] The following description, provided with reference to the accompanying drawings, is intended to aid in a full understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to aid understanding, but these details are considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the invention. Furthermore, for clarity and brevity, descriptions of well-known functions and structures may be omitted.

[0021] The terms and words used in the following description and claims are not limited to their literal meaning, but are merely intended to enable a clear and consistent understanding of the invention. Therefore, it will be apparent to those skilled in the art that the following description of exemplary embodiments of the invention is for illustrative purposes only and is not intended to limit the invention as defined by the appended claims and their equivalents.

[0022] It should be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Thus, for example, unless the context clearly specifies otherwise, reference to “component surface” includes reference to one or more surfaces of that type.

[0023] In the context of this specification, the following conventions, terms and / or expressions may be used.

[0024] The term 'memory device' here can specifically refer to a memory cell used to store one or more bits based on phase change materials. Phase change memory (PCM) is known as a type of non-volatile random access memory. It is typically based on the unique properties of chalcogenide glasses. However, other materials have also been successfully used. The effect is based on the change in electrical conductivity between the crystalline and amorphous phases of the PCM. The phase change can be induced by heat, for example, by the current flowing through the device. PCMs can also be referred to as memristors. They can be used not only as memory elements but also as the basis for active computing devices.

[0025] The term 'minimum conductance state' can be used to describe the reset state of a PCM cell. If all or most of the PCM material in a PCM cell is in the amorphous phase, the resistance increases to the highest possible value for the PCM. This state can be described as the state with minimum conductance for the corresponding PCM cell.

[0026] The term 'protruding layer portion' or, in other words, 'liner' can refer to a more or less conductive material positioned parallel to the phase change material of the PCM cell, and in one embodiment, it can be specific, i.e., a mushroom-shaped portion in contact with one of the two electrodes of the cell. In other embodiments, particularly in lateral and restricted forms, the protruding layer portion does not contact any electrode. The protruding layer portion can also be referred to as a restricted liner or a restricted protrusion that does not span the entire length of the phase change memory volume.

[0027] In protruding memory cells, the protruding layer can help decouple the physical mechanism of resistive storage from the information retrieval process. The read current bypasses the amorphous phase change material and flows through a non-drifting, less noisy, and highly conductive protruding material. Conventional protruding memory cells also have disadvantages compared to the novel concept of restricted protrusions or liners presented here. The minimum conductance of the device can be significantly increased. Therefore, the device dynamic range is reduced, and the reset device (G approximately 0) can carry more current during readout. Consequently, the power efficiency of the memory cell may decrease during readout because the cell cannot be programmed to the proper OFF state (G = 0).

[0028] Therefore, a protruding layer portion that may only cover a portion of the phase change material in the reset state can also be represented as a 'restricted protrusion' within a potentially larger or very low conductivity layer portion, i.e., a non-protruding portion. Thus, this protruding layer portion can together with the non-protruding portion constitute a protruding layer.

[0029] The term 'non-protruding portion' can refer to a portion of the protruding layer of a phase change memory cell that has a much lower electrical conductivity than the restricted protruding portion or liner.

[0030] The term 'reset state' can refer to the state of a phase change memory cell, where the conductivity can be as low as possible, i.e., as much phase change material as possible can be in the amorphous phase.

[0031] The term 'discontinuity of conductance state' can refer to the conductance state of a phase change memory cell. Conversely, at some point, if the phase change material in the amorphous phase covers a larger area than the maximum area of ​​the liner or protruding layer, a step increase / decrease (depending on the viewing angle) can be observed in the current-to-voltage line.

[0032] The proposed memory device that achieves reduced minimum conductance states offers several advantages, contributions, and technical benefits:

[0033] For memory cells or memory devices, the drift and conductance fluctuations caused by 1 / f (f = frequency) are generally low. This is a consequence of the fact that most of the read current bypasses the amorphous volume when the memory cell is in the reset state.

[0034] This effect can be advantageously used in cross-arrays of memristor cells because the absolute noise level of the reset cell state is application-dependent, such as in neuromorphic computation, training, and inference of classical deep neural networks based on phase-change memory. These applications can benefit from low conductance (G) for several reasons. MIN Device state. Many weights in deep neural networks are small or close to zero. To encode such weights, low G... MIN It may be necessary.

[0035] When G MIN When the conductance is too high, the two devices in a differential configuration must be programmed to have the same conductance to represent zero. Programming two devices to have exactly the same conductance can be very challenging, and therefore this approach will result in prohibitive noise on zero weights, if the devices can be programmed to a sufficiently low G. MIN Then, prohibitive noise on zero weights can be completely avoided.

[0036] Additionally, if small weights or weights close to zero can be determined by G... MIN (Reset) device state encoding allows for a substantial reduction in the power consumption of the relevant deep neural network, because G MIN It has been reduced by at least an order of magnitude.

[0037] Improvements to conventional methods also include achieving protrusion within an intermediate conductance range that may be relevant to multi-level programming of memory devices by confining the protruding layer or liner to a region of small active volume (the maximum amorphous volume generated during device reset). However, for the low conductance state G... MIN It is disabled. This allows for drift mitigation in the intermediate and high conductance states. Therefore, G is essentially reduced. MIN It can achieve a high dynamic range, making G MIN The drift and noise can become irrelevant in the memory devices discussed (and other) applications.

[0038] In this way, the advantages of a prominent phase-change memory cell can be achieved, while successfully avoiding its disadvantages.

[0039] According to an advantageous embodiment of the memory device, the protruding layer portion may cover one of the first and second electrodes. This design can generally be referred to as a 'mushroom cell type'. The reason is that the lower electrode typically passes through the dielectric, and the liner or protruding layer portion may be located on top of the lower electrode (i.e., the bottom electrode). The amorphous phase change material may extend on the liner in a hemispherical form, making it appear as a mushroom shape (together with the lower electrode).

[0040] According to embodiments of the memory device, both the first electrode and the second electrode can contact the dielectric layer in a region where the first electrode and the second electrode do not contact the phase change material. A protruding layer portion can extend laterally on the dielectric layer, and the surface of the protruding layer portion opposite to the surface of the protruding layer that does not face the dielectric material can contact the phase change material. This phase change memory cell design can be referred to as a 'lateral cell design'.

[0041] According to embodiments of the memory device, a dielectric layer portion may surround (specifically, only partially and not from the top electrode to the bottom electrode) the phase change material. This cell design can be defined as a "restricted" phase change memory cell design. The phase change material may be located in the middle, and it may be partially surrounded by a protruding layer portion, which is then completely encapsulated by the dielectric material. A first and second electrode, which can be configured as a top electrode and a bottom electrode, may be in contact with the phase change material. Thus, according to a modified embodiment of the memory device, the protruding layer portion may be located around the phase change material, and the protruding layer portion may be surrounded by the dielectric material.

[0042] According to a preferred embodiment of the storage device, the protruding layer portion may include Ti. x N y Ta x N y Alternatively, amorphous carbon. These materials can be advantageously used as lining materials because of their well-defined electrical conductivity, which depends on the level of doping.

[0043] According to an additional embodiment of the memory device, the protruding layer portion can extend from non-protruding portions, which have a (significantly) lower conductivity than the protruding layer portion. Both the protruding layer portion and the non-protruding portions can constitute a protruding layer with a higher conductivity region (i.e., the protruding layer portion) and a less or non-conductive region ((multiple) non-protruding layer portions). Both portions can be located on a dielectric material. Different conductivity characteristics can be achieved by performing different doping processes on different portions of the protruding layer. Alternatively, the non-protruding portions of the protruding layer can be completely omitted.

[0044] According to a preferred embodiment of the storage device, the following conditions can be met:

[0045] R NON-PROJECTING >>R AMORPHOUS >>R PROJECTION ,

[0046] in

[0047] R NON-PROJECTION = Resistance of the non-protruding part,

[0048] R AMORPHOUS= If the region covered by the crystalline phase of the phase change material can cover the entire protruding layer, then the resistance of the phase change material, and

[0049] R PROJECTION = Resistance of the protruding layer portion. Therefore, if the volume of the phase change material has grown large enough (i.e., covering the entire liner), a discontinuity in the current-to-voltage ratio curve may occur because the current may no longer bypass the amorphous portion of the phase change material through the liner.

[0050] According to embodiments of the memory, the protruding and non-protruding portions can be doped differently. The doping concentration of the material can depend on whether the conductivity should be increased or decreased. Exemplary H2 or N2 can be used as the doping material.

[0051] According to embodiments of the memory device, doping of the non-protruding layer portion and the protruding layer portion allows the device current (when the phase change material is in the amorphous phase) to cover the entire protruding layer portion. Compared to a state where the entire protruding liner portion (i.e., the liner) can be covered by a phase change material in the amorphous phase, the device current can be reduced by at least two times. This can also be seen as a result of the resistivity relationship between different materials (i.e., the non-protruding portion, the protruding portion, and the phase change material in the amorphous phase).

[0052] According to embodiments of the memory device, the doping between the protruding layer portion and the non-protruding layer of the protruding layer can be varied according to a predetermined gradient. Therefore, a higher degree of dependence can be generated between the current passing through the protruding layer and the phase change material in the amorphous phase.

[0053] According to embodiments of the memory device, the protruding layer portions and / or non-protruding layer portions may be doped with hydrogen or nitrogen. These materials have proven practically useful for these types of memory cells and the constrained protruding layer designs. They can increase or decrease the conductivity of the corresponding layer materials. The doping process can be controlled using known masking techniques.

[0054] According to embodiments of the memory device, the dopant concentration that increases conductivity is higher in the protruding layer portion (i.e., the liner) compared to the non-protruding layer portion. This is a logical consequence of the design principle used here. The protruding layer portion will allow current to flow easily through that portion of the device. The contrast for the non-protruding portion is real.

[0055] According to embodiments of the memory device, if the concentration of dopant that reduces conductivity is higher in the non-protruding portion compared to the protruding portion, this may again be a logical consequence of the proposed cell design.

[0056] According to an embodiment of the memory device, during a read operation on the memory device, R CRYST < <R PROJECTION , where RCRYST It is the resistance of a phase change material in its crystalline phase, and R PROJECTION It is the resistance of the protruding layer. Therefore, most of the current through the cell can flow through the phase change material of the crystalline phase, rather than through the protruding layer.

[0057] According to another embodiment of the memory device, R AMORPHOUS >>R PROJECTION This relationship can help ensure the proper functioning of read operations.

[0058] A detailed description of the accompanying drawings is given below. All illustrations in the drawings are schematic. In particular, block diagrams of an embodiment of the memory device of the present invention capable of achieving a reduced minimum conductance state are shown.

[0059] Figure 1 A block diagram of an embodiment of the memory device 100 of the present invention, capable of achieving a reduced minimum conductivity state, is shown. The memory device 100 (here in the form of a single cell) shows patterned liner layers 110, 118 on top of a dielectric material 102. A bottom electrode 106 contacts the middle portion of the liner (i.e., the protruding layer portion 110). On top of the protruding layer portion 110, phase change materials in crystalline state 108 and amorphous states 112, 114, 116 are shown. A top electrode 104 is present on top of the phase change material 108.

[0060] A reduced G can be generated by patterning the protruding layers 110, 118 into protruding layer portions 110 and non-protruding layer portions 118. MIN State. The letter G indicates conductivity (1 / resistance). The liner 110 at the center of the active device volume has a low resistivity to achieve prominence (especially in the non-reset state), such that a readout current of less than (e.g., about 10%) should resolve the amorphous volumes 112, 114, 116.

[0061] Therefore, for the mushroom-shaped cell design shown, the size of the low-resistivity liner is limited to a region smaller than the maximum size of the amorphous dome. This is indicated by the boundary line 120 between the protruding layer portion 110 and the non-protruding layer portion 118. As a result of the limited liner or protruding layer portion 110, once a critical size of the amorphous volume is achieved—that is, once the region of the amorphous portion of the phase change material in contact with the protrusion is larger than the low-resistivity protruding layer portion 110—the device programming curve shows a discontinuity. This is Figure 2 As shown in the figure.

[0062] Figure 2 The conductivity diagram 200, as presented here, compares conventional raised liners with patterned raised lines. Line 202 shows the cell conductivity G relative to the write current I for different cell states. CELLOnce the volume of the amorphous portion of the phase change material grows to exceed the horizontal extension of the protruding layer portion 110 (i.e., if the amorphous dome blocks the complete protruding layer portion 110), the cell conductivity decreases significantly (the two conductivity states to the right of the dashed line are represented by solid black circles). Therefore, the reset conductivity is significantly lower than that of a conventional protruding memory cell.

[0063] Figure 3A A typical design of a conventional, prominent memory device 300 is shown again in the background. It includes a top electrode 302 and a bottom electrode 304. Between them, surrounding the phase change material 308, a protruding layer 306 is shown.

[0064] During the writing process, current (represented by a dashed straight line from the top electrode 302 to the bottom electrode 304) passes through the crystalline phase change material 308, which forms the amorphous phase 310 at some intermediate point between the top and bottom electrodes. Figure 3B The resistance R is shown in the figure. CRYST Therefore, the resistance R is much smaller than that of the protruding layer. PROJECTION R CRYST < <R PROJECTION During the read operation, due to R... AMOURPHOUS >>R PROJECTION The current (represented by the second dashed line) from the top electrode 302 to the bottom electrode 304 can flow around the amorphous portion 310 of the phase change material 308.

[0065] By highlighting this concept, the physical mechanism of resistive storage is decoupled from the information retrieval process (i.e., readout). It leverages the unique electrical transport and structural dynamics within the storage material (i.e., phase change material).

[0066] This is again illustrated in Table 312, which shows the current I depending on the voltage supplied to the phase change memory cell. The protruding layer shows a constant resistance (flat line). At some point in the amorphous phase (AMOR) resistance, there is a jump point in the unit resistance. The portion of the curve represented as "AMOR, On" is the point where the phase change material at least partially changes to the crystalline phase, thereby reducing resistance (i.e., increasing conductance).

[0067] Figure 4A cross array 400 of neural network cells is shown, which can be used as the basis for programming weights for, for example, deep neural networks (DNNs). The aforementioned effect can be particularly advantageous when mapping a deep neural network structure to a cross array 400 of phase-change memory cells. Typically, in practical implementations, only a smaller portion 402 of the larger cross array 400 of phase-change memory cells can be used. Therefore, in such a device, more phase-change memory cells than are actually needed and used are available. For these unused phase-change memory cells, it would be best if their conductivity exhibited only very small conductivity (ideally equal to zero) in the reset state (i.e., large amorphous volume).

[0068] This will significantly minimize the array's power consumption during readout and thus increase network efficiency. This is because most weights in a deep neural network that can be encoded by the array's phase-change memory cells are typically zero, or at least close to zero. Improved G MIN The state allows these weights to be directly mapped to device states without any additional electronic components. Therefore, different device configurations are not required. Because network efficiency is improved, the efficiency of deep neural networks is also significantly improved, which is particularly relevant for inference applications.

[0069] Apart from Figure 1 In addition to the mushroom-shaped device design, Figure 5 A lateral cell design 500 on a dielectric layer 502 is shown. A crystalline phase change material 508 is placed between a first electrode 504 and a second electrode 506. Below the amorphous phase change materials 512, 514, and 516, a patterned protruding liner 510 is shown. A region 518 outside the protruding portion 510 in the same layer (i.e., the non-protruding portion) has a much higher resistance (i.e., a much lower conductivity) than the central protrusion 510.

[0070] The amorphous phase of the phase change material is shown as having different diameters 512, 514, and 516 indicating different states of the phase change memory cell. The two exemplary states indicated by the volumes 512 and 514 of the phase change memory do not completely cover the protruding layer portion 510. However, if the amorphous volume 516 of the phase change memory covers a larger area than the protruding layer portion 510, a reset state (G) is reached. MIN This is because the current from the first electrode 504 to the second electrode 506 must primarily flow through the amorphous phase change material.

[0071] Figure 6A limited design of a phase-change memory cell or device based on the concept presented herein is shown. Here, a crystalline phase-change material 608 is positioned between a top electrode 604 and a bottom electrode 606. The entire device is surrounded by a dielectric layer 602. Also visible is a protruding layer portion 610 surrounding the middle portion of the phase-change material 608. Different volumes 612, 614, and 616 of the amorphous phase of the phase-change material in the memory cell are also shown. When the amorphous portion 616 of the phase-change memory material grows larger than the area covered by the protruding layer portion 610, the device 600 is in a reset state (i.e., reaching G). MIN It should also be mentioned that region 618 (i.e., the non-protruding layer portion) has a much higher resistivity than the protruding layer portion 610.

[0072] Therefore, in the horizontal direction ( Figure 5 ) and the limited unit design ( Figure 6 In the mushroom-shaped unit (compare), the lengths of the protruding layer portions 510 and 610 are limited to less than the longest amorphous length that can be generated in the device during reset. Figure 1 The prominent region 104 is confined to the area completely covered by the amorphous hemisphere generated in the device during reset.

[0073] Alternatively, a gradient liner layer can be used, where the core protrusion is in the middle of the liner. This makes the transition between the uncovered liner portion and the fully covered liner less abrupt. For this purpose, a 704 liner with a doping concentration gradient can be used. The 704 liner becomes more resistive from the center of the amorphous volume to the corresponding edge. This... Figure 7A and 7B In Figure 1 The unit version discussed in the context of the above and the gradient lining version on the right side of Figure 700 are shown side-by-side in comparison. Therefore, Figure 7A Repeated from Figure 1 The mushroom-shaped unit design, and Figure 7B It is related to the doping concentration gradient of the lining 710.

[0074] It can be noted that the reference numerals in the attached figures are Figure 1 Those widely used in the design, and the left mushroom-shaped unit design has a clear vertical line 120 between the protruding layer portion 110 of the lining and the remaining portion 118 (non-protruding portion) of the protruding layer. Figure 7B The comparable unit design on the right shows the rising and falling edges between the central portion (i.e., the lining) of the protruding portion 710 and the remaining portion 118 (the non-protruding portion).

[0075] Therefore, compared with the left-side design ( Figure 7CThe resistance of the lining shown on the right is abruptly decreasing and increasing, while the design on the right shows a gradual decrease and increase in resistance of the lining portion. Figure 7D This also translates to reading the current I. READ Different characteristics. For the left-side design ( Figure 7E The decrease in read current is sudden, which depends on the volume of the amorphous portion of the phase change material. ARMOR Conversely, for the right side of the memory cell ( Figure 7F The design shows that as the volume of the amorphous phase in the phase change material increases, the degradation of the read current exhibits a smoother (smaller tilt) characteristic.

[0076] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0077] This invention can be embodied in conjunction with systems, methods using storage devices, and / or computer program products. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0078] This document describes aspects of the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0079] The flowcharts and / or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions mentioned in the blocks may occur in a different order than those shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block illustrated in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including” as used in this specification specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0081] All components or steps in the following claims, plus corresponding structures, materials, actions, and equivalents of the functional elements, are intended to include any structure, material, or action for performing a function in combination with other claimed elements as specifically claimed. The invention has been described for purposes of illustration and description, but this description is not exhaustive or intended to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles and practical application of the invention and to enable others skilled in the art to understand various embodiments of the invention with various modifications, as suitable for the particular intended use.

[0082] Based on the foregoing, computer systems, methods, and computer program products have been disclosed. However, many modifications and substitutions can be made without departing from the scope of the invention. Therefore, the invention has been disclosed by way of example rather than limitation.

[0083] Although the invention has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0084] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements available in the market for one or more embodiments, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory device for achieving a reduced minimum conductance state, the device comprising: A first electrode, a second electrode, and a phase change material between the first electrode and the second electrode; A protruding layer located between the phase change material and the first electrode, wherein, in the reset state of the memory device, the protruding layer is positioned adjacent to the phase change material in the amorphous phase, wherein the contact surface of the amorphous phase of the phase change material is in direct contact with the contact surface of the protruding layer, wherein the area of ​​the contact surface of the protruding layer is smaller than the area of ​​the contact surface of the amorphous phase of the phase change material. A non-protruding layer is positioned adjacent to the protruding layer, wherein the contact surface of the non-protruding layer contacts the contact surface of the amorphous phase of the phase change material, and in the reset state of the memory device, the contact surface of the non-protruding layer contacts the contact surface of the phase change material in the crystalline phase, wherein the contact surface of the non-protruding layer is flush with the contact surface of the protruding layer. A dielectric layer positioned adjacent to the first electrode, the protruding layer, and the non-protruding layer, wherein the top surface of the dielectric layer contacts the bottom surface of the protruding layer and the non-protruding layer, wherein the side surface of the dielectric layer contacts the side surface of the first electrode, and wherein the top surface of the first electrode is smaller than the bottom surface of the protruding layer.

2. The memory device of claim 1, wherein the protruding layer comprises Ti x N y Ta x N y Or amorphous carbon.

3. The memory device of claim 1, wherein the non-protruding layer has a lower conductivity than the protruding layer.

4. The memory device according to claim 3, wherein: R NON-PROJECTING >> R AMORPHOUS >> R PROJECTION ; in: R NON-PROJECTING = The resistance of the non-protruding layer; R AMORPHOUS = The resistance of the phase change material if the region covered by the crystalline phase of the phase change material covers both the protruding layer and the non-protruding layer; and R PROJECTION = The resistance of the protruding layer.

5. The memory device of claim 3, wherein the protruding layer and the non-protruding layer are doped differently.

6. The memory device of claim 5, wherein the doping of the non-protruding layer and the protruding layer is such that: when the phase change material in the amorphous phase completely covers the protruding layer and the non-protruding layer, the device current is at least twice as low as when the protruding layer is covered by the phase change material in the amorphous phase.

7. The memory device of claim 5, wherein the doping between the protruding layer and the non-protruding layer varies according to a predetermined gradient.

8. The memory device of claim 7, wherein the protruding layer and / or the non-protruding layer is hydrogen- or nitrogen-doped.

9. The memory device of claim 8, wherein the concentration of dopant that increases the conductivity is higher in the protruding layer compared to the non-protruding layer.

10. The memory device of claim 8, wherein the concentration of dopant that reduces conductivity is higher in the non-protruding layer compared to the protruding layer.

11. The memory device according to claim 1, wherein: During a read operation on the memory device, R CRYST << R PROJECTION , where R CRYST R is the resistance of the phase change material in the crystalline phase, and PROJECTION It is the resistance of the protruding layer.

12. The memory device of claim 1, wherein R AMORPHOUS >> R PROJECTION .

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