A single event hardening flip-flop circuit

Abstract

The application discloses a single-particle reinforced flip-flop circuit, relates to the technical field of circuits, and can solve the problem that in the case that ionizing radiation energy is relatively strong or the size of a flip-flop device is relatively small, the node level subjected to ionizing radiation cannot be recovered by using an existing circuit structure, and thus the flip-flop is subjected to single-particle flipping. The single-particle reinforced flip-flop circuit comprises two latch units which are connected in series, and at least one of the latch units is provided with a delay unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a single event hardening flip-flop circuit. BACKGROUND

[0002] Electronic devices in circuits are vulnerable to ionizing radiation in a radiation environment, thus causing single event upset of the electronic devices. The level of a combinational logic unit will recover after a single event upset ends; when a particle upset occurs in a sequential logic circuit, such as a flip-flop, a latch or a memory, etc., due to the existence of a feedback structure, the upset is locked and the level cannot recover. A single event upset hardening structure is provided in a conventional circuit to prevent the upset level from being locked.

[0003] However, the conventional single event upset hardening structure has limited recovery capability for single event upset caused by ionizing radiation. In the case of strong ionizing radiation energy or small device size of the flip-flop, it is difficult to recover the node level affected by ionizing radiation, and the circuit is still affected by single event upset. SUMMARY

[0004] The single event hardening flip-flop circuit provided by the embodiments of the present application can solve the problem that the existing circuit structure is difficult to recover the node level affected by ionizing radiation, resulting in single event upset of the flip-flop in the case of strong ionizing radiation energy or small device size of the flip-flop.

[0005] The single event hardening flip-flop circuit provided by the embodiments of the present application comprises:

[0006] Two latch units, the two latch units are connected in series.

[0007] At least one delay unit is arranged in the latch unit.

[0008] In some embodiments, the latch unit comprises a latch input end and a latch output end, the latch unit comprises a first inverter and a first clock gating unit, an inverter input pin of the first inverter and a data output pin of the first clock gating unit are electrically connected to the latch input end, an inverter output pin of the first inverter and a data input pin of the first clock gating unit are electrically connected to the latch output end.

[0009] At least one delay unit is arranged between the latch input end and the latch output end.

[0010] In some embodiments, at least one delay unit is arranged between the latch input end and the inverter input pin of the first inverter.

[0011] In some embodiments, at least one of the delay units is provided between the latch output and a data input pin of the first clock gating unit.

[0012] In some embodiments, at least one of the delay units is provided between the latch output and an inverter output pin of the first inverter.

[0013] In some embodiments, at least one of the delay units is provided between the latch input and a data output pin of the first clock gating unit; and / or,

[0014] at least one of the delay units is provided between the latch output and a data input pin of the first clock gating unit.

[0015] In some embodiments, the delay unit comprises a resistor, two ends of the resistor being used to lead out a delay input pin and a delay output pin of the delay unit, respectively.

[0016] In some embodiments, the delay unit comprises a capacitor, one end of the capacitor being used to access a fixed potential, and the other end of the capacitor being used to lead out a delay input pin and a delay output pin of the delay unit.

[0017] In some embodiments, the delay unit comprises a capacitor and a resistor, one end of the capacitor and one end of the resistor being connected to lead out a delay output pin of the delay unit, the other end of the capacitor being used to access a fixed potential, and the other end of the resistor being used to lead out a delay input pin of the delay unit.

[0018] In some embodiments, the single-event-hardened flip-flop circuit further comprises:

[0019] a logic input circuit;

[0020] a second clock gating unit, the second clock gating unit being provided between the logic input circuit and one of the latch units;

[0021] a third clock gating unit, the third clock gating unit being provided between two of the latch units.

[0022] The single event hardening flip-flop circuit provided by the embodiment of the present application can maintain the level of another node of the feedback loop unchanged by the load delay characteristic of the delay unit when the level of a certain node of the feedback loop in the latch unit is flipped by the single particle of ionizing radiation, and restore the level of the affected node after the ionizing radiation ends. The problem that the single event hardening structure in the existing circuit is difficult to restore the level of the node affected by ionizing radiation when the ionizing radiation energy is strong or the device size of the flip-flop is small, resulting in single event flip-flop of the flip-flop, can be solved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A schematic structural diagram of a single event hardening flip-flop circuit provided by the embodiment of the present application is provided.

[0024] Figure 2 A schematic structural diagram of a latch unit provided by the embodiment of the present application is provided.

[0025] Figure 3 A schematic structural diagram of another latch unit provided by the embodiment of the present application is provided.

[0026] Figure 4 A schematic structural diagram of another latch unit provided by the embodiment of the present application is provided.

[0027] Figure 5 A schematic structural diagram of another latch unit provided by the embodiment of the present application is provided.

[0028] Figure 6 A schematic structural diagram of a delay unit provided by the embodiment of the present application is provided.

[0029] Figure 7 A schematic structural diagram of another delay unit provided by the embodiment of the present application is provided.

[0030] Figure 8 A schematic structural diagram of another delay unit provided by the embodiment of the present application is provided.

[0031] Figure 9 A schematic structural diagram of another single event hardening flip-flop circuit provided by the embodiment of the present application is provided.

[0032] Figure 10 A schematic structural diagram of a clock signal input circuit provided by the embodiment of the present application is provided.

[0033] Figure 11 A schematic structural diagram of a clock gating unit provided by the embodiment of the present application is provided.

[0034] Figure 12 A schematic structural diagram of another clock gating unit provided by the embodiment of the present application is provided.

[0035] Figure 13 Another schematic structural diagram of a clock gating unit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to better understand the technical solutions provided by the embodiments of the present application, the technical solutions of the embodiments of the present application will be described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present application and the embodiments are detailed descriptions of the technical solutions of the embodiments of the present application, rather than limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0037] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element(s). The term "two or more" includes two or more than two.

[0038] Electronic devices in circuits are susceptible to ionizing radiation in a radiation environment, thereby causing single event upsets of the electronic devices. The level of combinational logic circuits will recover after a single event upset ends; when a particle upset occurs in a sequential logic circuit, such as a flip-flop, latch or memory, etc., due to the existence of a feedback structure, the upset is locked, and the level cannot recover. In a conventional circuit, a single event upset hardening structure is provided to prevent the upset level from being locked. However, the conventional single event upset hardening structure has limited recovery capability for single event upsets caused by ionizing radiation. In the case of strong ionizing radiation energy or small device size of the flip-flop, it is difficult to recover the node level affected by ionizing radiation, and the circuit is still affected, resulting in single event upsets of the flip-flop.

[0039] Therefore, an embodiment of the present application provides a single event hardened flip-flop circuit, which can solve the problem that in the case of strong ionizing radiation energy or small device size of the flip-flop, the existing circuit structure is difficult to recover the node level affected by ionizing radiation, resulting in single event upsets of the flip-flop.

[0040] The embodiment of the present application provides a single particle hardened flip-flop circuit, Figure 1 A single particle hardened flip-flop circuit provided by the embodiment of the present application is shown in a schematic structural diagram. Figure 1 As shown in the figure, the single particle hardened flip-flop circuit provided by the embodiment of the present application comprises two latch units which are connected in series, and at least one latch unit is provided with a delay unit. As shown in the figure, Figure 1 The two latch units are respectively represented as a first latch unit 110 and a second latch unit 120, and the first latch unit 110 is provided with a delay unit 101. Figure 1 The number and setting position of the delay unit 101 are not regarded as specific limitations of the embodiment of the present application, and the second latch unit 120 can also be provided with a delay unit. The first latch unit 110 and the second latch unit 120 can both be provided with the delay unit 101, and the embodiment of the present application does not make specific limitations.

[0041] As an example, the charged particles in the environment can cause ionizing radiation, and a certain number of electron-hole pairs are generated around the motion track of the particles. When the deposited electron-hole pairs along the particle incidence direction are enough, the current caused by the collection of the electron-hole pairs to the depletion layer of the transistor can cause the inversion of the drain level, forming a single particle flip. The latch unit has a feedback loop, and the delay unit 101 plays a role in delaying signal transmission. When a node of the feedback loop in the latch unit is affected by the single particle of ionizing radiation and the level is inverted, the load delay characteristic of the delay unit 101 can maintain the level of another node of the feedback loop unchanged, and restore the level of the affected node after the ionizing radiation ends. The problem that the single particle flip-flop hardening structure in the existing circuit is difficult to restore the level of the node affected by ionizing radiation when the ionizing radiation energy is relatively strong or the device size of the flip-flop is relatively small, resulting in the single particle flip of the flip-flop.

[0042] The single particle hardened flip-flop circuit provided by the embodiment of the present application can solve the problem that the single particle flip-flop hardening structure in the existing circuit is difficult to restore the level of the node affected by ionizing radiation when the ionizing radiation energy is relatively strong or the device size of the flip-flop is relatively small, resulting in the single particle flip of the flip-flop, by arranging the delay unit 101 in at least one latch unit. The delay unit 101 can play a role in delaying signal transmission. When a node of the feedback loop in the latch unit is affected by the single particle of ionizing radiation and the level is inverted, the load delay characteristic of the delay unit 101 can maintain the level of another node of the feedback loop unchanged, and restore the level of the affected node after the ionizing radiation ends.

[0043] In some embodiments, Figure 2 A schematic structural diagram of a latch unit provided by the embodiment of the present application is shown in the figure. Figure 2As shown in the figure, the latch unit includes a latch input end IN and a latch output end OUT, and the latch unit includes a first inverter 111 and a first clock gating unit 112, the inverter input pin e of the first inverter 111 and the data output pin h of the first clock gating unit 112 are electrically connected with the latch input end IN, and the inverter output pin f of the first inverter 111 and the data input pin p of the first clock gating unit 112 are electrically connected with the latch output end OUT; at least one delay unit 101 is arranged between the latch input end IN and the latch output end OUT.

[0044] As shown in the figure, Figure 2 As shown in the figure, the delay unit 101 is arranged between the latch input end IN and the first inverter 111, the delay input pin A of the delay unit 101 is connected with the latch input end IN, and the delay output pin B of the delay unit 101 is connected with the inverter input pin e of the first inverter. It should be noted that the internal circuit structures of the first latch unit 110 and the second latch unit 120 can be the same or different, and the clock control end of the first clock gating unit 112 can be reversely arranged, and the embodiments of the present application are not limited specifically. The head and tail of the inverter and the clock gating unit in the latch unit can form a latch feedback to realize the latch function, and the clock gating unit can be a common clock gating inverter circuit which can play a role of controlling the switch through the clock signal. The number of the delay unit 101 in each latch unit can be two or more, and the embodiments of the present application are not limited specifically.

[0045] The latch unit provided by the embodiments of the present application has at least one delay unit 101 arranged between the latch input end IN and the inverter input pin e of the first inverter 111, when the latch input end IN (the output of the first clock gating unit 112) is affected by the single particle of ionizing radiation to cause level inversion, the load delay characteristic of the delay unit 101 can maintain the level of another node (the latch output end OUT) of the feedback loop unchanged, and restore the level of the affected node (the latch input end IN) after the ionizing radiation ends.

[0046] In some embodiments, Figure 3 Another schematic structural diagram of a latch unit provided by the embodiments of the present application is shown in the figure. Figure 3 As shown in the figure, at least one delay unit 101 is arranged between the latch output end OUT and the data input pin p of the first clock gating unit 112.

[0047] Exemplarily, at least one delay unit 101 can be arranged between the latch output OUT and the data input pin p of the first clock gating unit 112. When the latch output OUT (the output of the first inverter 111) is flipped by the single particle of the ionizing radiation, the load delay characteristic of the delay unit 101 can maintain the level of another node (the latch input IN) of the feedback loop unchanged and restore the level of the affected node (the latch output OUT) after the ionizing radiation ends.

[0048] Exemplarily, at least one delay unit 101 can be arranged between the latch input IN and the inverter input pin e of the first inverter 111, while at least one delay unit 101 is arranged between the latch output OUT and the data input pin p of the first clock gating unit 112. Arranging the delay unit 101 close to the latch input IN and close to the latch output OUT can double-protect both nodes of the latch unit to have the single particle hardening effect and ensure the accuracy of the latch signal.

[0049] In some embodiments, Figure 4 Another schematic structural diagram of a latch unit provided by an embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, at least one delay unit 101 is arranged between the latch output OUT and the inverter output pin f of the first inverter 111. Figure 4 As shown in FIG. 5, at least one delay unit 101 is arranged between the latch input IN and the data output pin h of the first clock gating unit 112. The delay unit 101 arranged close to the latch input IN can be arranged close to the data output pin h of the first clock gating unit 112, and the delay unit 101 arranged close to the latch output OUT can be arranged close to the inverter output pin f of the first inverter 111. Figure 4 As shown in FIG. 5, at least one delay unit 101 is arranged between the latch input IN and the data output pin h of the first clock gating unit 112. The delay unit 101 arranged close to the latch input IN can be arranged close to the data output pin h of the first clock gating unit 112, and the delay unit 101 arranged close to the latch output OUT can be arranged close to the inverter output pin f of the first inverter 111. Figure 4 The structure of the latch unit shown in FIG. 5 is only schematic. The positions of the delay units 101 can be arranged according to specific delay needs. Arranging two delay units can double-protect both nodes of the latch unit to have the single particle hardening effect and ensure the accuracy of the latch signal.

[0050] In some embodiments, at least one delay unit 101 can be arranged between the latch input IN and the data output pin h of the first clock gating unit 112.

[0051] Figure 5 Another schematic structural diagram of a latch unit provided by an embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, at least one delay unit 101 is arranged between the latch output OUT and the inverter output pin f of the first inverter 111. Figure 5

[0052] ​At least one delay unit 101 can also be arranged between the latch input end IN and the data output pin h of the first clock gating unit 112, and at least one delay unit 101 can also be arranged between the latch output end OUT and the data input pin p of the first clock gating unit 112. The embodiments of the present application are not limited in this regard.

[0053] The single event hardening flip-flop circuit provided by the embodiments of the present application can set the number and position of the delay unit 101 according to specific delay requirements, and can more flexibly adapt to the structural design of different single event hardening flip-flop circuits.

[0054] It should be noted that, Figures 2-5 The circuit structures of the latch units shown are applicable to the first latch unit 110 and the second latch unit 120, and the circuit structures in the first latch unit 110 and the second latch unit 120 can be the same, and the clock control end of the first clock gating unit 112 can be reversely provided.

[0055] In some embodiments, Figure 6 A schematic structural diagram of a delay unit provided by the embodiments of the present application is shown in FIG. 2. As shown in FIG. 2, Figure 6 The delay unit 101 can include a resistor R, and the two ends of the resistor R are respectively used to lead out the delay input pin A and the delay output pin B of the delay unit. The resistor R is easy to implement as a delay element, and the circuit structure is simple. According to different delay time requirements, different resistance values of the resistor R can be set.

[0056] In some embodiments, Figure 7 Another schematic structural diagram of a delay unit provided by the embodiments of the present application is shown in FIG. 3. As shown in FIG. 3, Figure 7 The delay unit 101 includes a capacitor C, one end of the capacitor C is used to access a fixed potential, and the fixed potential can be a power supply or a ground, Figure 7 As shown in FIG. 3, the fixed potential is a ground, and the other end of the capacitor C is used to lead out the delay input pin A and the delay output pin B of the delay unit. The charging and discharging process of the capacitor C can have the effect of delaying the transmission of the level signal, the circuit structure of the delay unit is simple and easy to implement, and the delay effect is obvious. According to different delay time requirements, different capacitance values of the capacitor C can be set.

[0057] In some embodiments, Figure 8 Another schematic structural diagram of a delay unit provided by the embodiments of the present application is shown in FIG. 4. As shown in FIG. 4, Figure 8 The delay unit 101 includes a capacitor C and a resistor R, one end of the capacitor C and one end of the resistor R are connected and used to lead out the delay output pin B of the delay unit 101, the other end of the capacitor C is used to access a fixed potential, and the fixed potential can be a power supply or a ground, Figure 8The fixed potential shown is grounded, and the other end of the resistor R is used to lead out the delay input pin A of the delay unit 101. The combined delay effect of the capacitor C and the resistor R is more obvious. Different values ​​of resistor R or capacitor C can be set according to the required delay time.

[0058] In addition to the aforementioned delay units, other devices can also be used to construct delay units, such as a delay unit containing a diode. This application does not limit the specific delay unit used.

[0059] In some implementations... Figure 9 A schematic structural diagram of another single-event hardened trigger circuit provided in an embodiment of this application. (See diagram below.) Figure 9 As shown in the figure, the single-event hardened trigger circuit provided in this application embodiment further includes: a logic input circuit 200; a second clock gate unit 300, which is disposed between the logic input circuit 200 and a latch unit; and a third clock gate unit 400, which is disposed between two latch units. It should be noted that... Figure 9 The structure of the single-event hardened trigger circuit shown corresponds to a rising-edge D flip-flop. By changing the connection of the first output clock signal cn and the second output clock signal c of all gated clock units, it can be converted to a falling-edge D trigger. Different logic input circuits 200 can be applied to edge-triggered types such as D flip-flops, synchronous reset D flip-flops, D scan flip-flops, or synchronous reset scan D flip-flops. It can also be applied to hardened latch circuits, which may include a second clock gate unit and a first latch unit; this application embodiment does not specifically limit the application. It can also be applied to other sequential circuits with memory functions; this application embodiment does not specifically limit the application.

[0060] For example, such as Figure 9 As shown, the first latch unit 110 can serve as a master latch, and the second latch unit 120 can serve as a slave latch. It should be noted that the connection of the first output clock signal cn and the second output clock signal c of the clock gating unit inside the second latch unit 120 is the opposite of that of the first latch unit 110. The second clock gating unit 300 can be located between the logic input circuit 200 and the first latch unit 110, and the third clock gating unit 400 can be located between the first latch unit 110 and the second latch unit 120. The output terminal Q of the single-event hardened trigger circuit is connected to the second inverter 500, and the inverted output terminal Qn is connected to the third inverter 600. Since the output terminal Q and the inverted output terminal Qn are respectively connected to the two ends of the second latch unit 120, the signals output by the output terminal Q and the inverted output terminal Qn are in opposite phases.

[0061] For example,Figure 10 A schematic structural diagram of a clock signal input circuit is provided for the embodiment of the present application. As shown in the figure, the clock signal input circuit is used to provide clock control signals for all clock gating units, and the clock signal input circuit inputs a clock signal CK. The clock signal CK passes through a fourth inverter 700 and a fifth inverter 800. The fifth inverter 800 has two ends, from which two output clock signals are led out, respectively a first output clock signal cn(CK inverted) and a second output clock signal c(CK in phase). The first output clock signal cn and the second output clock signal c are connected to corresponding pins of the clock gating units, respectively. Figure 10

[0062] An exemplary clock gating unit is provided for the embodiment of the present application. As shown in the figure, the clock gating unit includes a data input pin p, a data output pin h, a first clock pin OEN and a second clock pin OE. The first clock pin OEN can be used to receive the first output clock signal cn or the second output clock signal c, and the second clock pin OE can be used to receive the second output clock signal c or the first output clock signal cn. However, the first clock pin OEN receives one of the first output clock signal cn and the second output clock signal c, and the second clock pin OE receives the other one. Figure 11 Figure 11 An exemplary clock gating unit is provided for the embodiment of the present application. As shown in the figure, the clock gating unit includes a data input pin p, a data output pin h, a first clock pin OEN and a second clock pin OE. The first clock pin OEN can be used to receive the first output clock signal cn or the second output clock signal c, and the second clock pin OE can be used to receive the second output clock signal c or the first output clock signal cn. However, the first clock pin OEN receives one of the first output clock signal cn and the second output clock signal c, and the second clock pin OE receives the other one.

[0063] An exemplary clock gating unit is provided for the embodiment of the present application. As shown in the figure, the clock gating unit includes a data input pin p, a data output pin h, a first clock pin OEN and a second clock pin OE. The first clock pin OEN can be used to receive the first output clock signal cn or the second output clock signal c, and the second clock pin OE can be used to receive the second output clock signal c or the first output clock signal cn. However, the first clock pin OEN receives one of the first output clock signal cn and the second output clock signal c, and the second clock pin OE receives the other one. Figure 12 Figure 12 An exemplary clock gating unit is provided for the embodiment of the present application. As shown in the figure, the clock gating unit includes a data input pin p, a data output pin h, a first clock pin OEN and a second clock pin OE. The first clock pin OEN can be used to receive the first output clock signal cn or the second output clock signal c, and the second clock pin OE can be used to receive the second output clock signal c or the first output clock signal cn. However, the first clock pin OEN receives one of the first output clock signal cn and the second output clock signal c, and the second clock pin OE receives the other one.

[0064] An exemplary clock gating unit is provided for the embodiment of the present application. As shown in the figure, the clock gating unit includes a data input pin p, a data output pin h, a first clock pin OEN and a second clock pin OE. The first clock pin OEN can be used to receive the first output clock signal cn or the second output clock signal c, and the second clock pin OE can be used to receive the second output clock signal c or the first output clock signal cn. However, the first clock pin OEN receives one of the first output clock signal cn and the second output clock signal c, and the second clock pin OE receives the other one. Figure 13 An exemplary clock gating unit is provided for the embodiment of the present application. As shown in the figure, the clock gating unit includes a data input pin p, a data output pin h, a first clock pin OEN and a second clock pin OE. The first clock pin OEN can be used to receive the first output clock signal cn or the second output clock signal c, and the second clock pin OE can be used to receive the second output clock signal c or the first output clock signal cn. However, the first clock pin OEN receives one of the first output clock signal cn and the second output clock signal c, and the second clock pin OE receives the other one. Figure 13 ​​​As shown, the internal structure of the clock gating unit can be that the gate of the third PMOS tube P3 is connected with the gate of the third NMOS tube N3 to serve as a data input pin p, the source of the third PMOS tube P3 and the source of the third NMOS tube N3 are both connected to a fixed potential, the drain of the third PMOS tube P3 and the drain of the third NMOS tube N3 are connected to the source of the fourth PMOS tube P4, the drain of the fourth PMOS tube P4 serves as a data output pin h, the gate of the fourth PMOS tube P4 serves as a first clock pin OEN, the fourth NMOS tube N4 is connected in parallel with the fourth PMOS tube P4, and the gate of the fourth NMOS tube N4 serves as a second clock pin OE.

[0065] The single particle hardened flip-flop circuit provided by the embodiment of the present application sets a delay unit in a cascaded latch unit, the delay unit can play a role of delaying signal transmission, when a certain node of a feedback loop in the latch unit is affected by a single particle of ionizing radiation to cause level inversion, the load delay characteristic of the delay unit can maintain the level of another node of the feedback loop unchanged, and restore the level of the affected node after the ionizing radiation ends. The problem that the single particle inversion hardened structure in the existing circuit is difficult to restore the level of the node affected by ionizing radiation when the ionizing radiation energy is relatively strong or the device size of the flip-flop is relatively small, and the flip-flop is caused to have single particle inversion can be solved.

[0066] It should be noted that, Figures 11-13 The structures of the clock gating circuits shown are all schematic, and are not specific limitations of the present application. Figures 11-13 The clock gating circuits shown are applicable to the first clock gating unit 112, the second clock gating unit 300 and the third clock gating unit 400 mentioned in the present application.

[0067] Although the preferred embodiments of the present specification have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present specification.

[0068] Obviously, those skilled in the art can make various modifications and variations to the present specification without departing from the spirit and scope of the present specification. Thus, if these modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalent technologies, the present specification also intends to include these modifications and variations.

Claims

1. A single-event hardened trigger circuit, characterized in that, The application relates to a latch circuit. Two latch units are connected in series. At least one delay unit is arranged in the latch unit. The latch unit comprises a latch input end and a latch output end, and the latch unit comprises a first inverter and a first clock gating unit; the inverter input pin of the first inverter and the data output pin of the first clock gating unit are electrically connected with the latch input end; and the inverter output pin of the first inverter and the data input pin of the first clock gating unit are electrically connected with the latch output end. At least one delay unit is arranged between the latch input end and the latch output end.

2. The single event hardening flip-flop circuit of claim 1, wherein, At least one delay unit is arranged between the latch input end and the inverter input pin of the first inverter.

3. The single event hardening flip-flop circuit of claim 1 or 2, wherein, At least one delay unit is arranged between the latch output end and the data input pin of the first clock gating unit.

4. The single event hardening flip-flop circuit of claim 1, wherein, At least one delay unit is arranged between the latch output end and the inverter output pin of the first inverter.

5. The single event hardening flip-flop circuit of claim 1 or 4, wherein, At least one delay unit is arranged between the latch input end and the data output pin of the first clock gating unit; and / or At least one delay unit is arranged between the latch output end and the data input pin of the first clock gating unit.

6. The single event hardening flip-flop circuit of claim 1, wherein, The delay unit comprises a resistor, and the resistor is used for leading out a delay input pin and a delay output pin of the delay unit.

7. The single event hardening flip-flop circuit of claim 1, wherein, The delay unit comprises a capacitor, one end of the capacitor is used for being connected with a fixed potential, and the other end of the capacitor is used for leading out the delay input pin and the delay output pin of the delay unit.

8. The single event hardening flip-flop circuit of claim 1, wherein, The delay unit comprises a capacitor and a resistor, one end of the capacitor and one end of the resistor are connected and used for leading out the delay output pin of the delay unit, the other end of the capacitor is used for being connected with a fixed potential, and the other end of the resistor is used for leading out the delay input pin of the delay unit.

9. The single event hardening flip-flop circuit of claim 1, wherein, The application further relates to a latch circuit. A logic input circuit is arranged. A second clock gating unit is arranged between the logic input circuit and one latch unit. A third clock gating unit is arranged between two latch units.

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