Scattering communication device and program remote updating method thereof

Abstract

The present invention is applicable to the field of scattering communication technology, and provides a scattering communication device and a remote program update method thereof, wherein the scattering communication device includes an indoor unit and an outdoor unit, wherein the indoor unit includes a first processor, a first field programmable logic gate array (FPGA) module, and a first storage module, and the outdoor unit includes a second processor, a second FPGA module, and a second storage module, and a communication connection is established between the first FPGA module and the second FPGA module via an optical fiber. The first processor receives a first program and a second program, wherein the first program updates the first FPGA module, and the second program is sent to the outdoor unit via an optical fiber to update the second FPGA module. The present invention uses optical fibers to update the programs of the indoor and outdoor units of the scattering communication device, thereby simplifying the process and saving time and resources.

Description

Technical Field

[0001] The present invention belongs to the technical field of scatter communication, and in particular relates to a scatter communication device and a method for remotely updating a program thereof. Background Art

[0002] Scattering communication equipment usually includes an indoor unit and an outdoor unit. During the debugging process, later maintenance and product upgrades, the programs of the indoor unit and the outdoor unit need to be upgraded. In the existing method, the programs of the indoor unit and the outdoor unit need to be updated separately through the JTAG (Joint Test Action Group) interface, and since the JTAG interface is rarely brought out on the device panel, the device needs to be opened to update the program. The operation steps are cumbersome and time-consuming. In particular, since the outdoor unit is often installed at a high place, the program update is more complicated. If the JTAG interface is brought out separately, it will occupy the limited device interface. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a scattering communication device and a remote program update method thereof to simplify the update process, save update time, and save supporting resources.

[0004] In a first aspect, an embodiment of the present invention provides a scattering communication device, including an indoor unit and an outdoor unit; the indoor unit includes a first processor, a first FPGA (Field Programmable Gate Array) module and a first storage module; the first processor is connected to the first FPGA module and the first storage module respectively; the outdoor unit includes a second processor, a second FPGA module and a second storage module, the second processor is connected to the second FPGA module and the second storage module respectively; a communication connection is established between the first FPGA module and the second FPGA module via an optical fiber;

[0005] A first processor, configured to receive a first program and a second program, wherein the first program is used to update a program of the first FPGA module, and the second program is used to update a program of the second FPGA module;

[0006] The first processor is further used to fix the first program to the first storage module to update the program of the first FPGA module;

[0007] The first processor is further configured to send the second program to the second FPGA module through the first FPGA module and the optical fiber when detecting that the optical fiber is in a connected state;

[0008] The second processor is used to receive the second program transmitted by the second FPGA module, and fix the second program to the second storage module to update the program of the second FPGA module.

[0009] In combination with the first aspect, in a possible implementation manner, the indoor unit further includes a network port, and the network port is connected to the first processor;

[0010] The first processor is specifically configured to receive the first program and the second program through a network port.

[0011] In combination with the first aspect, in a possible implementation manner, the indoor unit further includes a target memory, and the target memory is connected to the first processor;

[0012] The first processor is specifically used to store the second program in a target memory after receiving the second program, and to read the second program from the target memory when detecting that the optical fiber is in a connected state, and to send the second program to the second FPGA module through the first FPGA module and the optical fiber.

[0013] In combination with the first aspect, in a possible implementation manner, the first processor is further configured to load the first program in the first storage module into the first FPGA module;

[0014] The second processor is further used to load the second program in the second storage module into the second FPGA module.

[0015] In combination with the first aspect, in a possible implementation manner, the indoor unit further includes a first optical port, and the outdoor unit further includes a second optical port;

[0016] The first optical port is connected to the first FPGA module, the second optical port is connected to the second FPGA module, and the first optical port and the second optical port are connected via an optical fiber.

[0017] In combination with the first aspect, in a possible implementation, the first FPGA module includes a first FPGA chip, and the second FPGA module includes a second FPGA chip and a third FPGA chip; the second FPGA chip and the third FPGA chip are connected, and a communication connection is established between the second FPGA chip and the first FPGA chip via an optical fiber; the second FPGA chip is used for modulation and demodulation, and the third FPGA chip is used for encoding and decoding;

[0018] The first storage module includes a first memory, and the second storage module includes a second memory and a third memory; the second FPGA chip, the third FPGA chip, the second memory and the third memory are all connected to the second processor;

[0019] The first program includes a first subprogram, and the second program includes a second subprogram and a third subprogram;

[0020] The second FPGA chip is used to send the received second subprogram and third subprogram to the second processor via the third FPGA chip;

[0021] The second processor is specifically used to fix the second subprogram into the second memory to update the program of the second FPGA chip, and fix the third subprogram into the third memory to update the program of the third FPGA chip.

[0022] In combination with the first aspect, in a possible implementation manner, the outdoor unit further includes a fourth memory, and the fourth memory is connected to the second FPGA chip;

[0023] The fourth memory stores an initialization program of the second FPGA chip;

[0024] The second FPGA chip is also used to read the initialization program in the fourth memory to initialize itself.

[0025] In combination with the first aspect, in a possible implementation manner, the first memory, the second memory, and the third memory are all FLASH memories.

[0026] In a second aspect, the present invention provides a method for remotely updating a program of a scattering communication device, wherein the scattering communication device includes an indoor unit and an outdoor unit; the indoor unit includes a first processor, a first field programmable logic gate array FPGA module and a first storage module; the outdoor unit includes a second processor, a second FPGA module and a second storage module, and a communication connection is established between the first FPGA module and the second FPGA module via an optical fiber; the method includes:

[0027] The first processor receives a first program and a second program, wherein the first program is used to update a program of the first FPGA module, and the second program is used to update a program of the second FPGA module;

[0028] The first processor solidifies the first program into the first storage module to update the program of the first FPGA module;

[0029] When the first processor detects that the optical fiber is in a connected state, the first processor sends the second program to the second FPGA module through the first FPGA module and the optical fiber;

[0030] The second processor receives the second program transmitted by the second FPGA module, and fixes the second program to the second storage module to update the program of the second FPGA module.

[0031] In conjunction with the second aspect, in a possible implementation manner, the indoor unit further includes a network port, and the network port is connected to the first processor;

[0032] The first processor receives the first program and the second program, including:

[0033] The first processor receives the first program and the second program through the network port.

[0034] In conjunction with the second aspect, in a possible implementation, the indoor unit further includes a target memory, and the target memory is connected to the first processor;

[0035] When the first processor detects that the optical fiber is in a connected state, the second program is sent to the second FPGA module through the first FPGA module and the optical fiber, including:

[0036] After receiving the second program, the first processor stores the second program in the target memory, and when detecting that the optical fiber is in a connected state, reads the second program from the target memory and sends the second program to the second FPGA module through the first FPGA module and the optical fiber.

[0037] An embodiment of the present invention provides a scattering communication device and a remote program update method thereof, wherein the program of the first FPGA module is updated through the first processor, the first field programmable logic gate array FPGA module and the first storage module of the indoor unit, and the program of the second FPGA module is updated through the second processor, the second FPGA module, the second storage module of the outdoor unit and the communication connection established between the first FPGA module and the second FPGA module through the optical fiber, and the program of the indoor unit and the outdoor unit of the scattering communication device is updated by using the existing optical fiber, without the need for additional supporting equipment and interfaces, without the need to update the indoor unit and the outdoor unit separately, and without the need to open the cover, thereby simplifying the update process, saving update time and supporting resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 is a schematic diagram of the structure of a scattering communication device provided by an embodiment of the present invention;

[0040] Figure 2 is a schematic structural diagram of a scattering communication device provided by another embodiment of the present invention;

[0041] Figure 3 is a schematic structural diagram of a scattering communication device provided by another embodiment of the present invention;

[0042] Figure 4is a schematic structural diagram of a scattering communication device provided by another embodiment of the present invention;

[0043] Figure 5 is a schematic structural diagram of a scattering communication device provided by another embodiment of the present invention;

[0044] Figure 6 It is a flow chart of the implementation of the remote updating method of the scatter communication device program provided by the embodiment of the present invention;

[0045] Figure 7 It is a structural diagram of a scattering communication device provided by a specific implementation example of the present invention. DETAILED DESCRIPTION

[0046] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0047] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0048] Figure 1 A schematic diagram of the structure of a scattering communication device provided by an embodiment of the present invention. Figure 1 The scattering communication device includes an indoor unit 11 and an outdoor unit 12. The indoor unit 11 includes a first processor 111, a first field programmable logic gate array FPGA module 112 and a first storage module 113. The first processor 111 is connected to the first FPGA module 112 and the first storage module 113 respectively. The outdoor unit 12 includes a second processor 121, a second FPGA module 122 and a second storage module 123. The second processor 121 is connected to the second FPGA module 122 and the second storage module respectively. A communication connection is established between the first FPGA module 112 and the second FPGA module 122 via an optical fiber.

[0049] The first processor 111 is configured to receive a first program and a second program, wherein the first program is used to update the program of the first FPGA module 112 , and the second program is used to update the program of the second FPGA module 122 .

[0050] The first processor 111 is further used to fix the first program into the first storage module 113 so as to update the program of the first FPGA module 112 .

[0051] The first processor 111 is further used to send the second program to the second FPGA module 122 through the first FPGA module 112 and the optical fiber when detecting that the optical fiber is in a connected state.

[0052] The second processor 121 is used to receive the second program transmitted by the second FPGA module 122 , and fix the second program to the second storage module 123 to update the program of the second FPGA module 122 .

[0053] Exemplarily, the first processor 111 can be a CPU (Central Processing Unit), a CPLD (Complex Programmable Logic Device), an FPGA, etc., which is not limited here. The first processor 111 can receive a program file containing a first program and a second program, first parse the program file and distinguish between the first program and the second program, wherein the first program is mainly responsible for completing the processing of interface signals, parsing of services, and opening up a channel for communication with the outdoors, and is used to update the program of the first FPGA module; the second program is mainly responsible for completing the modulation and demodulation and encoding and decoding functions, and is used to update the program of the second FPGA module.

[0054] The first processor 111 may fix the first program to the first storage module 113. Exemplarily, the first program may be fixed to the first storage module 113 via a QSPI (Queue Serial peripheral interface) interface.

[0055] When the first processor 111 detects that the optical fiber is in a connected state, the second program can be sent to the second FPGA module 122 through the first FPGA module 112 and the optical fiber. Exemplarily, the first processor 111 can firstly interact the second program to the first FPGA module 112 through a DMA (Direct Memory Access) interface, and then send it to the second FPGA module 122 through the optical fiber. The DMA interface is an interface for fast data interaction between the CPU and the FPGA, which can quickly interact the program file from the CPU to the FPGA module.

[0056] The second processor 121 may be a CPU, a CPLD, an FPGA, etc., which are not limited here. The second processor 121 may fix the second program to the second storage module 123. Exemplarily, the second processor 121 may fix the second program to the second storage module 123 through a QSPI interface.

[0057] In the embodiment of the present invention, by utilizing the existing optical fiber to update the program of the indoor unit and the outdoor unit of the scattering communication equipment, there is no need to additionally equip the supporting equipment and interfaces, there is no need to update the indoor unit and the outdoor unit separately, and there is no need to open the cover, which simplifies the update process and saves update time and supporting resources.

[0058] In some embodiments, reference Figure 2 The indoor unit 11 further includes a network port 114. The network port 114 is connected to the first processor 111. The first processor 111 is specifically configured to receive the first program and the second program through the network port 114.

[0059] One side of the network port 114 is connected to the first processor 111, and the other side is connected to the host computer. The program update software is installed on the host computer, and all operations are completed on the program update software.

[0060] The host computer can be a computer connected to the indoor unit through a network port.

[0061] In the embodiment of the present invention, the program transmission speed through the network port is faster, which further saves the update time, and the transmission is also updated and stable.

[0062] In some embodiments, reference Figure 3 The indoor unit 11 further includes a target memory 115. The target memory 115 is connected to the first processor 111.

[0063] The first processor 111 is specifically used to store the second program in the target memory 115 after receiving the second program, and when detecting that the optical fiber is in a connected state, read the second program from the target memory 115 and send the second program to the second FPGA module 122 through the first FPGA module 112 and the optical fiber.

[0064] The target memory 115 may be an EMMC (Embeded MultiMedia Card).

[0065] In the embodiment of the present invention, the second program may be first stored in the target memory 115 and updated when the optical fiber interface is in a connected state.

[0066] In some embodiments, the first processor 111 is further configured to load the first program in the first storage module 113 into the first FPGA module 112;

[0067] The second processor 121 is further configured to load the second program in the second storage module 123 into the second FPGA module 122 .

[0068] Exemplarily, the first processor 111 can load the first program in the first storage module 113 into the first FPGA module 112 when it is powered on next time. The second processor 121 can load the second program in the second storage module 123 into the second FPGA module 122 when it is powered on next time.

[0069] In some embodiments, reference Figure 4 The indoor unit 11 further includes a first optical port 116 . The outdoor unit further includes a second optical port 124 .

[0070] The first optical port 116 is connected to the first FPGA module 112. The second optical port 124 is connected to the second FPGA module 122. The first optical port 116 and the second optical port 124 are connected via an optical fiber.

[0071] After the first processor 111 exchanges the second program with the first FPGA module 112, it is sent to the second FPGA module 122 via optical fiber. Exemplarily, the first FPGA module 112 can send the second program to the first optical port 116 via SERDES (SERializer / DESerializer), and the first optical port 116 converts the electrical signal into an optical signal via an optoelectronic conversion module, and sends it to the second optical port 124 via optical fiber. The second optical port 124 is connected to the second FPGA module 122, and the second optical port 124 receives the second program and then transmits it to the second FPGA module 122. SERDES is a high-speed serial interface used for high-speed serial transmission between devices, and can connect optical modules to form a fast transmission channel.

[0072] In some embodiments, reference Figure 5 , the first FPGA module 112 includes a first FPGA chip 1121. The second FPGA module 122 includes a second FPGA chip 1221 and a third FPGA chip 1222. The second FPGA chip 1221 and the third FPGA chip 1222 are connected. The second FPGA chip 1221 and the first FPGA chip 1121 are connected via an optical fiber. The second FPGA chip 1221 is used for modulation and demodulation, and the third FPGA chip 1222 is used for encoding and decoding.

[0073] The first storage module 113 includes a first memory 1131. The second storage module 123 includes a second memory 1231 and a third memory 1232. The second FPGA chip 1221, the third FPGA chip 1222, the second memory 1231 and the third memory 1232 are all connected to the second processor 121.

[0074] The first program includes a first subprogram. The second program includes a second subprogram and a third subprogram.

[0075] The second FPGA chip 1221 is used to send the received second subprogram and third subprogram to the second processor 121 through the third FPGA chip 1222 .

[0076] The second processor 121 is specifically used to fix the second subprogram into the second memory 1231 to update the program of the second FPGA chip 1221, and fix the third subprogram into the third memory 1232 to update the program of the third FPGA chip 1222.

[0077] Exemplarily, after receiving the program, the first processor 111 parses it, distinguishes the first subprogram, the second subprogram and the third subprogram, fixes the first subprogram to the first memory 1131 through the QSPI interface, and stores the second subprogram and the third subprogram in the target memory 115.

[0078] After receiving the second subprogram and the third subprogram, the second FPGA chip 1221 sends them to the third FPGA chip 1222 through an LVDS (Low Voltage Differential Signaling) interface. The LVDS interface is an inter-chip differential interface.

[0079] After receiving the second subprogram and the third subprogram, the second processor 121 parses them to distinguish the second subprogram from the third subprogram. Then, on the one hand, the second subprogram is solidified into the second memory 1231. When powered on next time, the second processor 121 loads the program stored in the second memory 1231 to the second FPGA chip 1221 through SELECTMAP to update the program of the second FPGA chip 1221. On the other hand, the third subprogram is solidified into the third memory 1232. When powered on next time, the second processor 121 loads the program stored in the third memory 1232 to the third FPGA chip 1222 through SELECTMAP to update the program of the third FPGA chip 1222.

[0080] SELECTMAP is a program configuration mode of FPGA. It is a general term for the method and interface by which the host computer configures the FPGA program after the FPGA is powered on.

[0081] The first optical port 116 is connected to the first FPGA chip 1121 . The second optical port 124 is connected to the second FPGA chip 1221 .

[0082] In some embodiments, reference Figure 5 The outdoor unit further includes a fourth memory 125. The fourth memory 125 is connected to the second FPGA chip 1221. The fourth memory 125 stores an initialization program of the second FPGA chip 1221.

[0083] The second FPGA chip 1221 is also used to read the initialization program in the fourth memory 125 to initialize itself.

[0084] The fourth memory 125 is used to store the initialization program of the second FPGA chip 1221. When the second processor 121 cannot load the program from the second memory 1231, the second FPGA chip 1221 loads the program from the fourth memory 125. For example, when there is no program of the second FPGA chip 1221 in the second memory 1231, it can be started from the fourth memory 125; for another example, when the second processor 121 cannot load the program to the second FPGA chip 1221 through SELECTMAP, the second FPGA chip 1221 can load the program from the fourth memory 125. The fourth memory 125 can be a FLASH memory.

[0085] In some embodiments, reference Figure 5 The first memory 1131, the second memory 1231, and the third memory 1232 are all FLASH memories.

[0086] Figure 6 A flowchart of a method for remotely updating a program of a scattering communication device provided in an embodiment of the present invention. The method is used for the above-mentioned scattering communication device. The scattering communication device includes an indoor unit 11 and an outdoor unit 12. The indoor unit 11 includes a first processor 111, a first field programmable logic gate array FPGA module 112 and a first storage module 113. The outdoor unit 12 includes a second processor 121, a second FPGA module 122 and a second storage module 123. A communication connection is established between the first FPGA module 112 and the second FPGA module 122 via an optical fiber; the method includes:

[0087] In S601, the first processor 111 receives a first program and a second program, wherein the first program is used to update a program of the first FPGA module 112, and the second program is used to update a program of the second FPGA module 122;

[0088] In S602, the first processor 111 solidifies the first program into the first storage module 113 to update the program of the first FPGA module 112;

[0089] In S603, when the first processor 111 detects that the optical fiber is in a connected state, the second program is sent to the second FPGA module 122 through the first FPGA module 112 and the optical fiber;

[0090] In S604 , the second processor 121 receives the second program transmitted by the second FPGA module 122 , and fixes the second program to the second storage module 123 to update the program of the second FPGA module 122 .

[0091] The technical effects of the remote updating method of the scatter communication device program provided by the embodiment of the present invention refer to the above-mentioned scatter communication device and will not be repeated here.

[0092] In some embodiments, the indoor unit 11 further includes a network port 114 , which is connected to the first processor 111 ; the first processor 111 receives the first program and the second program, including: the first processor 111 receives the first program and the second program through the network port 114 .

[0093] In some embodiments, the indoor unit 11 further includes a target memory 115, and the target memory 115 is connected to the first processor 111; when the first processor 111 detects that the optical fiber is in a connected state, the second program is sent to the second FPGA module 122 through the first FPGA module 112 and the optical fiber, including:

[0094] After receiving the second program, the first processor 111 stores the second program in the target memory 115, and when detecting that the optical fiber is in a connected state, reads the second program from the target memory 115 and sends the second program to the second FPGA module 122 through the first FPGA module 112 and the optical fiber.

[0095] In some embodiments, the first processor 111 loads the first program in the first storage module 113 to the first FPGA module 112 ; the second processor 121 loads the second program in the second storage module 123 to the second FPGA module 122 .

[0096] In some embodiments, the first FPGA module 112 includes a first FPGA chip 1121, and the second FPGA module 122 includes a second FPGA chip 1221 and a third FPGA chip 1222; the second FPGA chip 1221 and the third FPGA chip 1222 are connected, and a communication connection is established between the second FPGA chip 1221 and the first FPGA chip 1121 via an optical fiber; the second FPGA chip 1221 is used for modulation and demodulation, and the third FPGA chip 1222 is used for encoding and decoding;

[0097] The first storage module 113 includes a first memory 1131. The second storage module 123 includes a second memory 1231 and a third memory 1232; the second FPGA chip 1221, the third FPGA chip 1222, the second memory 1231 and the third memory 1232 are all connected to the second processor 121;

[0098] The first program includes a first subprogram, and the second program includes a second subprogram and a third subprogram;

[0099] The second FPGA chip 1221 sends the received second subprogram and third subprogram to the second processor 121 through the third FPGA chip 1222;

[0100] The second processor 121 solidifies the second subprogram into the second memory 1231 to update the program of the second FPGA chip 1221 , and solidifies the third subprogram into the third memory 1232 to update the program of the third FPGA chip 1222 .

[0101] In some embodiments, after the second processor 121 solidifies the second subprogram into the second memory 1231 and solidifies the third subprogram into the third memory 1232, the second processor 121 feeds back the update completion message to the host computer. Exemplarily, the second processor 121 sends the update completion message to the third FPGA chip 1222, and then the third FPGA chip 1222 sends it to the second FPGA chip 1221, the second FPGA chip 1221 sends it to the first optical port 116 through the second optical port 124, and then to the first FPGA chip 1121, the first FPGA chip 1121 sends it to the first processor 111, and the first processor 111 sends the update completion message to the host computer through the network port. After the host computer receives the message, it indicates that the update is completed, and the update completion message is displayed on the update software. If the host computer does not receive the update completion message after the timeout, it will re-initiate the update process, and the timeout time can be set to 10 minutes.

[0102] The above-mentioned scattering communication device and its program remote update method are described below through a specific implementation example. Figure 7 In this implementation example, the scattering communication device includes an indoor unit and an outdoor unit; the indoor unit includes a processor CPU1, a programmable logic device FPGA1, a storage chip FLASH1, a network port, a storage chip EMMC and an optical port 1. The network port is connected to CPU1. CPU1 is connected to FPGA1, FLASH1, and EMMC respectively, and FPGA1 is connected to optical port 1. The outdoor unit includes a processor CPU2, a programmable logic device FPGA2, a programmable logic device FPGA3, a storage chip FLASH2, a storage chip FLASH3, a storage chip FLASH4, and an optical port 2. FPGA2 is connected to optical port 2, FPGA3, and FLASH4. CPU2 is connected to FPGA2, FPGA3, FLASH2, and FLASH3. A communication connection is established between optical port 1 and optical port 2 via an optical fiber. The remote program update method of the scattering device includes:

[0103] STEP1: Install the program to update the software on the host computer. The host computer is connected to the processor CPU1 through the network port. The processor CPU1 parses the program and distinguishes three programs: the program I_P for updating FPGA1, the program O_P1 for updating FPGA2, and the program O_P2 for updating FPGA3.

[0104] STEP2: Update I_P to the storage chip FLASH1 through the QSPI interface, and store O_P1 and O_P2 in the storage chip EMMC.

[0105] STEP3: Check the fiber optic interface status. If it is connected, the processor CPU1 reads O_P1 and O_P2 in the EMMC.

[0106] STEP4: Processor CPU1 exchanges O_P1 and O_P2 programs to FPGA1 through direct memory access interface DMA. FPGA1 sends O_P1 and O_P2 programs to optical port 1 through high-speed serial interface SERDES. Optical port 1 converts electrical signals into optical signals through optoelectronic conversion module and sends O_P1 and O_P2 programs to optical port 2 through optical fiber.

[0107] STEP5: FPGA2 sends the program received by optical port 2 to FPGA3 through the inter-chip differential interface LVDS.

[0108] STEP6: FPGA3 sends the program to processor CPU2, and CPU2 parses O_P1 and O_P2.

[0109] STEP7: CPU2 fixes the program O_P1 of FPGA2 to FLASH2, and fixes the program O_P2 of FPGA3 to FLASH3.

[0110] STEP8: CPU2 sends the update completion message to FPGA3, then FGGA3 sends it to FPGA2, FPGA2 sends it to optical port 1 through optical port 2, then to FPGA1, and then to CPU1. CPU1 sends the update completion message to the host computer through the network port. After the host computer receives the message, it indicates that the update is completed. The update completion message is displayed on the update software. If the update completion message is not received for more than 10 minutes, the update process will be re-initiated.

[0111] STEP9: After the update is completed, the next time the power is turned on, the processor CPU1 loads the program stored in FLASH1 to FPGA1, the processor CPU2 loads the program stored in FLASH2 to FPGA2 through SELECTMAP, and the processor CPU2 loads the program stored in FLASH3 to FPGA3 through SELECTMAP.

[0112] STEP10: When there is no FPGA2 program in Flash2, or CPU2 cannot load FPGA2 through SELECTMAP, FPGA2 can load the initialization program from Flash4.

[0113] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0114] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0115] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0116] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0117] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0118] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0119] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A scattering communication device, characterized in that: It includes an indoor unit and an outdoor unit; the indoor unit includes a first processor, a first FPGA module and a first storage module; the first processor is connected to the first FPGA module and the first storage module respectively; the outdoor unit includes a second processor, a second FPGA module and a second storage module, the second processor is connected to the second FPGA module and the second storage module respectively; the first FPGA module and the second FPGA module are connected to each other through an optical fiber; The first processor is used to receive a first program and a second program, wherein the first program is used to update the program of the first FPGA module, and the second program is used to update the program of the second FPGA module; The first processor is further used to fix the first program to the first storage module to update the program of the first FPGA module; The first processor is further configured to send the second program to the second FPGA module through the first FPGA module and the optical fiber when detecting that the optical fiber is in a connected state; The second processor is used to receive the second program transmitted by the second FPGA module, and fix the second program to the second storage module to update the program of the second FPGA module; The first FPGA module includes a first FPGA chip, and the second FPGA module includes a second FPGA chip and a third FPGA chip; the second FPGA chip is connected to the third FPGA chip, and a communication connection is established between the second FPGA chip and the first FPGA chip via an optical fiber; the second FPGA chip is used for modulation and demodulation, and the third FPGA chip is used for encoding and decoding; The first storage module includes a first memory, and the second storage module includes a second memory and a third memory; the second FPGA chip, the third FPGA chip, the second memory and the third memory are all connected to the second processor; The first program includes a first subprogram, and the second program includes a second subprogram and a third subprogram; The second FPGA chip is used to send the received second subprogram and the third subprogram to the second processor through the third FPGA chip; The second processor is specifically used to fix the second subprogram into the second memory to update the program of the second FPGA chip, and fix the third subprogram into the third memory to update the program of the third FPGA chip; The outdoor unit further includes a fourth memory, the fourth memory is connected to the second FPGA chip; the fourth memory stores an initialization program of the second FPGA chip; The second FPGA chip is also used to read the initialization program in the fourth memory to initialize itself.

2. The scattering communication device according to claim 1, characterized in that: The indoor unit further includes a network port, and the network port is connected to the first processor; The first processor is specifically configured to receive the first program and the second program through the network port.

3. The scattering communication device according to claim 1, characterized in that: The indoor unit further comprises a target memory connected to the first processor; The first processor is specifically used to store the second program in the target memory after receiving the second program, and when detecting that the optical fiber is in a connected state, read the second program from the target memory and send the second program to the second FPGA module through the first FPGA module and the optical fiber.

4. The scattering communication device according to claim 1, characterized in that: The first processor is further configured to load the first program in the first storage module into the first FPGA module; The second processor is further configured to load the second program in the second storage module into the second FPGA module; The indoor unit further includes a first optical port, and the outdoor unit further includes a second optical port; The first optical port is connected to the first FPGA module, the second optical port is connected to the second FPGA module, and the first optical port and the second optical port are connected via an optical fiber.

5. The scattering communication device according to claim 1, characterized in that: The first memory, the second memory and the third memory are all FLASH memories.

6. A method for remotely updating a program of a scatter communication device, characterized in that: The method is applied to the scattering communication device as described in any one of claims 1 to 5 above; the method comprises: The first processor receives a first program and a second program, wherein the first program is used to update a program of the first FPGA module, and the second program is used to update a program of the second FPGA module; The first processor solidifies the first program into the first storage module to update the program of the first FPGA module; When the first processor detects that the optical fiber is in a connected state, the first processor sends the second program to the second FPGA module through the first FPGA module and the optical fiber; The second processor receives the second program transmitted by the second FPGA module, and fixes the second program to the second storage module to update the program of the second FPGA module.

7. The method according to claim 6, characterized in that The indoor unit further includes a network port, and the network port is connected to the first processor; The first processor receives a first program and a second program, including: The first processor receives the first program and the second program through the network port.

8. The method according to claim 7, characterized in that The indoor unit further comprises a target memory connected to the first processor; When the first processor detects that the optical fiber is in a connected state, sending the second program to the second FPGA module through the first FPGA module and the optical fiber, including: After receiving the second program, the first processor stores the second program in the target memory, and when detecting that the optical fiber is in a connected state, reads the second program from the target memory and sends the second program to the second FPGA module through the first FPGA module and the optical fiber.

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