Switching control method of motor drive control system

Abstract

The application discloses a switching control method of a motor driving control system. The method is applied to the motor driving control system, and the system comprises an MCU motor driving control module, an FPGA motor driving control module, a parallel communication module, a current collection module and a power module. The MCU motor driving control module comprises a first current signal collection end, a first power signal collection end, a first pulse signal output end and a first parallel communication end. The FPGA motor driving control module comprises a second current signal collection end, a second power signal collection end, a second pulse signal output end and a second parallel communication end. The method comprises the following steps: monitoring faults of each signal output end in the MCU and the FPGA motor driving control module through the parallel communication module; when any signal end in the MCU or the FPGA motor driving control module is faulty, switching the FPGA or the MCU motor driving control module to drive the motor to work; and thus, the reliable operation of the motor is ensured.

Description

Technical Field

[0001] The embodiments of the present invention relate to motor control technology, and more particularly to a switching control method for a motor drive control system. Background Technology

[0002] Pure electric vehicles generally use permanent magnet synchronous motors or three-phase asynchronous motors as drive motors. Vector control systems are often used to control the motors. According to the control core, common forms of vector control systems include: MCU, DSP or FPGA for individual control; however, using MCU, DSP or FPGA alone will relatively reduce the performance of the entire control system. Summary of the Invention

[0003] This invention provides a switching control method for a motor drive control system, which uses a combination of MCU and FPGA to form the entire motor drive control system. When a system fault occurs, the fault of each signal terminal is determined by monitoring and verification between the MCU and FPGA, and the control method is switched to ensure the reliable operation of the motor.

[0004] This invention provides a switching control method for a motor drive control system, which is applied to a motor drive control system including an MCU motor drive control module, an FPGA motor drive control module, a current acquisition module, a power supply module, and a parallel communication module.

[0005] The MCU motor drive control module includes a first current signal acquisition terminal, a first power signal acquisition terminal, a first pulse signal output terminal, and a first parallel communication terminal;

[0006] The FPGA motor drive control module includes a second current signal acquisition terminal, a second power signal acquisition terminal, a second pulse signal output terminal, and a second parallel communication terminal.

[0007] The output terminal of the current acquisition module is electrically connected to the first current signal acquisition terminal and the second current signal acquisition terminal; the power supply module is electrically connected to the first power signal acquisition terminal and the second power signal acquisition terminal; the parallel communication module is electrically connected to the first parallel communication terminal and the second parallel communication terminal respectively.

[0008] The switching control method includes:

[0009] The parallel communication module is used to monitor the first current signal acquisition terminal, the first power signal acquisition terminal, and the first pulse signal output terminal in the MCU motor drive control module for faults.

[0010] The parallel communication module is used to monitor the second current signal acquisition terminal, the second power signal acquisition terminal, and the second pulse signal output terminal in the FPGA motor drive control module for faults.

[0011] If any signal terminal in the MCU motor drive control module fails, the FPGA motor drive control module will be switched to drive the motor.

[0012] If any signal terminal in the FPGA motor drive control module fails, the MCU motor drive control module will be switched to drive the motor.

[0013] Optionally, fault monitoring is performed on the first current signal acquisition terminal in the MCU motor drive control module through the parallel communication module, including:

[0014] The first current signal acquisition terminal in the MCU motor drive control module receives the first phase current signal output by the current acquisition module.

[0015] The second current signal terminal in the FPGA motor drive control module receives the second phase current signal output by the current acquisition module; and sends the second phase current signal to the MCU motor drive control module through the parallel communication module.

[0016] The MCU motor drive control module performs fault monitoring on the first current signal acquisition terminal based on the first phase current signal and the second phase current signal.

[0017] Fault monitoring is performed on the second current signal acquisition terminal in the FPGA motor drive control module through the parallel communication module, including:

[0018] The MCU motor drive control module sends the first phase current signal to the FPGA motor drive control module through the parallel communication module;

[0019] The FPGA motor drive control module performs fault monitoring on the second current signal acquisition terminal based on the second phase current signal and the first phase current signal received by the second current signal terminal.

[0020] Optionally, fault monitoring is performed on the first power signal acquisition terminal in the MCU motor drive control module through the parallel communication module, including:

[0021] The first power signal acquisition terminal in the MCU motor drive control module receives the first power signal output by the power module.

[0022] The second power signal acquisition terminal in the FPGA motor drive control module receives the second power signal output by the power module; and sends the second power signal to the MCU motor drive control module through the parallel communication module.

[0023] The MCU motor drive control module performs fault monitoring on the first power signal acquisition terminal based on the first power signal and the second power signal.

[0024] Fault monitoring is performed on the second power signal acquisition terminal in the FPGA motor drive control module through the parallel communication module, including:

[0025] The MCU motor drive control module sends the first power signal to the FPGA motor drive control module through the parallel communication module;

[0026] The FPGA motor drive control module performs fault monitoring on the second power signal acquisition terminal based on the second power signal acquired by the second power signal acquisition terminal and the first power signal.

[0027] Optionally, the MCU motor drive control module further includes a first pulse signal acquisition terminal; the FPGA motor drive control module further includes a second pulse signal acquisition terminal.

[0028] The parallel communication module performs fault monitoring on the first pulse signal output terminal of the MCU motor drive control module, including:

[0029] The MCU motor drive control module outputs duty cycle information through the first pulse signal output terminal, and outputs the duty cycle information to the FPGA motor drive control module through the parallel communication module.

[0030] The FPGA motor drive control module captures the duty cycle information output by the first pulse signal output terminal through the second pulse signal capture terminal, and outputs the second duty cycle information.

[0031] The FPGA motor drive control module performs fault monitoring on the first pulse signal output terminal based on the first duty cycle information and the second duty cycle information.

[0032] The parallel communication module performs fault monitoring on the second pulse signal output terminal of the FPGA motor drive control module, including:

[0033] The FPGA motor drive control module outputs duty cycle information through the second pulse signal output terminal, and outputs the duty cycle information to the MCU motor drive control module through the parallel communication module to output third duty cycle information;

[0034] The MCU motor drive control module captures the duty cycle information output by the second pulse signal output terminal through the first pulse signal capture terminal, and outputs the fourth duty cycle information.

[0035] The MCU motor drive control module performs fault monitoring on the second pulse signal output terminal based on the third duty cycle information and the fourth duty cycle information.

[0036] Optionally, the MCU motor drive control module further includes a first GPIO output terminal and a first GPIO input terminal; the FPGA motor drive control module further includes a second GPIO output terminal and a second GPIO input terminal.

[0037] The switching control method further includes:

[0038] The parallel communication module is used to monitor the first GPIO output terminal of the MCU motor drive control module for faults.

[0039] The parallel communication module is used to monitor the faults of the second GPIO output terminal in the FPGA motor drive control module.

[0040] Optionally, fault monitoring is performed on the first GPIO output terminal of the MCU motor drive control module through the parallel communication module, including:

[0041] The MCU motor drive control module outputs high and low level information through the first GPIO output terminal, and outputs the high and low level information to the FPGA motor drive control module through the parallel communication module.

[0042] The FPGA motor drive control module receives the high and low level information output by the first GPIO output terminal through the second GPIO input terminal, and uses it as the second high and low level information.

[0043] The FPGA motor drive control module performs fault monitoring on the first GPIO output terminal based on the first high / low level information and the second high / low level information.

[0044] The parallel communication module performs fault monitoring on the second GPIO output of the FPGA motor drive control module, including:

[0045] The FPGA motor drive control module outputs high and low level information through the second GPIO output terminal, and outputs the high and low level information to the MCU motor drive control module through the parallel communication module to output third high and low level information.

[0046] The MCU motor drive control module receives the high and low level information output by the second GPIO output through the first GPIO input terminal and uses it as the fourth high and low level information.

[0047] The MCU motor drive control module performs fault monitoring on the second GPIO output terminal based on the third high / low level information and the fourth high / low level information.

[0048] Optionally, the switching control method further includes:

[0049] If the first GPIO output terminal in the MCU motor drive control module fails, the FPGA motor drive control module will be switched to drive the motor.

[0050] If the second GPIO output terminal in the FPGA motor drive control module fails, the MCU motor drive control module will be switched to drive the motor.

[0051] Optionally, the motor drive control system further includes an angular velocity acquisition module, a first buffer chip, and a second buffer chip; the MCU motor drive control module further includes a first SPI terminal; the FPGA motor drive control module further includes a first CAN terminal and a second SPI terminal; both the first SPI terminal and the second SPI terminal are electrically connected to the angular velocity acquisition module; the first pulse signal output terminal is electrically connected to the input terminal of the motor drive board through the first buffer chip; the second pulse signal output terminal is electrically connected to the input terminal of the motor drive board through the second buffer chip.

[0052] When the first power signal acquisition terminal, the first current signal acquisition terminal, the first pulse signal output terminal, or the first GPIO output terminal in the MCU motor drive control module fails, the MCU motor drive control module controls the first buffer chip to stop working. The FPGA motor drive control module outputs duty cycle information to the second pulse signal output terminal based on the power signal acquired by the second power signal acquisition terminal, the current signal acquired by the second current signal terminal, the angular velocity information acquired by the second SPI terminal, and the current reference value converted from the torque command received by the first CAN terminal, in order to drive the motor to work.

[0053] Optionally, the MCU motor drive control module further includes a second CAN terminal;

[0054] When any signal terminal in the FPGA motor drive control module fails, the MCU motor drive control module is switched to drive the motor, including:

[0055] When the second current signal acquisition terminal, the second power signal acquisition terminal, the second pulse signal output terminal, or the second GPIO output terminal in the FPGA motor drive control module fails, the FPGA motor drive control module controls the second buffer chip to stop working. The MCU motor drive control module outputs duty cycle information to the first pulse signal output terminal based on the current signal acquired by the first current signal acquisition terminal, the power signal acquired by the first power signal terminal, the angular velocity information acquired by the first SPI terminal, and the current reference value converted from the torque command received by the second CAN terminal, in order to drive the motor to work.

[0056] Optionally, the method further includes:

[0057] The MCU motor drive control module and the FPGA motor drive control module are divided into regions to select at least one of the following at the center of different regions: a first current signal acquisition terminal, a first power signal acquisition terminal, a first pulse signal output terminal, a second current signal acquisition terminal, a second power signal acquisition terminal, and a second pulse signal output terminal.

[0058] In this embodiment of the invention, a parallel communication module is used to monitor the first current signal acquisition terminal, the first power signal acquisition terminal, and the first pulse signal output terminal in the MCU motor drive control module for faults; and the same parallel communication module is used to monitor the second current signal acquisition terminal, the second power signal acquisition terminal, and the second pulse signal output terminal in the FPGA motor drive control module for faults. When any signal terminal in the MCU motor drive control module fails, the FPGA motor drive control module is switched to drive the motor; conversely, when any signal terminal in the FPGA motor drive control module fails, the MCU motor drive control module is switched to drive the motor. This achieves a motor drive control system formed by combining MCU and FPGA, where monitoring and verification of each signal terminal between the MCU and FPGA determines faults in each signal terminal within the system, and the corresponding motor drive control module is switched to ensure reliable motor operation. Attached Figure Description

[0059] Figure 1 This is a flowchart illustrating a switching control method for a motor drive control system provided in an embodiment of the present invention.

[0060] Figure 2 This is a schematic diagram of the structure of a motor drive control system provided in an embodiment of the present invention;

[0061] Figure 3 This is a flowchart illustrating another switching control method for a motor drive control system provided in an embodiment of the present invention. Detailed Implementation

[0062] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0063] Figure 1 This is a flowchart illustrating a switching control method for a motor drive control system provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the switching control method includes:

[0064] S100: The first current signal acquisition terminal, the first power signal acquisition terminal, and the first pulse signal output terminal in the MCU motor drive control module are monitored for faults through the parallel communication module; the second current signal acquisition terminal, the second power signal acquisition terminal, and the second pulse signal output terminal in the FPGA motor drive control module are monitored for faults through the parallel communication module.

[0065] The switching control method of this motor drive control system is applied to the motor drive control system. Figure 2 This is a schematic diagram of the structure of a motor drive control system provided in an embodiment of the present invention, as shown below. Figure 2As shown, the motor drive control system 01 includes an MCU motor drive control module 10, an FPGA motor drive control module 20, a parallel communication module 30, a current acquisition module 40, and a power supply module 50. The MCU motor drive control module 10 includes a first current signal acquisition terminal, a first power signal acquisition terminal, a first pulse signal output terminal, a first parallel communication terminal, and a second CAN terminal. The FPGA motor drive control module 20 includes a second current signal acquisition terminal, a second power signal acquisition terminal, a second pulse signal output terminal, a second parallel communication terminal, and a first CAN terminal. The parallel communication module 30 is electrically connected to the first parallel communication terminal and the second parallel communication terminal, respectively. The output terminal of the current acquisition module 40 is electrically connected to the first current signal acquisition terminal and the second current signal acquisition terminal. The power supply module 50 is electrically connected to the first power signal acquisition terminal and the second power signal acquisition terminal. Under normal operation, the motor drive control system operates as follows: The MCU motor drive control module 10 sends the current reference value converted from the torque command received at its second CAN terminal to the FPGA motor drive control module 20. The FPGA motor drive control module 20 then uses a certain control algorithm to output corresponding high-precision duty cycle information to the second pulse signal output terminal based on the power signal acquired by the second power signal acquisition terminal, the current signal acquired by the second current signal acquisition terminal, and the current reference value, thereby driving the motor to operate normally. Alternatively, the FPGA motor drive control module 20 sends the current reference value converted from the torque command received at its first CAN terminal to the MCU motor drive control module 10. The MCU motor drive control module 10 then uses a certain control algorithm to output corresponding high-precision duty cycle information to the first pulse signal output terminal based on the power signal acquired by the first power signal acquisition terminal, the current signal acquired by the first current signal acquisition terminal, and the current reference value, thereby driving the motor to operate normally. The second current signal acquisition terminal can acquire the current signal output by the current acquisition module 40 through an external ADC chip; the first current signal acquisition terminal can be an ADC sampling terminal, which can directly acquire the current signal output by the current acquisition module 40.

[0066] In actual operation, some key signal terminals in the system may fail, causing the motor to fail to drive normally. This solution uses the parallel communication module 30 to monitor and verify each signal terminal between the MCU and FPGA to determine whether the first current signal acquisition terminal, the first power signal acquisition terminal, and the first pulse signal output terminal in the MCU motor drive control module have failed; and to determine whether the second current signal acquisition terminal, the second power signal acquisition terminal, and the second pulse signal output terminal in the FPGA motor drive control module have failed.

[0067] S110. If any signal terminal in the MCU motor drive control module fails, the FPGA motor drive control module will be switched to drive the motor.

[0068] Specifically, if any signal terminal in the MCU motor drive control module or the FPGA motor drive control module fails, the FPGA motor drive control module or the MCU motor drive control module will be switched to drive the motor. In this way, the entire motor drive control system is formed by combining MCU and FPGA. By monitoring and verifying the signal terminals between the MCU and FPGA, the faults of each signal terminal in each system are determined, and the corresponding motor drive control module is switched to ensure the reliable operation of the motor.

[0069] Based on the above embodiments, further refinement is made. Figure 3 This is a flowchart illustrating another switching control method for a motor drive control system provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the switching control method includes:

[0070] S210. The MCU motor drive control module and the FPGA motor drive control module are divided into regions to select at least one of the following in different regions: first current signal acquisition terminal, first power signal acquisition terminal, first pulse signal output terminal, first GPIO output terminal, second current signal acquisition terminal, second power signal acquisition terminal, second pulse signal output terminal and second GPIO output terminal.

[0071] The MCU motor drive control module and the FPGA motor drive control module are mostly BGA or QPFP packaged chips. The MCU motor drive control module and the FPGA motor drive control module are divided into different areas according to space. Then, pins are selected in each area for monitoring. There is at least one monitored pin in each area. These pins can be current signal acquisition terminals, power signal acquisition terminals, pulse signal output terminals and GPIO output terminals, so as to realize the monitoring of each signal pin in the space.

[0072] S220. The first current signal acquisition terminal, the first power signal acquisition terminal, and the first pulse signal output terminal in the MCU motor drive control module are monitored for faults through the parallel communication module; the second current signal acquisition terminal, the second power signal acquisition terminal, and the second pulse signal output terminal in the FPGA motor drive control module are monitored for faults through the parallel communication module.

[0073] The specific process for fault monitoring of the first current signal acquisition terminal, the first power signal acquisition terminal, the first pulse signal output terminal, the second current signal acquisition terminal, the second power signal acquisition terminal, and the second pulse signal output terminal is as follows:

[0074] Fault monitoring of the first current signal acquisition terminal in the MCU motor drive control module via a parallel communication module includes: the first current signal acquisition terminal in the MCU motor drive control module receives the first phase current signal Iu output by the current acquisition module; the second current signal acquisition terminal in the FPGA motor drive control module receives the second phase current signal Iu1 output by the current acquisition module; and sends the second phase current signal to the MCU motor drive control module via the parallel communication module; the MCU motor drive control module performs fault monitoring of the first current signal acquisition terminal based on the first phase current signal Iu and the second phase current signal Iu1; for example, when |Iu-Iu1|≥I and Iu≤I0, a short circuit to ground fault occurs at the first current signal acquisition terminal; I and I0 are calibrated values. Similarly, fault monitoring of the second current signal acquisition terminal in the FPGA motor drive control module via a parallel communication module includes: the MCU motor drive control module sends the first phase current signal Iu to the FPGA motor drive control module via the parallel communication module; the FPGA motor drive control module performs fault monitoring of the second current signal acquisition terminal based on the second phase current signal Iu1 and the first phase current signal Iu received by the second current signal acquisition terminal. For example, when |Iu-Iu1|≥I and Iu1≤I0, a short circuit to ground fault occurs at the second current signal acquisition terminal; I and I0 are both calibrated values.

[0075] Fault monitoring of the first power signal acquisition terminal in the MCU motor drive control module via a parallel communication module includes: the first power signal acquisition terminal in the MCU motor drive control module receiving a first power signal output by the power module; the second power signal acquisition terminal in the FPGA motor drive control module receiving a second power signal output by the power module; and sending the second power signal to the MCU motor drive control module via the parallel communication module; the MCU motor drive control module performing fault monitoring of the first power signal acquisition terminal based on the first and second power signals. Similarly, fault monitoring of the second power signal acquisition terminal in the FPGA motor drive control module via a parallel communication module includes: the MCU motor drive control module sending the first power signal to the FPGA motor drive control module via the parallel communication module; and the FPGA motor drive control module performing fault monitoring of the second current signal acquisition terminal based on the second power signal acquired by the second power signal acquisition terminal and the first power signal.

[0076] Optionally, the MCU motor drive control module further includes a first pulse signal acquisition terminal; the FPGA motor drive control module further includes a second pulse signal acquisition terminal; fault monitoring of the first pulse signal output terminal in the MCU motor drive control module is performed through a parallel communication module, including: the MCU motor drive control module outputs duty cycle information through the first pulse signal output terminal, and outputs the first duty cycle information to the FPGA motor drive control module through the parallel communication module; the FPGA motor drive control module captures the duty cycle information output by the first pulse signal output terminal through the second pulse signal acquisition terminal, and outputs second duty cycle information; the FPGA motor drive control module performs fault monitoring of the first pulse signal output terminal based on the first duty cycle information and the second duty cycle information. For example, when the first duty cycle information and the second duty cycle information are greater than 5%, a fault is determined to have occurred at the first pulse signal output terminal. Similarly, fault monitoring of the second pulse signal output terminal in the FPGA motor drive control module is performed through a parallel communication module, including: the FPGA motor drive control module outputs duty cycle information through the second pulse signal output terminal, and outputs third duty cycle information to the MCU motor drive control module through the parallel communication module; the MCU motor drive control module captures the duty cycle information output by the second pulse signal output terminal through the first pulse signal capture terminal, and outputs fourth duty cycle information; the MCU motor drive control module performs fault monitoring of the second pulse signal output terminal based on the third and fourth duty cycle information. For example, when the third duty cycle information and the fourth duty cycle information are greater than 5%, a fault is determined to have occurred at the second pulse signal output terminal.

[0077] S230. The first GPIO output terminal in the MCU motor drive control module is monitored for faults through the parallel communication module; the second GPIO output terminal in the FPGA motor drive control module is monitored for faults through the parallel communication module.

[0078] Among them, reference Figure 2The MCU motor drive control module 10 also includes a first GPIO output terminal and a first GPIO input terminal; the FPGA motor drive control module 20 also includes a second GPIO output terminal and a second GPIO input terminal; in actual operation, for example, the first GPIO output terminal and the second GPIO output terminal can be electrically connected to the power module 50; the first GPIO output terminal and the second GPIO output terminal output high and low level information to the power module 50 so that the power module 50 outputs a power signal. Understandably, when the first GPIO output and the second GPIO output fail, the motor cannot be driven or controlled. Therefore, fault monitoring of the first and second GPIO outputs is necessary. Specifically, fault monitoring of the first GPIO output in the MCU motor drive control module 10 is performed via a parallel communication module. This includes: the MCU motor drive control module 10 outputs high and low level information through the first GPIO output, and outputs the high and low level information to the FPGA motor drive control module 20 via the parallel communication module; the FPGA motor drive control module 20 receives the high and low level information output from the first GPIO output through the second GPIO input, and uses it as the second high and low level information; the FPGA motor drive control module 20... The first GPIO output is monitored for faults based on the first high / low level information and the second high / low level information. Similarly, the second GPIO output in the FPGA motor drive control module 20 is monitored for faults through the parallel communication module, including: the FPGA motor drive control module 20 outputs high / low level information through the second GPIO output, and outputs the high / low level information to the MCU motor drive control module 10 through the parallel communication module 30 as the third high / low level information; the MCU motor drive control module 10 receives the high / low level information output by the second GPIO output through the first GPIO input and uses it as the fourth high / low level information; the MCU motor drive control module 10 monitors the second GPIO output for faults based on the third high / low level information and the fourth high / low level information.

[0079] S240. If any signal terminal in the MCU motor drive control module fails, the FPGA motor drive control module will be switched to drive the motor.

[0080] Among them, reference Figure 2The motor drive control system also includes an angular velocity acquisition module 60, a first buffer chip 70, and a second buffer chip 80; the MCU motor drive control module 10 also includes a first SPI terminal; the FPGA motor drive control module 20 also includes a second SPI terminal; both the first SPI terminal and the second SPI terminal are electrically connected to the angular velocity acquisition module 60; the first pulse signal output terminal is electrically connected to the input terminal of the motor drive board through the first buffer chip 70; the second pulse signal output terminal is electrically connected to the input terminal of the motor drive board through the second buffer chip 80. When the first power signal acquisition terminal, the first current signal acquisition terminal, the first pulse signal output terminal, or the first GPIO output terminal in the MCU motor drive control module malfunctions, the MCU motor drive control module outputs an enable signal to the first buffer chip 70, controlling the first buffer chip 70 to not work, ensuring that the first pulse signal output terminal of the MCU motor drive control module cannot output a duty cycle signal to the motor drive board, thus not affecting the output duty cycle signal of the FPGA motor drive control module; the FPGA motor drive control module 20 then outputs duty cycle information through the second pulse signal output terminal to drive the motor to work based on the power signal acquired by the second power signal acquisition terminal, the current signal acquired by the second current signal acquisition terminal, the angular velocity information acquired by the second SPI terminal, and the current reference value converted from the torque command received by the first CAN terminal.

[0081] When a fault occurs in the second current signal acquisition terminal, second power signal acquisition terminal, second pulse signal output terminal, or second GPIO output terminal of the FPGA motor drive control module, the FPGA motor drive control module controls the second buffer chip to stop working. This ensures that the second pulse signal output terminal of the FPGA motor drive control module cannot output a duty cycle signal to the motor drive board, thus not affecting the output of the duty cycle signal by the MCU motor drive control module. The MCU motor drive control module then outputs duty cycle information to the first pulse signal output terminal based on the current signal acquired by the first current signal acquisition terminal, the power signal acquired by the first power signal acquisition terminal, the angular velocity information acquired by the first SPI terminal, and the current reference value converted from the torque command received by the second CAN terminal, to drive the motor. Thus, this proposal uses a combination of MCU and FPGA to form the entire motor drive control system. By monitoring and verifying the signal terminals between the MCU and FPGA, faults in each signal terminal within the system are determined, and the corresponding motor drive control module is switched to ensure reliable motor operation.

[0082] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A switching control method for a motor drive control system, characterized in that, It is applied to a motor drive control system, which includes an MCU motor drive control module, an FPGA motor drive control module, a current acquisition module, a power supply module, and a parallel communication module; The MCU motor drive control module includes a first current signal acquisition terminal, a first power signal acquisition terminal, a first pulse signal output terminal, and a first parallel communication terminal; The FPGA motor drive control module includes a second current signal acquisition terminal, a second power signal acquisition terminal, a second pulse signal output terminal, and a second parallel communication terminal. The output terminal of the current acquisition module is electrically connected to the first current signal acquisition terminal and the second current signal acquisition terminal; the power supply module is electrically connected to the first power signal acquisition terminal and the second power signal acquisition terminal; the parallel communication module is electrically connected to the first parallel communication terminal and the second parallel communication terminal respectively. The switching control method includes: The parallel communication module is used to monitor the first current signal acquisition terminal, the first power signal acquisition terminal, and the first pulse signal output terminal in the MCU motor drive control module for faults. The parallel communication module is used to monitor the second current signal acquisition terminal, the second power signal acquisition terminal, and the second pulse signal output terminal in the FPGA motor drive control module for faults. If any signal terminal in the MCU motor drive control module fails, the FPGA motor drive control module will be switched to drive the motor. If any signal terminal in the FPGA motor drive control module fails, the MCU motor drive control module will be switched to drive the motor. The MCU motor drive control module further includes a first pulse signal acquisition terminal; the FPGA motor drive control module further includes a second pulse signal acquisition terminal. The parallel communication module performs fault monitoring on the first pulse signal output terminal of the MCU motor drive control module, including: The MCU motor drive control module outputs duty cycle information through the first pulse signal output terminal, and outputs the duty cycle information to the FPGA motor drive control module through the parallel communication module. The FPGA motor drive control module captures the duty cycle information output by the first pulse signal output terminal through the second pulse signal capture terminal, and outputs the second duty cycle information. The FPGA motor drive control module performs fault monitoring on the first pulse signal output terminal based on the first duty cycle information and the second duty cycle information. The parallel communication module performs fault monitoring on the second pulse signal output terminal of the FPGA motor drive control module, including: The FPGA motor drive control module outputs duty cycle information through the second pulse signal output terminal, and outputs the duty cycle information to the MCU motor drive control module through the parallel communication module to output third duty cycle information; The MCU motor drive control module captures the duty cycle information output by the second pulse signal output terminal through the first pulse signal capture terminal, and outputs the fourth duty cycle information. The MCU motor drive control module performs fault monitoring on the second pulse signal output terminal based on the third duty cycle information and the fourth duty cycle information.

2. The switching control method of the motor drive control system according to claim 1, characterized in that, Fault monitoring is performed on the first current signal acquisition terminal in the MCU motor drive control module through the parallel communication module, including: The first current signal acquisition terminal in the MCU motor drive control module receives the first phase current signal output by the current acquisition module. The second current signal acquisition terminal in the FPGA motor drive control module receives the second phase current signal output by the current acquisition module; and sends the second phase current signal to the MCU motor drive control module through the parallel communication module. The MCU motor drive control module performs fault monitoring on the first current signal acquisition terminal based on the first phase current signal and the second phase current signal. Fault monitoring is performed on the second current signal acquisition terminal in the FPGA motor drive control module through the parallel communication module, including: The MCU motor drive control module sends the first phase current signal to the FPGA motor drive control module through the parallel communication module; The FPGA motor drive control module performs fault monitoring on the second current signal acquisition terminal based on the second phase current signal and the first phase current signal received by the second current signal acquisition terminal.

3. The switching control method of the motor drive control system according to claim 1, characterized in that, The parallel communication module performs fault monitoring on the first power signal acquisition terminal in the MCU motor drive control module, including: The first power signal acquisition terminal in the MCU motor drive control module receives the first power signal output by the power module. The second power signal acquisition terminal in the FPGA motor drive control module receives the second power signal output by the power module; and sends the second power signal to the MCU motor drive control module through the parallel communication module. The MCU motor drive control module performs fault monitoring on the first power signal acquisition terminal based on the first power signal and the second power signal. Fault monitoring is performed on the second power signal acquisition terminal in the FPGA motor drive control module through the parallel communication module, including: The MCU motor drive control module sends the first power signal to the FPGA motor drive control module through the parallel communication module; The FPGA motor drive control module performs fault monitoring on the second power signal acquisition terminal based on the second power signal acquired by the second power signal acquisition terminal and the first power signal.

4. The switching control method of the motor drive control system according to claim 1, characterized in that, The MCU motor drive control module further includes a first GPIO output terminal and a first GPIO input terminal; the FPGA motor drive control module further includes a second GPIO output terminal and a second GPIO input terminal. The switching control method further includes: The parallel communication module is used to monitor the first GPIO output terminal of the MCU motor drive control module for faults. The parallel communication module is used to monitor the faults of the second GPIO output terminal in the FPGA motor drive control module.

5. The switching control method of the motor drive control system according to claim 4, characterized in that, The parallel communication module performs fault monitoring on the first GPIO output of the MCU motor drive control module, including: The MCU motor drive control module outputs high and low level information through the first GPIO output terminal, and outputs the high and low level information to the FPGA motor drive control module through the parallel communication module. The FPGA motor drive control module receives the high and low level information output by the first GPIO output terminal through the second GPIO input terminal, and uses it as the second high and low level information. The FPGA motor drive control module performs fault monitoring on the first GPIO output terminal based on the first high / low level information and the second high / low level information. The parallel communication module performs fault monitoring on the second GPIO output of the FPGA motor drive control module, including: The FPGA motor drive control module outputs high and low level information through the second GPIO output terminal, and outputs the high and low level information to the MCU motor drive control module through the parallel communication module to output third high and low level information. The MCU motor drive control module receives the high and low level information output by the second GPIO output through the first GPIO input terminal and uses it as the fourth high and low level information. The MCU motor drive control module performs fault monitoring on the second GPIO output terminal based on the third high / low level information and the fourth high / low level information.

6. The switching control method of the motor drive control system according to claim 5, characterized in that, The switching control method further includes: If the first GPIO output terminal in the MCU motor drive control module fails, the FPGA motor drive control module will be switched to drive the motor. If the second GPIO output terminal in the FPGA motor drive control module fails, the MCU motor drive control module will be switched to drive the motor.

7. The switching control method of the motor drive control system according to claim 6, characterized in that, The motor drive control system further includes an angular velocity acquisition module, a first buffer chip, and a second buffer chip; the MCU motor drive control module further includes a first SPI terminal; the FPGA motor drive control module further includes a first CAN terminal and a second SPI terminal; both the first SPI terminal and the second SPI terminal are electrically connected to the angular velocity acquisition module; the first pulse signal output terminal is electrically connected to the input terminal of the motor drive board through the first buffer chip; the second pulse signal output terminal is electrically connected to the input terminal of the motor drive board through the second buffer chip; when the first power signal acquisition terminal, the first current signal acquisition terminal, the first pulse signal output terminal, or the first GPIO output terminal in the MCU motor drive control module fails, the MCU motor drive control module controls the first buffer chip to not work, and the FPGA motor drive control module outputs duty cycle information to the second pulse signal output terminal to drive the motor to work based on the power signal acquired by the second power signal acquisition terminal, the current signal acquired by the second current signal acquisition terminal, the angular velocity information acquired by the second SPI terminal, and the current reference value converted from the torque command received by the first CAN terminal.

8. The switching control method of the motor drive control system according to claim 7, characterized in that, The MCU motor drive control module also includes a second CAN terminal; When any signal terminal in the FPGA motor drive control module fails, the MCU motor drive control module is switched to drive the motor, including: When the second current signal acquisition terminal, the second power signal acquisition terminal, the second pulse signal output terminal, or the second GPIO output terminal in the FPGA motor drive control module fails, the FPGA motor drive control module controls the second buffer chip to stop working. The MCU motor drive control module outputs duty cycle information to the first pulse signal output terminal based on the current signal acquired by the first current signal acquisition terminal, the power signal acquired by the first power signal terminal, the angular velocity information acquired by the first SPI terminal, and the current reference value converted from the torque command received by the second CAN terminal, in order to drive the motor to work.

9. The switching control method of the motor drive control system according to claim 1, characterized in that, Also includes: The MCU motor drive control module and the FPGA motor drive control module are divided into regions to select at least one of the following at the center of different regions: a first current signal acquisition terminal, a first power signal acquisition terminal, a first pulse signal output terminal, a second current signal acquisition terminal, a second power signal acquisition terminal, and a second pulse signal output terminal.

Images