Potential generating circuits, inverters, delay circuits and logic gate circuits

Abstract

The present application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit includes: a first transistor and a second transistor, the potential of the substrate end of the first transistor changes with the change of a first parameter, the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process of the potential generating circuit, and the potential of the substrate end of the second transistor changes with the change of the first parameter. Among them, the gate end of the first transistor is connected to the drain end of the first transistor, the substrate end of the first transistor serves as the first output end of the potential generating circuit, the gate end of the second transistor is connected to the drain end of the second transistor, and the substrate end of the second transistor serves as the second output end of the potential generating circuit. Thus, the first output end and the second output end can respectively output a potential that changes with any one of the power supply voltage, the operating temperature and the manufacturing process.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. Background Art

[0002] At present, delay circuits are often used in semiconductor components. Delay circuits are circuits that can delay pulse signals for a certain period of time. When delay circuits are used in dynamic random access memory (DRAM), it is often necessary to accurately control the delay time of the delay circuit. The delay circuit needs to meet the requirement that the delay time changes little when parameters such as power supply voltage, operating temperature, and manufacturing process change.

[0003] Figure 1 It is a schematic diagram of an input signal and an output signal after a delay circuit. After the input signal passes through the delay circuit, a delayed signal is output. Figure 1 As shown, the output signal is the signal after the input signal is delayed by time T. Figure 1 The illustrated case is that both the rising edge and the falling edge of the input signal are delayed by time T. There is also a case that only the rising edge of the input signal is delayed by time T or only the falling edge of the input signal is delayed by time T.

[0004] In the existing delay circuit, the delay time T will change greatly (increase or decrease) with the change of power supply voltage, operating temperature and manufacturing process, which will affect the accuracy of the delay time. How to reduce the influence of the change of the above parameters on the delay time T of the delay circuit so that the change of the delay time T is smaller is an urgent problem to be solved. Summary of the invention

[0005] The present application provides a potential generating circuit, which can output a potential that changes with any one of a supply voltage, an operating temperature and a manufacturing process.

[0006] The present application provides an inverter, which can reduce the change of the delay time T of the inverter and improve the control capability of the inverter on the accuracy of the delay time.

[0007] The present application provides a delay circuit to reduce the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the delay time T of the delay circuit, so that the change of the delay time T is smaller.

[0008] The present application provides a logic gate circuit to reduce the influence of the manufacturing process, power supply voltage and operating temperature of the logic gate circuit on the delay time T of the logic gate circuit, so that the change of the delay time T is smaller.

[0009] In a first aspect, the present application provides a potential generating circuit, comprising:

[0010] a first transistor, wherein the potential of a substrate terminal of the first transistor changes with a first parameter, and the first parameter is any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit;

[0011] a second transistor, wherein a potential at a substrate terminal of the second transistor changes as the first parameter changes;

[0012] Among them, the gate terminal of the first transistor is connected to the drain terminal of the first transistor, and the substrate terminal of the first transistor serves as the first output terminal of the potential generating circuit; the gate terminal of the second transistor is connected to the drain terminal of the second transistor, and the substrate terminal of the second transistor serves as the second output terminal of the potential generating circuit.

[0013] The potential generating circuit provided by the present application is provided with a first transistor and a second transistor, wherein the gate terminal of the first transistor is connected to the drain terminal of the first transistor, the substrate terminal of the first transistor serves as the first output terminal of the potential generating circuit, the gate terminal of the second transistor is connected to the drain terminal of the second transistor, and the substrate terminal of the second transistor serves as the second output terminal of the potential generating circuit. Since the potential of the substrate terminal of the first transistor changes with the first parameter, the potential of the substrate terminal of the second transistor changes with the first parameter, thus, the first output terminal and the second output terminal can respectively output a potential that changes with any one of the supply voltage, the operating temperature and the manufacturing process.

[0014] Optionally, the first parameter is the power supply voltage or operating temperature of the potential generating circuit, and the potential of the substrate end of the first transistor increases as the first parameter increases, and the potential of the substrate end of the first transistor decreases as the first parameter decreases; the potential of the substrate end of the second transistor decreases as the first parameter increases, and the potential of the substrate end of the second transistor increases as the first parameter decreases.

[0015] Optionally, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0016] Optionally, the source terminal of the first transistor is connected to a first voltage node, the source terminal of the second transistor is connected to a second voltage node, and the drain terminal of the first transistor is connected to the drain terminal of the second transistor.

[0017] Optionally, also include:

[0018] A constant current source, wherein a first end of the constant current source is connected to the second voltage node, and a second end of the constant current source is connected to a third voltage node.

[0019] Optionally, also include:

[0020] A first error amplifier, forming a first feedback loop with the second transistor, wherein a substrate terminal of the second transistor is connected to a voltage node of the first feedback loop;

[0021] A second error amplifier and a third transistor, wherein the second error amplifier and the third transistor form a second feedback loop, and a substrate terminal of the first transistor is connected to a voltage node of the second feedback loop.

[0022] Optionally, a negative input terminal of the first error amplifier is connected to the second voltage node, a positive input terminal of the first error amplifier is connected to a first reference voltage, and an output terminal of the first error amplifier is connected to a substrate terminal of the second transistor;

[0023] The negative input terminal of the second error amplifier is connected to the second reference voltage, the positive input terminal of the second error amplifier is connected to the fourth voltage node, the output terminal of the second error amplifier is connected to the gate terminal of the third transistor, the source terminal of the third transistor is connected to the first voltage node, the drain terminal of the third transistor is coupled to the fourth voltage node through a first resistor, and the output terminal of the first error amplifier is coupled to the fourth voltage node through a second resistor.

[0024] Optionally, the first voltage node is connected to a power supply terminal, the first reference voltage is connected to a ground terminal, and a potential of the third voltage node is less than a potential of the first reference voltage.

[0025] Optionally, also include:

[0026] A constant current source, wherein a first end of the constant current source is connected to the third voltage node, and a second end of the constant current source is connected to the first voltage node.

[0027] Optionally, also include:

[0028] A first error amplifier, forming a first feedback loop with the first transistor, wherein a substrate terminal of the first transistor is connected to a voltage node of the first feedback loop;

[0029] A second error amplifier and a third transistor, wherein the second error amplifier and the third transistor form a second feedback loop, and a substrate terminal of the second transistor is connected to a voltage node of the second feedback loop.

[0030] Optionally, a negative input terminal of the first error amplifier is connected to the first voltage node, a positive input terminal of the first error amplifier is connected to a first reference voltage, and an output terminal of the first error amplifier is connected to a substrate terminal of the first transistor;

[0031] The negative input terminal of the second error amplifier is connected to the second reference voltage, the positive input terminal of the second error amplifier is connected to the fourth voltage node, the output terminal of the second error amplifier is connected to the gate terminal of the third transistor, the source terminal of the third transistor is connected to the second voltage node, the drain terminal of the third transistor is coupled to the fourth voltage node through the second resistor, and the output terminal of the first error amplifier is coupled to the fourth voltage node through the first resistor.

[0032] Optionally, the second voltage node is connected to a ground terminal, the first reference voltage is connected to a power supply terminal, and a potential of the third voltage node is greater than a potential of the first reference voltage.

[0033] Optionally, also include:

[0034] a first buffer connected to the first output terminal and outputting a first substrate potential, wherein a value of the first substrate potential is equal to a potential value of a substrate terminal of the first transistor;

[0035] A second buffer is connected to the second output terminal and outputs a second substrate potential, wherein a value of the second substrate potential is equal to a potential value of a substrate terminal of the second transistor.

[0036] In a second aspect, the present application provides a delay circuit, comprising: a potential generating circuit as described in the first aspect and any possible implementation manner of the first aspect;

[0037] A delay unit, the delay unit comprising a first inverter, the first inverter comprising a fourth transistor and a fifth transistor, a substrate terminal of the fourth transistor being connected to the potential of the substrate terminal of the first transistor, and a substrate terminal of the fifth transistor being connected to the potential of the substrate terminal of the second transistor;

[0038] or,

[0039] A potential generating circuit as described in a possible implementation manner of the first aspect;

[0040] A delay unit, wherein the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the first substrate potential, and the substrate end of the fifth transistor is connected to the second substrate potential.

[0041] The delay circuit provided in the present application, since the potential of the substrate end of the first transistor in the potential generating circuit can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process, can provide the substrate end of the fourth transistor with a first substrate potential that changes with the change of the first parameter, and the potential of the substrate end of the second transistor can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process, so as to provide the substrate end of the fifth transistor with a second substrate potential that changes with the change of the first parameter, therefore, the current flowing through the two transistors of the first inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the delay time T of the delay circuit changes less, thereby improving the control ability of the delay circuit on the accuracy of the delay time.

[0042] Optionally, the ratio of the channel length of the first transistor to the channel length of the fourth transistor is H, the ratio of the channel length of the second transistor to the channel length of the fifth transistor is L, the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M, the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N, and H is equal to L, and M is equal to N.

[0043] In a third aspect, the present application provides an inverter, comprising:

[0044] A P-type transistor and an N-type transistor, wherein the source terminal of the P-type transistor is connected to the power supply terminal, the drain terminal of the P-type transistor is connected to the drain terminal of the N-type transistor, the source terminal of the N-type transistor is connected to the ground terminal, the gate terminal of the P-type transistor is connected to the gate terminal of the N-type transistor and serves as the input terminal of the inverter, and the drain terminal of the P-type transistor serves as the output terminal of the inverter;

[0045] The substrate end of the P-type transistor is connected to a first substrate potential, and the substrate end of the N-type transistor is connected to a second substrate potential. The first substrate potential changes with a first parameter, and the second substrate potential changes with the first parameter. The first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the inverter.

[0046] The inverter provided in the present application has a first substrate potential that can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process, so that the first substrate potential that changes with the change of the first parameter can be provided to the substrate end of TP1, and the second substrate potential can change with the change of the power supply voltage, the operating temperature and the manufacturing process, so that the second substrate potential that changes with the change of the first parameter can be provided to the substrate end of TN1. Therefore, the current flowing through the P-type transistor TP1 and the N-type transistor TN1 of the inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the change of the delay time T of the inverter is smaller, thereby improving the inverter's control ability of the delay time accuracy.

[0047] Optionally, the first parameter is the supply voltage or operating temperature of the inverter.

[0048] The first substrate potential increases as the first parameter increases, and decreases as the first parameter decreases; the second substrate potential decreases as the first parameter increases, and increases as the first parameter decreases.

[0049] In a fourth aspect, the present application provides a delay circuit, comprising:

[0050] The inverter according to the third aspect and each possible mode of the third aspect;

[0051] A capacitor, one end of which is connected to the output end of the inverter, and the other end of which is connected to the power supply end or the ground end.

[0052] The delay circuit provided in the present application can compensate for the change in the current flowing through the two transistors of the inverter, so that the change in the delay time T of the inverter is smaller, and thus the change in the delay time T of the delay circuit can be smaller, thereby improving the delay circuit's ability to control the accuracy of the delay time.

[0053] Optionally, the capacitor is a capacitor array.

[0054] In a fifth aspect, the present application provides a logic gate circuit, comprising:

[0055] A P-type transistor and an N-type transistor, wherein the substrate end of the P-type transistor is connected to a first substrate potential, and the substrate end of the N-type transistor is connected to a second substrate potential, and the first substrate potential and the second substrate potential change with a first parameter, so that a delay time from an input end to an output end of the logic gate circuit changes with the first parameter within a first range, and the first parameter includes any one of a power supply voltage, an operating temperature, and a manufacturing process of the logic gate circuit.

[0056] The logic gate circuit provided in the present application can reduce the change in the delay time from the input end to the output end of the logic gate circuit when any one of the power supply voltage, operating temperature and manufacturing process changes, thereby improving the logic gate circuit's ability to control the accuracy of the delay time. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0058] Figure 1 A schematic diagram of an input signal and an output signal after a delay circuit;

[0059] Figure 2 A schematic diagram of an input signal and an output signal after a delay circuit;

[0060] Figure 3 A schematic diagram of an input signal and an output signal after a delay circuit;

[0061] Figure 4 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0062] Figure 5 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0063] Figure 6 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0064] Figure 7 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0065] Figure 8 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0066] Fig. 9 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0067] Fig.10 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0068] Fig.11 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0069] Fig.12A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0070] Fig.13 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0071] Fig.14 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0072] Fig.15 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0073] Fig.16 A schematic diagram of the structure of an inverter provided in an embodiment of the present application;

[0074] Fig.17 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0075] Fig.18 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0076] Fig.19 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0077] Fig. 20 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0078] Fig.21 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0079] Fig. 22 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0080] Fig.23 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0081] Fig.24 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0082] Fig.25 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0083] Fig.26 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0084] Fig. 27 A schematic diagram of a potential generating circuit provided in an embodiment of the present application;

[0085] Fig.28 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0086] Fig.29 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0087] Fig.30 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0088] Fig.31 A schematic diagram of the structure of an inverter provided in an embodiment of the present application;

[0089] Fig.32 A schematic diagram of the structure of an inverter provided in an embodiment of the present application;

[0090] Fig.33 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0091] Fig.34 A schematic diagram of the structure of a delay circuit provided in an embodiment of the present application;

[0092] Fig.35 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0093] Fig.36 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0094] Fig.37 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0095] Fig.38 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0096] Fig.39 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0097] Fig.40 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0098] Fig.41 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0099] Fig.42 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0100] Fig.43 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0101] Fig.44A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0102] Fig.45 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0103] Fig.46 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0104] Fig.47 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0105] Fig.48 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0106] Fig.49 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0107] Fig.50 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0108] Fig.51 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0109] Fig.52 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0110] Fig.53 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0111] Fig.54 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0112] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0113] First, the rising edge delay time and the falling edge delay time involved in this application are explained for easy understanding.

[0114] 1. Rising edge delay time, Figure 1 is a schematic diagram of an input signal and an output signal after a delay circuit, such as Figure 1As shown, the delay time T between the rising edge of the output signal and the rising edge of the input signal is the rising edge delay time.

[0115] 2. Falling edge delay time, such as Figure 1 As shown, the delay time T between the falling edge of the output signal and the falling edge of the input signal is the falling edge delay time.

[0116] The delay circuit provided in the present application can delay both the rising edge and the falling edge of the input signal by a time T, and the width of the pulse signal remains unchanged, such as Figure 1 As shown in , a rising edge delay time T of the input signal can be achieved, and a falling edge delay time T of the input signal can be achieved. Figure 2 is a schematic diagram of an input signal and an output signal after a delay circuit, such as Figure 2 As shown, the rising edge of the input signal is delayed by time T to obtain the output signal, and the width of the pulse signal is shortened by time T. Figure 3 is a schematic diagram of an input signal and an output signal after a delay circuit, such as Figure 3 As shown, the falling edge of the input signal is delayed by time T to obtain the output signal, and the width of the pulse signal is extended by time T. It should be noted that Figure 1-Figure 3 Only one cycle of the pulse signal is shown.

[0117] The delay circuit provided in the present application can be applied to scenarios where the delay time of the delay circuit needs to be precisely controlled, for example, it can be applied to DRAM, and can simultaneously compensate for the impact of changes in any one of the power supply voltage, operating temperature, and manufacturing process on the delay time, so that the delay time T changes less, thereby improving the delay circuit's ability to control the accuracy of the delay time.

[0118] The delay unit in the existing delay circuit includes an inverter, which is composed of two transistors (P-type transistor and N-type transistor). The delay time T of the output signal of the delay circuit will change greatly with the change of power supply voltage, operating temperature and manufacturing process, which will affect the accuracy of the delay time. To solve this problem, the present application starts from the structure of the delay unit. When the power supply voltage, operating temperature and manufacturing process change, the current flowing through the two transistors of the inverter will change, which will cause the delay time to change. Therefore, the present application provides a delay circuit, the delay circuit includes a potential generating circuit and a delay unit, the potential generating circuit includes a first transistor and a second transistor, the potential of the substrate end of the first transistor changes with the change of a first parameter, and the potential of the substrate end of the second transistor changes with the change of a first parameter. The first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit. The delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor, and the substrate end of the fifth transistor is connected to the potential of the substrate end of the second transistor.

[0119] Since the potential of the substrate terminal of the first transistor can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process, the substrate potential that changes with the first parameter can be provided to the substrate terminal of the fourth transistor. The potential of the substrate terminal of the second transistor can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process, so that the substrate potential that changes with the first parameter can be provided to the substrate terminal of the fifth transistor. Therefore, the current flowing through the two transistors of the first inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the delay time T of the delay circuit changes less, thereby improving the delay circuit's ability to control the accuracy of the delay time.

[0120] The specific structures of the potential generating circuit, inverter, delay circuit and logic gate circuit provided by the present application are described in detail below through specific embodiments.

[0121] Embodiment 1

[0122] Figure 4 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the potential generating circuit of this embodiment may include: a first transistor T1 and a second transistor T2, wherein the potential of the substrate end of the first transistor T1 changes with a first parameter, the first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit, and the potential of the substrate end of the second transistor T2 changes with the first parameter.

[0123] Among them, the gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the substrate terminal of the first transistor T1 serves as the first output terminal of the potential generating circuit, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, and the substrate terminal of the second transistor T2 serves as the second output terminal of the potential generating circuit.

[0124] Specifically, the potential of the substrate terminal of the first transistor T1 is the potential output by the first output terminal, and the potential of the substrate terminal of the second transistor T2 is the potential output by the second output terminal. The potential of the substrate terminal of the first transistor T1 changes with the first parameter, and the potential of the substrate terminal of the second transistor T2 changes with the first parameter. Therefore, the potential generating circuit provided in this embodiment can output a potential that changes with any one of the power supply voltage, the operating temperature, and the manufacturing process.

[0125] Specifically, if the first parameter is the power supply voltage or operating temperature of the potential generating circuit, the potential of the substrate terminal of the first transistor T1 changes with the first parameter, and the potential of the substrate terminal of the second transistor T2 changes with the first parameter. Specifically, the potential of the substrate terminal of the first transistor T1 increases as the first parameter increases, and the potential of the substrate terminal of the first transistor T1 decreases as the first parameter decreases, that is, the two are in a proportional relationship; the potential of the substrate terminal of the second transistor T2 decreases as the first parameter increases, and the potential of the substrate terminal of the second transistor T2 increases as the first parameter decreases.

[0126] In an operative manner, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor.

[0127] In an operative manner, a source terminal of the first transistor T1 is connected to a first voltage node, a source terminal of the second transistor T2 is connected to a second voltage node, and a drain terminal of the first transistor T1 is connected to a drain terminal of the second transistor T2.

[0128] In this embodiment, Figure 5 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the potential generating circuit of this embodiment is Figure 4 On the basis of the circuit shown, it may further include: a constant current source 11, a first end of the constant current source 11 is connected to the second voltage node, and a second end of the constant current source 11 is connected to the third voltage node.

[0129] Figure 6 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the potential generating circuit of this embodiment is Figure 5On the basis of the circuit shown, it can further include: a first error amplifier 12, a second error amplifier 13 and a third transistor T3, wherein:

[0130] The first error amplifier 12 and the second transistor T2 form a first feedback loop, and the substrate terminal of the second transistor T2 is connected to a voltage node of the first feedback loop.

[0131] The second error amplifier 13 and the third transistor T3 form a second feedback loop, and the substrate terminal of the first transistor is connected to a voltage node of the second feedback loop.

[0132] like Figure 6 As shown, optionally, the negative input terminal of the first error amplifier 12 is connected to the second voltage node, the positive input terminal of the first error amplifier 12 is connected to the first reference voltage V1, and the output terminal of the first error amplifier 12 is connected to the substrate terminal of the second transistor T2.

[0133] The negative input terminal of the second error amplifier 13 is connected to the second reference voltage V2, the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node, the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3, the source terminal of the third transistor T3 is connected to the first voltage node, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the first resistor R1, and the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the second resistor R2.

[0134] In this embodiment, the first voltage node may be connected to a power supply terminal, the first reference voltage V1 may be connected to a ground terminal, and the potential of the third voltage node is lower than the potential of the first reference voltage V1.

[0135] Figure 6 In the potential generating circuit shown, the first voltage node is connected to the power supply terminal, the first reference voltage V1 is connected to the ground terminal, and the potential of the third voltage node is less than the potential of V1, that is, the potential of the third voltage node is less than 0. The potential of the first voltage node is greater than the potential of the third voltage node.

[0136] Combine the following Figure 7 and Figure 8 Another potential generating circuit is shown below. Figure 7 and Figure 8 Provide detailed explanation.

[0137] Figure 7 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the potential generating circuit of this embodiment is Figure 4On the basis of the circuit shown, it may further include: a constant current source 11, a first end of the constant current source 11 is connected to the third voltage node, and a second end of the constant current source 11 is connected to the first voltage node.

[0138] Figure 8 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the potential generating circuit of this embodiment is Figure 7 On the basis of the circuit shown, it can further include: a first error amplifier 12, which forms a first feedback loop with the first transistor T1, and the substrate end of the first transistor T1 is connected to a voltage node of the first feedback loop.

[0139] The second error amplifier 13 and the third transistor T3 form a second feedback loop, and the substrate terminal of the second transistor T2 is connected to a voltage node of the second feedback loop.

[0140] like Figure 8 As shown, optionally, the negative input terminal of the first error amplifier 12 is connected to the first voltage node, the positive input terminal of the first error amplifier is connected to the first reference voltage V1, and the output terminal of the first error amplifier 12 is connected to the substrate terminal of the first transistor T1.

[0141] The negative input terminal of the second error amplifier 13 is connected to the second reference voltage V2, the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node, the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3, the source terminal of the third transistor T3 is connected to the second voltage node, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the second resistor R2, and the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the first resistor R1.

[0142] In this embodiment, the second voltage node may be connected to the ground terminal, the first reference voltage V1 may be connected to the power terminal, and the potential of the third voltage node is greater than the potential of the first reference voltage V1.

[0143] Figure 8 In the potential generating circuit shown, the second voltage node is connected to the ground terminal, the first reference voltage V1 is connected to the power terminal, the potential of the third voltage node is greater than the potential of V1, that is, the potential of the third voltage node is greater than the potential of the power terminal. The potential of the first voltage node is less than the potential of the third voltage node.

[0144] Figures 4 to 8Any of the potential generating circuits shown is configured by setting a first transistor and a second transistor, wherein the gate terminal of the first transistor is connected to the drain terminal of the first transistor, the substrate terminal of the first transistor serves as the first output terminal of the potential generating circuit, the gate terminal of the second transistor is connected to the drain terminal of the second transistor, and the substrate terminal of the second transistor serves as the second output terminal of the potential generating circuit. Since the potential of the substrate terminal of the first transistor changes with the first parameter, the potential of the substrate terminal of the second transistor changes with the first parameter. Thus, the first output terminal and the second output terminal can respectively output potentials that change with any one of the power supply voltage, the operating temperature and the manufacturing process.

[0145] Further, in Figures 4 to 8 Based on any of the potential generating circuits shown, it can also include: a first buffer 14 and a second buffer 15, Fig. 9 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig.10 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig. 9 The potential generating circuit shown in Figure 6 Based on the circuit shown, it can also include: a first buffer 14 and a second buffer 15, Fig.10 The potential generating circuit shown in Figure 8 On the basis of the circuit shown, it can also include: a first buffer 14 and a second buffer 15.

[0146] See also Fig. 9 and Fig.10 The first buffer 14 is connected to the first output terminal and outputs a first substrate potential, the value of which is equal to the potential value of the substrate terminal of the first transistor T1. The input potential and output potential of the first buffer 14 are the same. The first buffer 14 is used to enhance the driving capability of the potential of the substrate terminal of the first transistor T1, and can also isolate the substrate terminal of the first transistor T1 to prevent the potential of the substrate terminal of the first transistor T1 from being disturbed.

[0147] The second buffer 15 is connected to the second output terminal and outputs a second substrate potential, the value of which is equal to the potential value of the substrate terminal of the second transistor T2. The input potential and output potential of the second buffer 15 are the same. The second buffer 15 is used to enhance the driving capability of the potential of the substrate terminal of the second transistor T2, and can also isolate the substrate terminal of the second transistor T2 to prevent the potential of the substrate terminal of the second transistor T2 from being disturbed.

[0148] The structure of the potential generating circuit of the present application is described below in conjunction with specific embodiments. The specific structure of the potential generating circuit of the present application is not limited to any of the following structures.

[0149] Fig.11A structural schematic diagram of a potential generating circuit provided in an embodiment of the present application, the potential generating circuit of this embodiment may include: a first transistor T1, a second transistor T2, a constant current source 11, a first error amplifier 12, a second error amplifier 13, a first resistor R1, a second resistor R2, a third transistor T3, a first buffer 14 and a second buffer 15.

[0150] In this embodiment, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, the source terminal of the first transistor T1 is connected to the power supply terminal Vcc, the source terminal of the second transistor T2 is connected to the first terminal of the constant current source 11, and the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2. The second terminal of the constant current source 11 is connected to Vkb, and the potential of Vkb is less than 0.

[0151] Among them, the first error amplifier 12 and the second transistor T2 form a first feedback loop, the negative input terminal of the first error amplifier 12 is connected to the source terminal of the second transistor T2 and the first terminal of the constant current source 11, the positive input terminal of the first error amplifier 12 is connected to the ground terminal, and the output terminal of the first error amplifier 12 is connected to the substrate terminal of the second transistor T2.

[0152] Among them, the negative input terminal of the second error amplifier 13 is connected to the power supply terminal (for example, it can be Vcc / 2), the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node, the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3, the source terminal of the third transistor T3 is connected to the power supply terminal Vcc, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the first resistor R1, and the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the second resistor R2.

[0153] The first buffer 14 is connected to the substrate terminal of the first transistor and outputs a first substrate potential, the value of which is equal to the potential value of the substrate terminal of the first transistor T1. The second buffer 15 is connected to the substrate terminal of the second transistor and outputs a second substrate potential, the value of which is equal to the potential value of the substrate terminal of the second transistor T2.

[0154] Optionally, the resistance values ​​of the first resistor R1 and the second resistor R2 can be set larger, for example, set to 100 MΩ. By setting the resistance values ​​of the first resistor R1 and the second resistor R2 larger, the output of the first error amplifier 12 will only slowly affect the input of the second error amplifier 13, and have little effect on the first substrate potential.

[0155] In this embodiment, the potential of the substrate end of the first transistor T1 increases as the first parameter increases, and the potential of the substrate end of the first transistor T1 decreases as the first parameter decreases; the potential of the substrate end of the second transistor T2 decreases as the first parameter increases, and the potential of the substrate end of the second transistor T2 increases as the first parameter decreases, and the first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit.

[0156] Taking the first parameter as the operating temperature as an example, the following describes in detail the principle that the potential of the substrate end of the first transistor T1 changes with the first parameter, and the principle that the potential of the substrate end of the second transistor T2 changes with the first parameter.

[0157] The current flowing through the first transistor T1 Id = μ*Cox*(W / L)*(Vgs-Vth) 2 , where μ is the electron mobility, Cox is the gate capacitance, Vgs is the voltage difference between the gate and the source, and Vth is the threshold voltage. For example, when the operating temperature increases, the electron mobility μ decreases, which will cause the current Id flowing through the first transistor T1 to decrease, and the corresponding delay time of the inverter to increase. At this time, if Vgs-Vth is adjusted to increase, the current change caused by the decrease in electron mobility μ can be compensated. The specific adjustment value can be set according to actual needs. Fig.11 In the potential generating circuit shown, if the temperature rises, the electron mobility μ decreases, and the current Id flowing through the first transistor T1 decreases. In order to keep the current of the constant current source unchanged, the first substrate potential needs to be increased, for example, to Vcc+100mV, and the second substrate potential needs to be reduced, for example, to -100mV. When the temperature rises, the current Id flowing through the first transistor T1 and the second transistor T2 decreases. For the constant current source 11, the current provided from the top decreases, while the current flowing to the bottom remains unchanged, so that the potential of the negative input terminal of the first error amplifier 12 decreases, and then the second substrate potential decreases. At this time, the output of the first error amplifier 12 gradually becomes -100mV, and then the positive input terminal of the second error amplifier 13 decreases, resulting in a decrease in the output voltage of the second error amplifier 13, and then the pull-up capability of the third transistor T3 is enhanced, so that the voltage of the first substrate potential becomes higher, and the first substrate potential gradually becomes Vcc+100mV.

[0158] When the first parameter is the power supply voltage and the manufacturing process, changes in the power supply voltage and the manufacturing process will cause changes in the current Id flowing through the first transistor T1, thereby causing changes in the delay time. The compensation principle is similar to the above principle and will not be repeated here.

[0159] Fig.12A structural schematic diagram of a potential generating circuit provided in an embodiment of the present application, the potential generating circuit of this embodiment may include: a first transistor T1, a second transistor T2, a constant current source 11, a first error amplifier 12, a second error amplifier 13, a first resistor R1, a second resistor R2, a third transistor T3, a first buffer 14 and a second buffer 15.

[0160] In this embodiment, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, the source terminal of the first transistor T1 is connected to the first terminal of the constant current source 11, the source terminal of the second transistor T2 is connected to the ground terminal, and the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2. The second terminal of the constant current source 11 is connected to the power supply terminal Vdd.

[0161] Among them, the first error amplifier 12 and the first transistor T1 form a first feedback loop, the negative input terminal of the first error amplifier 12 is connected to the first end of the constant current source 11, the positive input terminal of the first error amplifier is connected to the power supply terminal Vcc, and the output terminal of the first error amplifier 12 is connected to the substrate terminal of the first transistor T1.

[0162] Among them, Vdd is greater than Vcc.

[0163] Among them, the negative input terminal of the second error amplifier 13 is connected to the power supply terminal (for example, it can be Vcc / 2), the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node, the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3, the source terminal of the third transistor T3 is connected to the ground terminal, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the second resistor R2, and the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the first resistor R1.

[0164] The first buffer 14 is connected to the substrate terminal of the first transistor and outputs a first substrate potential, the value of which is equal to the potential value of the substrate terminal of the first transistor T1. The second buffer 15 is connected to the substrate terminal of the second transistor and outputs a second substrate potential, the value of which is equal to the potential value of the substrate terminal of the second transistor T2.

[0165] In this embodiment, the potential of the substrate end of the first transistor T1 increases as the first parameter increases, and the potential of the substrate end of the first transistor T1 decreases as the first parameter decreases; the potential of the substrate end of the second transistor T2 decreases as the first parameter increases, and the potential of the substrate end of the second transistor T2 increases as the first parameter decreases, and the first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit.

[0166] Taking the first parameter as the operating temperature as an example, the following describes in detail the principle that the potential of the substrate end of the first transistor T1 changes with the first parameter, and the principle that the potential of the substrate end of the second transistor T2 changes with the first parameter.

[0167] The current flowing through the first transistor T1 Id = μ*Cox*(W / L)*(Vgs-Vth) 2 , where μ is the electron mobility and Vth is the threshold voltage. For example, when the operating temperature increases, the electron mobility μ decreases, which will cause the current Id flowing through the first transistor T1 to decrease, and the corresponding delay time of the inverter to increase. At this time, if Vgs-Vth is adjusted to increase, the current change caused by the decrease in electron mobility μ can be compensated. The specific adjustment value can be set according to actual needs. Fig.12 In the potential generating circuit shown, if the temperature rises, the electron mobility μ decreases, and the current Id flowing through the first transistor T1 decreases. In order to keep the current of the constant current source unchanged, the second substrate potential needs to be reduced, for example, to -100mV, and the first substrate potential needs to be increased, for example, to Vcc+100mV. If the temperature rises, the current provided by the top of the constant current source remains unchanged, and the current flowing downward from the constant current source is equal to the current Id flowing through the first transistor T1 and the second transistor T2, and Id decreases, so the potential of the negative input terminal of the first error amplifier 12 increases, and the first substrate potential increases, which will cause the output of the first error amplifier 12 to gradually become Vcc+100mV, and then the positive input terminal of the second error amplifier 13 increases, causing the output voltage of the second error amplifier 13 to increase, and then the pull-down capability of the third transistor T3 is enhanced, so that the voltage of the second substrate potential decreases.

[0168] When the first parameter is the power supply voltage and the manufacturing process, changes in the power supply voltage and the manufacturing process will cause changes in the current Id flowing through the first transistor T1, thereby causing changes in the delay time. The compensation principle is similar to the above principle and will not be repeated here.

[0169] The present application also provides a delay circuit, comprising: Figures 4 to 12 Any of the potential generating circuits and delay units shown, the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor T1, and the substrate end of the fifth transistor is connected to the potential of the substrate end of the second transistor T2.

[0170] The delay circuit provided in this embodiment has a potential at the substrate end of the first transistor in the potential generating circuit that can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process, thereby providing a first substrate potential that changes with the change of the first parameter for the substrate end of the fourth transistor, and a potential at the substrate end of the second transistor that can change with the change of the power supply voltage, the operating temperature and the manufacturing process, thereby providing a second substrate potential that changes with the change of the first parameter for the substrate end of the fifth transistor. Therefore, the current flowing through the two transistors of the first inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the delay time T of the delay circuit changes less, thereby improving the control ability of the delay circuit on the accuracy of the delay time.

[0171] When the first transistor is a P-type transistor, the second transistor is an N-type transistor, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor, by providing a first substrate potential that changes with a first parameter to the substrate end of the P-type transistor, the change value of the rising edge delay time of the delay circuit can be adjusted, so that the change in the rising edge delay time of the delay circuit is smaller. By providing a second substrate potential that changes with the first parameter to the substrate end of the N-type transistor, the change value of the falling edge delay time of the delay circuit can be adjusted, so that the change in the falling edge delay time of the delay circuit is smaller.

[0172] It should be noted that, in the embodiment of the present application, the connection relationship between the potential generating circuit and the inverter can be set according to the number of inverters included in the delay circuit and the demand for delay time compensation. For example, two inverters are connected in series, and the substrate end of the P-type transistor in the inverter is connected to the substrate end of the P-type transistor in the potential generating circuit, and the change value of the rising edge delay time of the delay circuit can be adjusted. The substrate end of the N-type transistor in the inverter is connected to the substrate end of the N-type transistor in the potential generating circuit, and the change value of the falling edge delay time of the delay circuit can be adjusted. Specifically, the connection relationship between the potential generating circuit and the inverter can be set according to the change value of the rising edge and / or falling edge delay time to be adjusted. The potential generating circuit provided in the embodiment of the present application can be applied to a delay circuit in which both the rising edge and / or the falling edge are delayed, and can reduce the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the delay time T of the delay circuit, so that the change of the delay time T (including the rising edge and / or the falling edge) is small, and the control ability of the delay circuit on the delay time accuracy is improved.

[0173] Combine the following Figures 13 to 15 Give three examples of delay circuits, Fig.13 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.13 As shown, the delay circuit of this embodiment includes a potential generating circuit 1 and a delay unit 2. The potential generating circuit 1 is Fig.11The circuit shown in the figure can be found in the detailed structure description. Fig.11 The description in the illustrated embodiment is not repeated here. The potential generating circuit 1 outputs a first substrate potential BP and a second substrate potential BN. The delay unit 2 includes an inverter and a capacitor C1. The inverter includes a P-type transistor TP1 and an N-type transistor TN1. The substrate end of the P-type transistor TP1 is connected to the first substrate potential BP, and the substrate end of the N-type transistor TN1 is connected to the second substrate potential BN. In the delay circuit of this embodiment, the potential generating circuit 1 provides a first substrate potential that varies with a first parameter for the substrate end of the P-type transistor in the delay unit 2. When the input end of the delay unit 2 is a falling edge, the first substrate potential BP can adjust the change value of the rising edge delay time of the delay circuit, so that the change of the rising edge delay time of the delay circuit is small. The potential generating circuit 1 provides a second substrate potential that varies with a first parameter for the substrate end of the N-type transistor in the delay unit 2. When the input end of the delay unit 2 is a rising edge, the second substrate potential BN can adjust the change value of the falling edge delay time of the delay circuit, so that the change of the falling edge delay time of the delay circuit is small. Therefore, the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the delay time T of the delay circuit can be reduced, so that the change of the delay time T (including the rising edge and the falling edge) is small, and the control ability of the delay circuit on the delay time accuracy is improved.

[0174] Fig.14 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.14 As shown, the delay circuit of this embodiment includes a potential generating circuit 1 and a delay unit 2. The potential generating circuit 1 is Fig.11 The circuit shown in the figure can be found in the detailed structure description. Fig.11 The description in the illustrated embodiment is not repeated here. The potential generating circuit 1 outputs a first substrate potential BP and a second substrate potential BN. The delay unit 2 includes a first inverter, a second inverter and a capacitor C1. The first inverter includes a P-type transistor TP1 and an N-type transistor TN1. The second inverter includes a P-type transistor TP2 and an N-type transistor TN2. Among them, the substrate end of the N-type transistor TN1 in the delay unit 2 is connected to the second substrate potential BN, and the substrate end of the N-type transistor TN2 is connected to the second substrate potential BN. In the delay circuit of this embodiment, the potential generating circuit 1 provides the substrate ends of the N-type transistor TN1 and the N-type transistor TN2 in the delay unit 2 with the second substrate potential BN that changes with the first parameter. When the input end of the delay unit 2 is a rising edge, the change value of the falling edge delay time of the delay circuit can be adjusted, so that the change of the rising edge delay time of the delay circuit is small, thereby reducing the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the rising edge delay time T of the delay circuit, so that the change of the rising edge delay time T is small, and the control ability of the delay circuit on the delay time accuracy is improved.

[0175] It can be understood that in another delay circuit, the substrate end of the P-type transistor TP1 in the delay unit 2 can be connected to the first substrate potential BP, and the substrate end of the P-type transistor TP2 can be connected to the first substrate potential BP, so that the change value of the falling edge delay time of the delay circuit can be adjusted, so that the change of the falling edge delay time of the delay circuit is smaller.

[0176] Fig.15 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.15 As shown, the delay circuit and Fig.13 The difference between the delay circuit shown in the figure is that the potential generating circuit 1 in this embodiment is Fig.12 The circuit shown has the same other structures and the same effects, which will not be described here.

[0177] The present application also provides a delay circuit, comprising: Figures 9 to 12 In any of the potential generating circuits and delay units shown, the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the first substrate potential, and the substrate end of the fifth transistor is connected to the second substrate potential.

[0178] The delay circuit provided in this embodiment has a first substrate potential in the potential generating circuit that can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process, thereby providing a first substrate potential that changes with the change of the first parameter to the substrate end of the fourth transistor, and a second substrate potential that can change with the change of the power supply voltage, the operating temperature and the manufacturing process, thereby providing a second substrate potential that changes with the change of the first parameter to the substrate end of the fifth transistor. Therefore, the current flowing through the two transistors of the first inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the delay time T of the delay circuit changes less, thereby improving the delay circuit's ability to control the accuracy of the delay time.

[0179] In the above two delay circuits, the ratio of the channel length of the first transistor T1 to the channel length of the fourth transistor is H, the ratio of the channel length of the second transistor T2 to the channel length of the fifth transistor is L, the ratio of the channel width of the first transistor T1 to the channel width of the fourth transistor is M, the ratio of the channel width of the second transistor T2 to the channel width of the fifth transistor is N, H is equal to L, M is equal to N, and optionally, H, L, M and N can be 1. Optionally, the first transistor and the fourth transistor can be of the same type, and the second transistor and the fifth transistor can be of the same type.

[0180] The embodiment of the present application also provides an inverter, Fig.16A schematic diagram of the structure of an inverter provided in an embodiment of the present application is shown in FIG. Fig.16 As shown, the inverter comprises:

[0181] P-type transistor TP1 and N-type transistor TN1, the source terminal of the P-type transistor TP1 is connected to the power supply terminal, the drain terminal of the P-type transistor TP1 is connected to the drain terminal of the N-type transistor TN1, the source terminal of the N-type transistor TN1 is connected to the ground terminal, the gate terminal of the P-type transistor TP1 is connected to the gate terminal of the N-type transistor TN1 and serves as the input terminal of the inverter, and the drain terminal of the P-type transistor serves as the output terminal of the inverter.

[0182] The substrate end of the P-type transistor TP1 is connected to a first substrate potential, and the substrate end of the N-type transistor TN1 is connected to a second substrate potential. The first substrate potential changes with a first parameter, and the second substrate potential changes with the first parameter. The first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the inverter.

[0183] Among them, when the first parameter is the power supply voltage or operating temperature of the inverter, the first substrate potential increases as the first parameter increases, and the first substrate potential decreases as the first parameter decreases; the second substrate potential decreases as the first parameter increases, and the second substrate potential increases as the first parameter decreases.

[0184] The inverter provided in this embodiment has a first substrate potential that can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process, so that the first substrate potential that changes with the change of the first parameter can be provided to the substrate end of TP1, and the second substrate potential can change with the change of the power supply voltage, the operating temperature and the manufacturing process, so that the second substrate potential that changes with the change of the first parameter can be provided to the substrate end of TN1. Therefore, the current flowing through the P-type transistor TP1 and the N-type transistor TN1 of the inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the change of the delay time T of the inverter is small, thereby improving the inverter's control ability of the delay time accuracy.

[0185] The embodiment of the present application also provides a delay circuit, Fig.17 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.17 As shown, the delay circuit of this embodiment may include Fig.16 The inverter and the capacitor C1 are shown, and one end of the capacitor C1 is connected to the ground. In an operative manner, the capacitor C1 may be a capacitor array.

[0186] The delay circuit provided in this embodiment can compensate for the change in the current flowing through the two transistors of the inverter, so that the change in the delay time T of the inverter is small, and thus the change in the delay time T of the delay circuit can be small, thereby improving the delay circuit's ability to control the accuracy of the delay time.

[0187] An embodiment of the present application also provides a logic gate circuit, including: a P-type transistor and an N-type transistor, wherein the substrate end of the P-type transistor is connected to a first substrate potential, and the substrate end of the N-type transistor is connected to a second substrate potential, and the first substrate potential and the second substrate potential change with a first parameter, so that a delay time from an input end to an output end of the logic gate circuit changes with the first parameter and the change value thereof is within a first range, and the first parameter includes any one of a power supply voltage, an operating temperature, and a manufacturing process of the logic gate circuit.

[0188] Specifically, the first range is a smaller range, for example, a range close to 0. If the first range is 1% or 3% or 5%, the delay time from the input to the output of the logic gate circuit can change less when any one of the power supply voltage, operating temperature and manufacturing process changes, thereby improving the logic gate circuit's ability to control the accuracy of the delay time.

[0189] Embodiment 2

[0190] Fig.18 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig.18 As shown, the potential generating circuit of this embodiment may include: a first transistor T1 and a second transistor T2, wherein the potential of the substrate end of the first transistor T1 changes with a first parameter, and the first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit.

[0191] The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1 , the substrate terminal of the first transistor T1 serves as the output terminal of the potential generating circuit, and the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2 .

[0192] Specifically, the potential of the substrate end of the first transistor T1 is the potential output by the output end, and the potential of the substrate end of the first transistor T1 changes with the first parameter. Therefore, the potential generating circuit provided in this embodiment can output a potential that changes with any one of the power supply voltage, operating temperature and manufacturing process.

[0193] Specifically, if the first parameter is the power supply voltage or operating temperature of the potential generating circuit, the potential of the substrate end of the first transistor T1 changes with the first parameter. Specifically, the potential of the substrate end of the first transistor T1 increases with the increase of the first parameter, and the potential of the substrate end of the first transistor T1 decreases with the decrease of the first parameter, that is, the two are in direct proportional relationship.

[0194] In an operative manner, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor.

[0195] In one practicable manner, the source terminal of the first transistor T1 is connected to the first voltage node, the source terminal of the second transistor T2 is connected to the second voltage node, the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2, and the substrate terminal of the second transistor T2 is connected to the second voltage node.

[0196] In this embodiment, Fig.19 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig.19 As shown, the potential generating circuit of this embodiment is Fig.18 On the basis of the circuit shown, further, it can also include: a constant current source 21, a first end of the constant current source 21 is connected to the first voltage node, and a second end of the constant current source 21 is connected to the third voltage node.

[0197] Fig. 20 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig. 20 As shown, the potential generating circuit of this embodiment is Fig.19 On the basis of the circuit shown, it can further include: an error amplifier 22, which forms a feedback loop with the first transistor T1, and the substrate end of the first transistor T1 is connected to a voltage node of the first feedback loop.

[0198] like Fig. 20 As shown, optionally, the negative input terminal of the error amplifier 22 is connected to the first voltage node, the positive input terminal of the error amplifier 22 is connected to the first reference voltage V1, and the output terminal of the error amplifier 22 is connected to the substrate terminal of the first transistor T1.

[0199] In this embodiment, the first reference voltage V1 may be connected to a power supply terminal, and the potential of the third voltage node is greater than the potential of the first reference voltage V1.

[0200] Fig. 20 In the potential generating circuit shown, the potential of the third voltage node is greater than the potential of the first reference voltage V1, and the potential of the first voltage node is less than the potential of the third voltage node. For example, the voltage of the third voltage node can be Vdd, the first reference voltage V1 can be equal to Vcc, and Vdd is greater than Vcc.

[0201] Figures 18 to 20 Any of the potential generating circuits shown is configured by setting a first transistor and a second transistor, wherein the gate terminal of the first transistor is connected to the drain terminal of the first transistor, the substrate terminal of the first transistor serves as the output terminal of the potential generating circuit, and the gate terminal of the second transistor is connected to the drain terminal of the second transistor. Since the potential of the substrate terminal of the first transistor changes with the first parameter, the output terminal can output a potential that changes with any one of the power supply voltage, the operating temperature and the manufacturing process.

[0202] Fig.21 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig.21 As shown, in Fig. 20 On the basis of the potential generating circuit shown, further, it can also include: a buffer 23, the buffer 23 is connected to the output end, and outputs a substrate potential, the value of the substrate potential is equal to the potential value of the substrate end of the first transistor T1. The input potential and the output potential of the buffer 23 are the same, and the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to prevent the potential of the substrate end of the first transistor T1 from being disturbed.

[0203] Combine the following Figure 22 to Figure 25 Another potential generating circuit is shown, Fig. 22 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig. 22 As shown, the potential generating circuit of this embodiment may include: a first transistor T1 and a second transistor T2, wherein the potential of the substrate end of the second transistor T2 changes with a first parameter, and the first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit.

[0204] The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, and the substrate terminal of the second transistor serves as the output terminal of the potential generating circuit.

[0205] Specifically, the potential of the substrate end of the second transistor T2 is the potential output by the output end, and the potential of the substrate end of the second transistor T2 changes with the first parameter. Therefore, the potential generating circuit provided in this embodiment can output a potential that changes with any one of the power supply voltage, operating temperature and manufacturing process.

[0206] Specifically, if the first parameter is the power supply voltage or operating temperature of the potential generating circuit, the potential of the substrate end of the second transistor T2 changes with the first parameter. Specifically, the potential of the substrate end of the second transistor T2 decreases as the first parameter increases, and the potential of the substrate end of the second transistor T2 increases as the first parameter decreases.

[0207] In an operative manner, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor.

[0208] In one practicable manner, the source terminal of the first transistor T1 is connected to the first voltage node, the source terminal of the second transistor T2 is connected to the second voltage node, the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2, and the substrate terminal of the first transistor T1 is connected to the first voltage node.

[0209] In this embodiment, Fig.23 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig.23 As shown, the potential generating circuit of this embodiment is Fig. 22 On the basis of the circuit shown, further, it may also include: a constant current source 21, a first end of the constant current source 21 is connected to the third voltage node, and a second end of the constant current source 21 is connected to the second voltage node.

[0210] Fig.24 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig.24 As shown, the potential generating circuit of this embodiment is Fig.23 On the basis of the circuit shown, it can further include: an error amplifier 22, which forms a feedback loop with the second transistor T2, and the substrate end of the second transistor T2 is connected to a voltage node of the first feedback loop.

[0211] like Fig.24 As shown, optionally, the negative input terminal of the error amplifier 22 is connected to the second voltage node, the positive input terminal of the error amplifier 22 is connected to the first reference voltage V1, and the output terminal of the error amplifier 22 is connected to the substrate terminal of the second transistor T2.

[0212] In this embodiment, the first voltage node may be connected to the power supply terminal Vcc, the first reference voltage V1 may be connected to the ground terminal Vss, and the potential of the third voltage node is lower than the potential of the first reference voltage V1.

[0213] Fig.24 In the potential generating circuit shown, the first voltage node is connected to the power supply terminal Vcc, the first reference voltage V1 is connected to the ground terminal Vss, the potential of the third voltage node is less than the potential of V1, for example, the potential of the third voltage node is less than 0, and the potential of the second voltage node is greater than the potential of the third voltage node.

[0214] Figure 22 to Figure 24Any of the potential generating circuits shown is configured by setting a first transistor and a second transistor, wherein the gate terminal of the first transistor is connected to the drain terminal of the first transistor, the gate terminal of the second transistor is connected to the drain terminal of the second transistor, the potential of the substrate terminal of the second transistor T2 changes with the first parameter, and the substrate terminal of the second transistor serves as the output terminal of the potential generating circuit. Since the potential of the substrate terminal of the second transistor changes with the first parameter, the output terminal can output a potential that changes with any one of the power supply voltage, the operating temperature and the manufacturing process.

[0215] Fig.25 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig.25 As shown, in Fig.24 On the basis of the potential generating circuit shown, further, it can also include: a buffer 23, the buffer 23 is connected to the output end, and outputs a substrate potential, and the value of the substrate potential is equal to the potential value of the substrate end of the second transistor T2. The input potential and the output potential of the buffer 23 are the same. The buffer 23 is used to enhance the driving capability of the potential of the substrate end of the second transistor T2, and can also isolate the substrate end of the second transistor T2 to prevent the potential of the substrate end of the second transistor T2 from being disturbed.

[0216] The structure of the potential generating circuit of the present application is described below in conjunction with specific embodiments. The specific structure of the potential generating circuit of the present application is not limited to any of the following structures.

[0217] Fig.26 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig.26 As shown, the potential generating circuit of this embodiment may include: a first transistor T1 , a second transistor T2 , a constant current source 21 , an error amplifier 22 and a buffer 23 .

[0218] In this embodiment, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, the source terminal of the first transistor T1 is connected to the power supply terminal Vcc, the source terminal of the second transistor T2 is connected to the first terminal of the constant current source 21, and the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2. The second terminal of the constant current source 21 is connected to Vkb, and the potential of Vkb is less than 0.

[0219] Among them, the error amplifier 22 and the second transistor T2 form a first feedback loop, the negative input terminal of the error amplifier 22 is connected to the source terminal of the second transistor T2 and the first terminal of the constant current source 21, the positive input terminal of the error amplifier 22 is connected to the ground terminal, and the output terminal of the error amplifier 22 is connected to the substrate terminal of the second transistor T2.

[0220] The buffer 23 is connected to the substrate terminal of the second transistor T2 and outputs a substrate potential, the value of which is equal to the potential value of the substrate terminal of the second transistor T2.

[0221] In this embodiment, the potential of the substrate end of the second transistor T2 changes with the first parameter. Specifically, the potential of the substrate end of the second transistor T2 decreases as the first parameter increases, and the potential of the substrate end of the second transistor T2 increases as the first parameter decreases. The first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit.

[0222] Taking the first parameter as the operating temperature as an example, the principle that the potential of the substrate terminal of the second transistor T2 changes with the change of the first parameter is described in detail below.

[0223] The current flowing through the second transistor T2 Id = μ*Cox*(W / L)*(Vgs-Vth) 2 , where μ is the electron mobility and Vth is the threshold voltage. For example, when the operating temperature increases, the electron mobility μ decreases, which will cause the current Id flowing through the second transistor T2 to decrease, and the corresponding delay time of the inverter to increase. At this time, if Vgs-Vth is adjusted to increase, the current change caused by the decrease in electron mobility μ can be compensated. The specific adjustment value can be set according to actual needs. Fig.26 In the potential generating circuit shown, if the temperature rises, the electron mobility μ decreases, and the current Id flowing through the second transistor T2 decreases. In order to keep the current of the constant current source unchanged, the substrate potential of the second transistor T2 needs to be reduced. At this time, the substrate potential decreases as the temperature increases.

[0224] When the first parameter is the power supply voltage and the manufacturing process, changes in the power supply voltage and the manufacturing process will cause the current Id flowing through the second transistor T2 to change, thereby causing the delay time to change. The compensation principle is similar to the above principle and will not be repeated here.

[0225] Fig. 27 A schematic diagram of a potential generating circuit provided in an embodiment of the present application is shown in FIG. Fig. 27 As shown, the potential generating circuit of this embodiment may include: a first transistor T1 , a second transistor T2 , a constant current source 21 , an error amplifier 22 and a buffer 23 .

[0226] In this embodiment, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, the source terminal of the first transistor T1 is connected to the first terminal of the constant current source 21, the source terminal of the second transistor T2 is connected to the ground terminal, and the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2. The second terminal of the constant current source 21 is connected to Vdd.

[0227] Among them, the error amplifier 22 and the first transistor T1 form a first feedback loop, the negative input terminal of the error amplifier 22 is connected to the source terminal of the first transistor T1 and the first terminal of the constant current source 21, the positive input terminal of the error amplifier 22 is connected to the power supply terminal Vcc, and the output terminal of the error amplifier 22 is connected to the substrate terminal of the first transistor T1.

[0228] Among them, Vdd is greater than Vcc.

[0229] The buffer 23 is connected to the substrate terminal of the first transistor T1 and outputs a substrate potential, the value of which is equal to the potential value of the substrate terminal of the first transistor T1.

[0230] In this embodiment, the potential of the substrate end of the first transistor T1 changes with the first parameter. Specifically, the potential of the substrate end of the first transistor T1 increases as the first parameter increases, and the potential of the substrate end of the first transistor T1 decreases as the first parameter decreases. The first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit.

[0231] Taking the first parameter as the operating temperature as an example, the principle that the potential of the substrate terminal of the first transistor T1 changes with the change of the first parameter is described in detail below.

[0232] The current flowing through the first transistor T1 Id = μ*Cox*(W / L)*(Vgs-Vth) 2 , where μ is the electron mobility and Vth is the threshold voltage. For example, when the operating temperature increases, the electron mobility μ decreases, which will cause the current Id flowing through the first transistor T1 to decrease, and the corresponding delay time of the inverter to increase. At this time, if Vgs-Vth is adjusted to increase, the current change caused by the decrease in electron mobility μ can be compensated. The specific adjustment value can be set according to actual needs. Fig.26 In the potential generating circuit shown, if the temperature rises, the electron mobility μ decreases, and the current Id flowing through the first transistor T1 decreases. In order to keep the current of the constant current source unchanged, the substrate potential of the first transistor T1 needs to be reduced. At this time, the substrate potential decreases as the temperature increases.

[0233] When the first parameter is the power supply voltage and the manufacturing process, changes in the power supply voltage and the manufacturing process will cause the current Id flowing through the second transistor T2 to change, thereby causing the delay time to change. The compensation principle is similar to the above principle and will not be repeated here.

[0234] The present application also provides a delay circuit, comprising: Fig.18 or Fig.19 or Fig. 20 Fig.21 or Fig. 27 The potential generating circuit and delay unit shown, the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor, the substrate end of the fifth transistor is connected to the ground end, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0235] Wherein, optionally, the ratio of the channel length of the first transistor to the channel length of the fourth transistor is recorded as H, the ratio of the channel length of the second transistor to the channel length of the fifth transistor is recorded as L, the ratio of the channel width of the first transistor to the channel width of the fourth transistor is recorded as M, the ratio of the channel width of the second transistor to the channel width of the fifth transistor is recorded as N, H is equal to L, and M is equal to N. Optionally, H, L, M and N can be 1. Optionally, the first transistor and the fourth transistor can be of the same type, and the second transistor and the fifth transistor can be of the same type.

[0236] The delay circuit provided in this embodiment can provide a substrate potential that changes with the first parameter for the substrate end of the P-type transistor in the inverter, because the potential of the substrate end of the first transistor in the potential generating circuit can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process. Therefore, the current flowing through the P-type transistor in the inverter can be adjusted, and the change value of the current flowing through the P-type transistor in the inverter can be compensated, so that the rising edge delay time T of the delay circuit changes less, thereby improving the delay circuit's ability to control the accuracy of the rising edge delay time.

[0237] The delay circuit provided in this embodiment can be applied to scenarios where the rising edge delay time of the delay circuit needs to be accurately controlled, for example, it can be applied to DRAM, and can simultaneously compensate for the impact of changes in any one of the power supply voltage, operating temperature, and manufacturing process on the rising edge delay time, so that the change in the rising edge delay time T is smaller, thereby improving the delay circuit's ability to control the accuracy of the rising edge delay time.

[0238] The present application also provides a delay circuit, comprising: Figure 22 to Figure 26Any of the potential generating circuits and delay units shown, the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor, the substrate end of the fifth transistor is connected to the power supply end, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0239] Wherein, optionally, the ratio of the channel length of the first transistor to the channel length of the fourth transistor is recorded as H, the ratio of the channel length of the second transistor to the channel length of the fifth transistor is recorded as L, the ratio of the channel width of the first transistor to the channel width of the fourth transistor is recorded as M, the ratio of the channel width of the second transistor to the channel width of the fifth transistor is recorded as N, H is equal to L, and M is equal to N. Optionally, H, L, M and N can be 1. Optionally, the first transistor and the fourth transistor can be of the same type, and the second transistor and the fifth transistor can be of the same type.

[0240] The delay circuit provided in this embodiment can provide a substrate potential that changes with the first parameter for the substrate end of the N-type transistor in the inverter, because the potential of the substrate end of the second transistor in the potential generating circuit can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process. Therefore, the current flowing through the N-type transistor in the inverter can be adjusted, and the change value of the current flowing through the N-type transistor in the inverter can be compensated, so that the change of the falling edge delay time T of the delay circuit is small, thereby improving the control ability of the delay circuit on the accuracy of the falling edge delay time.

[0241] The delay circuit provided in this embodiment can be applied to scenarios where the falling edge delay time of the delay circuit needs to be accurately controlled, for example, it can be applied to DRAM, and can simultaneously compensate for the impact of changes in any one of the power supply voltage, operating temperature, and manufacturing process on the falling edge delay time, so that the change in the falling edge delay time T is smaller, thereby improving the delay circuit's ability to control the accuracy of the falling edge delay time.

[0242] The embodiment of the present application further provides a delay circuit, comprising: a first potential generating circuit, a second potential generating circuit and a delay unit, wherein:

[0243] The first potential generating circuit is as follows Fig.18 or Fig.19 or 20 or Fig.21 or Fig. 27 The potential generating circuit shown;

[0244] The second potential generating circuit is as follows Figure 22 to Figure 26 Any potential generating circuit shown;

[0245] A delay unit, the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor in the first potential generating circuit, the substrate end of the fifth transistor is connected to the potential of the substrate end of the second transistor in the second potential generating circuit, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0246] Wherein, optionally, the ratio of the channel length of the first transistor in the first potential generating circuit to the channel length of the fourth transistor is recorded as H1, the ratio of the channel length of the second transistor in the first potential generating circuit to the channel length of the fifth transistor is recorded as L1, the ratio of the channel width of the first transistor in the first potential generating circuit to the channel width of the fourth transistor is recorded as M1, the ratio of the channel width of the second transistor in the first potential generating circuit to the channel width of the fifth transistor is recorded as N1, H1 is equal to L1, and M1 is equal to N1. Optionally, H1, L1, M1 and N1 can be 1.

[0247] The ratio of the channel length of the first transistor in the second potential generating circuit to the channel length of the fourth transistor is recorded as H2, the ratio of the channel length of the second transistor in the second potential generating circuit to the channel length of the fifth transistor is recorded as L2, the ratio of the channel width of the first transistor in the second potential generating circuit to the channel width of the fourth transistor is recorded as M2, the ratio of the channel width of the second transistor in the second potential generating circuit to the channel width of the fifth transistor is recorded as N2, H2 is equal to L2, and M2 is equal to N2. Optionally, H2, L2, M2 and N2 can be 1.

[0248] The delay circuit provided in this embodiment can be applied to scenarios where the rising edge delay time and the falling edge delay time of the delay circuit need to be accurately controlled, for example, it can be applied to DRAM, and can simultaneously compensate for the influence of changes in any one of the power supply voltage, operating temperature and manufacturing process on the rising edge delay time and the falling edge delay time, so that the changes in the rising edge delay time T and the falling edge delay time T are relatively small, thereby improving the delay circuit's ability to control the accuracy of the rising edge delay time and the falling edge delay time.

[0249] It should be noted that the delay circuit provided in the embodiment of the present application can set the connection relationship between the potential generating circuit shown in the above two embodiments and the inverter in the delay unit according to the rising edge delay and / or falling edge delay realized by the delay unit. For example, a certain delay circuit realizes a rising edge delay, and the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. Then, a first potential generating circuit is set in the delay circuit. The first potential generating circuit can provide a substrate potential that changes with a first parameter to the substrate end of the P-type transistor in the inverter, thereby adjusting the current flowing through the P-type transistor in the inverter, and compensating for the change in the current flowing through the P-type transistor in the inverter, so that the change in the rising edge delay time T of the delay circuit is smaller. For another example, a delay circuit implements falling edge delay, and the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. In this delay circuit, a second potential generating circuit is provided, and the second potential generating circuit can provide a substrate potential that changes with a first parameter to the substrate end of the N-type transistor in the inverter, thereby adjusting the current flowing through the N-type transistor in the inverter, compensating for the change in the current flowing through the N-type transistor in the inverter, and making the change in the falling edge delay time T of the delay circuit smaller. For another example, a certain delay circuit realizes delay of both rising edge and falling edge, and the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. Then, a first potential generating circuit and a second potential generating circuit are provided in the delay circuit, and the first potential generating circuit can provide a substrate potential that changes with the first parameter for the substrate end of the P-type transistor in the inverter, thereby adjusting the current flowing through the P-type transistor in the inverter, and compensating for the change value of the current flowing through the P-type transistor in the inverter, so that the change of the rising edge delay time T of the delay circuit is small, and the second potential generating circuit can provide a substrate potential that changes with the first parameter for the substrate end of the N-type transistor in the inverter, thereby adjusting the current flowing through the N-type transistor in the inverter, and compensating for the change value of the current flowing through the N-type transistor in the inverter, so that the change of the falling edge delay time T of the delay circuit is small. Thus, the change of the rising edge delay time T and the falling edge delay time T of the delay circuit can be small. The control capability of the delay circuit on the accuracy of the delay time (including the rising edge delay time and the falling edge delay time) is improved.

[0250] Combine the following Figure 28-Figure 30 Give three examples of delay circuits, Fig.28 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.28 As shown, the delay circuit of this embodiment includes a potential generating circuit 1 and a delay unit 2. The potential generating circuit 1 is Fig.26 The circuit shown in the figure can be found in the detailed structure description. Fig.26The description in the illustrated embodiment will not be repeated here. The potential generating circuit 1 outputs the substrate potential BN. The delay unit 2 includes an inverter and a capacitor C1. The inverter includes a P-type transistor TP1 and an N-type transistor TN1. The substrate end of the P-type transistor TP1 is connected to the power supply end Vcc, and the substrate end of the N-type transistor TN1 is connected to the substrate potential BN. In the delay circuit of this embodiment, the potential generating circuit 1 provides the substrate end of the N-type transistor in the delay unit 2 with a substrate potential that changes with the first parameter, and can adjust the change value of the falling edge delay time of the delay circuit, so that the change of the falling edge delay time of the delay circuit is small, thereby reducing the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the falling edge delay time T of the delay circuit, so that the change of the falling edge delay time T is small, and the control ability of the delay circuit on the accuracy of the falling edge delay time is improved.

[0251] Fig.29 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.29 As shown, the delay circuit of this embodiment includes a potential generating circuit 1 and a delay unit 2. The potential generating circuit 1 is Fig. 27 The circuit shown in the figure can be found in the detailed structure description. Fig. 27 The description in the illustrated embodiment will not be repeated here. The potential generating circuit 1 outputs the substrate potential BP. The delay unit 2 includes an inverter and a capacitor C1. The inverter includes a P-type transistor TP1 and an N-type transistor TN1. The substrate end of the P-type transistor TP1 is connected to the substrate potential BP, and the substrate end of the N-type transistor TN1 is connected to the ground end. In the delay circuit of this embodiment, the potential generating circuit 1 provides the substrate end of the P-type transistor in the delay unit 2 with a substrate potential that changes with the first parameter, and can adjust the change value of the rising edge delay time of the delay circuit, so that the change of the rising edge delay time of the delay circuit is small, thereby reducing the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the rising edge delay time T of the delay circuit, so that the change of the rising edge delay time T is small, and the control ability of the delay circuit on the accuracy of the rising edge delay time is improved.

[0252] Fig.30 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.30 As shown, the delay circuit of this embodiment includes a first potential generating circuit 1, a second potential generating circuit 3 and a delay unit 2. The first potential generating circuit 1 is Fig. 27 The circuit shown in the figure can be found in the detailed structure description. Fig. 27 The description of the embodiment shown in the figure will not be repeated here. The first potential generating circuit 1 outputs the substrate potential BN. The second potential generating circuit 3 is Fig.28 The circuit shown in the figure can be found in the detailed structure description. Fig.28The description in the illustrated embodiment is not repeated here, and the second potential generating circuit 3 outputs the substrate potential BP. The delay unit 2 includes an inverter and a capacitor C1, the inverter includes a P-type transistor TP1 and an N-type transistor TN1, the substrate end of the P-type transistor TP1 is connected to the substrate potential BP output by the second potential generating circuit 3, and the substrate end of the N-type transistor TN1 is connected to the substrate potential BN output by the first potential generating circuit 1. In the delay circuit of this embodiment, the potential generating circuit 1 provides a substrate potential that varies with the first parameter for the substrate end of the N-type transistor in the delay unit 2, and can adjust the change value of the rising edge delay time of the delay circuit, so that the change of the rising edge delay time of the delay circuit is smaller. The potential generating circuit 3 provides a substrate potential that varies with the first parameter for the substrate end of the P-type transistor in the delay unit 2, and can adjust the change value of the falling edge delay time of the delay circuit, so that the change of the falling edge delay time of the delay circuit is smaller. Therefore, the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the delay time T (including the rising edge delay time and the falling edge delay time) of the delay circuit can be reduced, so that the change of the delay time T is smaller, and the delay circuit's ability to control the accuracy of the delay time is improved.

[0253] The embodiment of the present application also provides an inverter, Fig.31 A schematic diagram of the structure of an inverter provided in an embodiment of the present application is shown in FIG. Fig.31 As shown, the inverter comprises:

[0254] P-type transistor TP2 and N-type transistor TN2, the source terminal of P-type transistor TP2 is connected to the power supply terminal, the drain terminal of P-type transistor TP2 is connected to the drain terminal of N-type transistor TN2, the source terminal of N-type transistor TN2 is connected to the ground terminal, the gate terminal of P-type transistor TP2 is connected to the gate terminal of N-type transistor TN2 and serves as the input terminal of the inverter, and the drain terminal of P-type transistor TP2 serves as the output terminal of the inverter.

[0255] The substrate terminal of the P-type transistor TP2 is connected to the substrate potential, and the substrate terminal of the N-type transistor TN2 is connected to the ground terminal. The substrate potential changes with the first parameter, which is any one of the power supply voltage, operating temperature and manufacturing process of the inverter.

[0256] If the first parameter is the power supply voltage or the operating temperature of the inverter, the substrate potential increases as the first parameter increases, and the substrate potential decreases as the first parameter decreases.

[0257] The inverter provided in this embodiment can provide a substrate potential that changes with the first parameter to the substrate end of the P-type transistor TP2 because the substrate potential can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process. Therefore, the current flowing through the P-type transistor TP2 of the inverter can be adjusted, and the change value of the current flowing through the P-type transistor TP2 can be compensated, so that the change of the rising edge delay time T of the inverter is small, thereby improving the inverter's ability to control the accuracy of the rising edge delay time.

[0258] Fig.32 A schematic diagram of the structure of an inverter provided in an embodiment of the present application is shown in FIG. Fig.32 As shown, the inverter includes: a P-type transistor TP2 and an N-type transistor TN2, the source end of the P-type transistor TP2 is connected to the power supply end, the drain end of the P-type transistor TP2 is connected to the drain end of the N-type transistor TN2, the source end of the N-type transistor TN2 is connected to the ground end, the gate end of the P-type transistor TP2 is connected to the gate end of the N-type transistor TN2 and serves as the input end of the inverter, and the drain end of the P-type transistor TP2 serves as the output end of the inverter.

[0259] The substrate terminal of the N-type transistor TN2 is connected to the substrate potential, and the substrate terminal of the P-type transistor TP2 is connected to the power supply terminal. The substrate potential changes with the first parameter, which is any one of the power supply voltage, operating temperature and manufacturing process of the inverter.

[0260] If the first parameter is the power supply voltage or the operating temperature of the inverter, the substrate potential decreases as the first parameter increases, and the substrate potential increases as the first parameter decreases.

[0261] The inverter provided in this embodiment can provide a substrate potential that changes with the first parameter to the substrate end of the N-type transistor TN2 because the substrate potential can change with the change of any one of the power supply voltage, the operating temperature and the manufacturing process. Therefore, the current flowing through the N-type transistor TN2 of the inverter can be adjusted, and the change value of the current flowing through the N-type transistor TN2 can be compensated, so that the change of the falling edge delay time T of the inverter is small, thereby improving the inverter's ability to control the accuracy of the falling edge delay time.

[0262] The embodiment of the present application also provides a delay circuit, Fig.33 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.33 As shown, the delay circuit of this embodiment may include Fig.31 The inverter and the capacitor C1 are shown, and one end of the capacitor C1 is connected to the ground. In an operative manner, the capacitor C1 may be a capacitor array.

[0263] The delay circuit provided in this embodiment can compensate for the change in the current of the P-type transistor TP2 flowing through the inverter, so that the change in the rising edge delay time T of the inverter is small, and thus the change in the rising edge delay time T of the delay circuit can be small, thereby improving the delay circuit's ability to control the accuracy of the rising edge delay time.

[0264] The embodiment of the present application also provides a delay circuit, Fig.34 A schematic diagram of a delay circuit provided in an embodiment of the present application is shown in FIG. Fig.34 As shown, the delay circuit of this embodiment may include Fig.32 The inverter and the capacitor C1 are shown, and one end of the capacitor C1 is connected to the ground. In an operative manner, the capacitor C1 may be a capacitor array.

[0265] The delay circuit provided in this embodiment can compensate for the change in the current of the N-type transistor TN2 flowing through the inverter, so that the change in the falling edge delay time T of the inverter is small, and thus the change in the falling edge delay time T of the delay circuit can be small, thereby improving the delay circuit's ability to control the accuracy of the falling edge delay time.

[0266] An embodiment of the present application also provides a logic gate circuit, including: a P-type transistor and an N-type transistor, wherein the substrate end of the P-type transistor is connected to a substrate potential, and the substrate end of the N-type transistor is connected to a ground end, and the substrate potential changes with a first parameter, so that a delay time from an input end to an output end of the logic gate circuit changes with the first parameter and the change value thereof is within a first range, and the first parameter includes any one of a power supply voltage, an operating temperature, and a manufacturing process of the logic gate circuit.

[0267] Specifically, the first range is a smaller range, for example, a range close to 0. If the first range is 1% or 3% or 5%, the rising edge delay time from the input to the output of the logic gate circuit can change less when any one of the power supply voltage, operating temperature and manufacturing process changes, thereby improving the logic gate circuit's ability to control the accuracy of the rising edge delay time.

[0268] An embodiment of the present application also provides a logic gate circuit, including: a P-type transistor and an N-type transistor, wherein the substrate end of the N-type transistor is connected to a substrate potential, and the substrate end of the P-type transistor is connected to a power supply end, and the substrate potential changes with a first parameter, so that a delay time from an input end to an output end of the logic gate circuit changes with the first parameter and the change value thereof is within a first range, and the first parameter includes any one of a power supply voltage, an operating temperature, and a manufacturing process of the logic gate circuit.

[0269] Specifically, the first range is a smaller range, for example, a range close to 0. If the first range is 1% or 3% or 5%, the falling edge delay time from the input to the output of the logic gate circuit can change less when any one of the power supply voltage, operating temperature and manufacturing process changes, thereby improving the logic gate circuit's ability to control the accuracy of the falling edge delay time.

[0270] Embodiment 3

[0271] Fig.35 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.35 As shown, the control circuit of this embodiment may include: a control unit 41, a first feedback unit 42 and a second feedback unit 43, wherein the first feedback unit 42 is used to output a first feedback signal according to the voltage of the control unit 41 and the first reference voltage, the first end of the first feedback unit 42 is connected to the first end of the control unit, the second end of the first feedback unit 42 is the input end of the first reference voltage, and the output end of the first feedback unit 42 is connected to the second end of the control unit 41 and the first end of the second feedback unit 43.

[0272] The second feedback unit 43 is used to output a second feedback signal according to the voltage output by the first feedback unit 42 and the second reference voltage. The second end of the second feedback unit 43 is the input end of the second reference voltage. The output end of the second feedback unit 43 is connected to the third end of the control unit 41.

[0273] The control unit 41 is used to adjust the voltage of the second terminal of the control unit 41 according to the first feedback signal, and adjust the voltage of the third terminal of the control unit 41 according to the second feedback signal, so that the change value of the current of the control unit 41 with the change of the first parameter is within the first range, and the first parameter includes at least one of the manufacturing process, power supply voltage and operating temperature of the control circuit, the fourth terminal of the control unit 41 is connected to the first power supply terminal, and the fifth terminal of the control unit 41 is connected to the negative power supply terminal. Specifically, the first range is a smaller range, for example, a range close to 0, such as the first range is 1% or 3% or 5%, so that the change of the current of the control unit 41 with the change of the first parameter can be smaller.

[0274] Fig.36 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.36 As shown, this embodiment and Fig.35 The difference between the illustrated embodiment is that the fourth terminal of the control unit 41 is connected to the second power supply terminal, and the fifth terminal of the control unit 41 is connected to the ground terminal Vgg.

[0275] Fig.35 and Fig.36The control circuit shown is provided with a control unit, a first feedback unit and a second feedback unit, wherein the first end of the first feedback unit is connected to the first end of the control unit, the second end of the first feedback unit is the input end of the first reference voltage, the output end of the first feedback unit is connected to the second end of the control unit and the first end of the second feedback unit, the second end of the second feedback unit is the input end of the second reference voltage, and the output end of the second feedback unit is connected to the third end of the control unit. The first feedback unit is used to output a first feedback signal according to the voltage of the control unit and the first reference voltage, the second feedback unit is used to output a second feedback signal according to the voltage output by the first feedback unit and the second reference voltage, the control unit is used to adjust the voltage of the second end of the control unit according to the first feedback signal, and adjust the voltage of the third end of the control unit according to the second feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within a first range, and the first parameter is any one of the power supply voltage, the working temperature and the manufacturing process, so that the second end of the control unit and the third end of the control unit can respectively output a voltage that changes with any one of the power supply voltage, the working temperature and the manufacturing process.

[0276] Fig.37 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.37 As shown, the control circuit of this embodiment is Fig.35 On the basis of the circuit shown, further, the control unit 41 may include an inverter 411 and a constant current source 412, wherein a first end of the inverter 411 is connected to a first power supply end;

[0277] A first end of the constant current source 412 is connected to a second end of the inverter 411, and a second end of the constant current source 412 is connected to a negative power supply end;

[0278] The input terminal of the inverter 411 is short-circuited with the output terminal of the inverter 411 .

[0279] Fig.38 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.38 As shown, the control circuit of this embodiment is Fig.37 On the basis of the circuit shown, further, the inverter 411 includes a first transistor T1 and a second transistor T2, the substrate end of the first transistor T1 is connected to the output end of the second feedback unit 43, and the substrate end of the second transistor T2 is connected to the output end of the first feedback unit 42;

[0280] The first end of the first transistor T1 is connected to the first power supply end, the second end of the first transistor T1 is connected to the first end of the second transistor T2, the control end of the first transistor T1 is connected to the control end of the second transistor T2, and the second end of the second transistor T2 is connected to the first end of the constant current source 412.

[0281] In this embodiment, the control unit 41 is used to adjust the voltage of the substrate terminal of the second transistor T2 according to the first feedback signal, and to adjust the voltage of the substrate terminal of the first transistor T1 according to the second feedback signal.

[0282] The control circuit provided in this embodiment has a control unit used to adjust the voltage of the substrate terminal of the second transistor according to a first feedback signal, and to adjust the voltage of the substrate terminal of the first transistor according to a second feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within a first range, and the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process. Thus, the substrate terminal of the first transistor and the substrate terminal of the second transistor can respectively output a voltage that changes with the change of any one of the power supply voltage, the operating temperature and the manufacturing process.

[0283] Fig.39 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.39 As shown, the control circuit of this embodiment is Fig.36 On the basis of the circuit shown, further, the control unit 41 may include an inverter 411 and a constant current source 412, and a first end of the inverter 411 is connected to the ground end;

[0284] A first end of the constant current source 412 is connected to the second end of the inverter 411, and a second end of the constant current source 412 is connected to the second power supply end;

[0285] The input terminal of the inverter 411 is short-circuited with the output terminal of the inverter 411 .

[0286] Fig.40 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.40 As shown, the control circuit of this embodiment is Fig.39 On the basis of the circuit shown, further, the inverter 411 includes a first transistor T1 and a second transistor T2, the substrate end of the first transistor T1 is connected to the output end of the first feedback unit, and the substrate end of the second transistor T2 is connected to the output end of the second feedback unit 43.

[0287] A first terminal of the first transistor T1 is connected to a first terminal of a constant current source, a second terminal of the first transistor T1 is connected to a first terminal of a second transistor T2, a control terminal of the first transistor T1 is connected to a control terminal of the second transistor T2, and a second terminal of the second transistor T2 is connected to a ground terminal.

[0288] In this embodiment, the control unit 41 is used to adjust the voltage of the substrate terminal of the second transistor T2 according to the first feedback signal, and to adjust the voltage of the substrate terminal of the first transistor T1 according to the second feedback signal.

[0289] The control circuit provided in this embodiment has a control unit used to adjust the voltage of the substrate terminal of the second transistor according to a first feedback signal, and to adjust the voltage of the substrate terminal of the first transistor according to a second feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within a first range, and the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process. Thus, the substrate terminal of the first transistor and the substrate terminal of the second transistor can respectively output a voltage that changes with the change of any one of the power supply voltage, the operating temperature and the manufacturing process.

[0290] exist Fig.38 and Fig.40 In the control circuit shown, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0291] The specific implementable structures of the first feedback unit and the second feedback unit are described in detail below with reference to the accompanying drawings.

[0292] Fig.41 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.41 As shown, the control circuit of this embodiment is Fig.38 On the basis of the circuit shown, further, the first feedback unit 42 includes a first error amplifier 421, the negative input terminal of the first error amplifier 421 is connected to the first terminal of the control unit 41, the positive input terminal of the first error amplifier 421 is the input terminal of the first reference voltage, and the output terminal of the first error amplifier 421 is connected to the second terminal of the control unit 41 and the first terminal of the second feedback unit 43.

[0293] like Fig.41 As shown, further, the second feedback unit 43 includes a second error amplifier 431, a first resistor R1, a second resistor R2 and a third transistor T3, wherein the negative input terminal of the second error amplifier 431 is the input terminal of the second reference voltage, the positive input terminal of the second error amplifier 431 is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, and the output terminal of the second error amplifier 431 is connected to the control terminal of the third transistor T3;

[0294] The second end of the first resistor R1 is connected to the first end of the third transistor T3 and the third end of the control unit 41;

[0295] A second end of the second resistor R2 is connected to the output end of the first feedback unit and a second end of the control unit 41;

[0296] The second terminal of the third transistor is connected to the first power supply terminal.

[0297] Fig.42 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.42 As shown, the control circuit of this embodiment is Fig.40 On the basis of the circuit shown, further, the first feedback unit 42 includes a first error amplifier 421, the negative input terminal of the first error amplifier 421 is connected to the first terminal of the control unit 41, the positive input terminal of the first error amplifier 421 is the input terminal of the first reference voltage, and the output terminal of the first error amplifier 421 is connected to the second terminal of the control unit 41 and the first terminal of the second feedback unit 43.

[0298] like Fig.42 As shown, further, the second feedback unit 43 includes a second error amplifier 431, a first resistor R1, a second resistor R2 and a third transistor T3, wherein the negative input terminal of the second error amplifier 431 is the input terminal of the second reference voltage, the positive input terminal of the second error amplifier 431 is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, and the output terminal of the second error amplifier 431 is connected to the control terminal of the third transistor T3;

[0299] A second end of the first resistor R1 is connected to the output end of the first feedback unit and a second end of the control unit 41;

[0300] The second end of the second resistor R2 is connected to the first end of the third transistor T3 and the third end of the control unit 41;

[0301] The second terminal of the third transistor is connected to the ground terminal.

[0302] exist Fig.41 or Fig.42 The control circuit shown in the figure may further include a first buffer and a second buffer. Fig.43 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.44 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.43 and Fig.44 As shown, in Fig.41 or Fig.42 On the basis of the control circuit shown, it can further include: a first buffer 44 and a second buffer 45, wherein the first buffer 44 is connected to the substrate end of the first transistor T1 and outputs a first substrate voltage, the value of the first substrate voltage is equal to the voltage value of the substrate end of the first transistor T1, the input voltage and the output voltage of the first buffer 44 are the same, the first buffer 44 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid interference with the potential of the substrate end of the first transistor T1.

[0303] The second buffer 45 is connected to the substrate end of the second transistor T2 and outputs a second substrate voltage. The value of the second substrate voltage is equal to the voltage value of the substrate end of the first transistor T1. The second buffer 45 is used to enhance the driving capability of the potential of the substrate end of the second transistor T2 and can also isolate the substrate end of the second transistor T2 to prevent the potential of the substrate end of the second transistor T2 from being disturbed.

[0304] It should be noted that in Figure 35-Figure 44 In the control circuit shown, the voltage of the first power supply terminal is, for example, Vcc, the second reference voltage may be Vcc / 2, the voltage of the negative power supply terminal may be a voltage value less than 0, and the first reference voltage may be 0.

[0305] The voltage of the second power supply terminal is greater than the voltage of the first reference voltage, and the value of the second reference voltage can be half of the first reference voltage. For example, the voltage of the second power supply terminal is Vdd, the first reference voltage is Vcc, Vdd is greater than Vcc, and the value of the second reference voltage can be Vcc / 2.

[0306] The structure of the control circuit of the present application is described below in conjunction with specific embodiments. The specific structure of the control circuit of the present application is not limited to any of the following structures.

[0307] Specifically, the specific structure of the control circuit of this embodiment can be seen in Fig.11 and Fig.12 The circuit structure shown, Fig.11 and Fig.12 The potential generating circuit shown is the control circuit in this embodiment, and the working principle is the same. For details, please refer to Fig.11 and Fig.12 The description of the illustrated embodiment will not be repeated here.

[0308] The embodiment of the application also provides a delay circuit, comprising Figure 35-Figure 44 Any of the control circuits and delay units shown, wherein the second end of the control unit in the control circuit is connected to the first end of the delay unit, the third end of the control unit is connected to the second end of the delay unit, and the control circuit is used to control the rising edge delay time and / or falling edge delay time of the delay unit to change with the first parameter within a first range.

[0309] Optionally, the delay unit includes an inverter, the inverter includes a fourth transistor and a fifth transistor, the third end of the control unit is connected to the substrate end of the fourth transistor, and the second end of the control unit is connected to the substrate end of the fifth transistor.

[0310] Optionally, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0311] In this embodiment, optionally, the control circuit in the delay circuit is Fig.38 or Fig.40 or Figure 41-44 In any of the control circuits shown, the ratio of the channel length of the first transistor to the channel length of the fourth transistor is H, the ratio of the channel length of the second transistor to the channel length of the fifth transistor is L, the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M, the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N, H is equal to L, and M is equal to N.

[0312] In the delay circuit provided in this embodiment, since the second end of the control unit and the third end of the control unit can respectively output a voltage that changes with the first parameter (which is any one of the power supply voltage, the operating temperature and the manufacturing process), the first substrate voltage that changes with the first parameter can be provided to the substrate end of the fourth transistor, and the second substrate voltage that changes with the first parameter can be provided to the substrate end of the fifth transistor, so that the change value of the current flowing through the two transistors of the inverter with the change of the first parameter can be adjusted within the first range, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the change of the delay time T of the delay circuit is small, and the control ability of the delay circuit on the accuracy of the delay time is improved.

[0313] It should be noted that, in the embodiment of the present application, the connection relationship between the control circuit and the inverter can be set according to the number of inverters included in the delay circuit and the demand for delay time compensation, the substrate end of the P-type transistor in the inverter is connected to the substrate end of the P-type transistor in the control circuit, and the change value of the rising edge delay time of the delay circuit can be adjusted, and the substrate end of the N-type transistor in the inverter is connected to the substrate end of the N-type transistor in the control circuit, and the change value of the falling edge delay time of the delay circuit can be adjusted. Specifically, the connection relationship between the control circuit and the inverter can be set according to the change value of the rising edge and / or falling edge delay time that needs to be adjusted. The control circuit provided in the embodiment of the present application can be applied to a delay circuit in which both the rising edge and / or the falling edge are delayed, and can reduce the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the delay time T of the delay circuit, so that the change of the delay time T (including the rising edge and / or the falling edge) is small, and the control ability of the delay circuit on the accuracy of the delay time is improved.

[0314] Figure 13-Figure 15 Two examples of delay circuits are given, which are also applicable to this embodiment. Figure 13-Figure 15 The potential generating circuit shown in is the specific control circuit in this embodiment, which can be seen in Figure 13-Figure 15 The specific description in will not be repeated here.

[0315] Embodiment 4

[0316] Fig.45 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.45 As shown, the control circuit of this embodiment may include: a control unit 51 and a feedback unit 52, wherein:

[0317] The feedback unit 52 is used to output a feedback signal according to the voltage of the control unit 51 and the reference voltage. Its first end is connected to the first end of the control unit 51, its second end is the input end of the reference voltage, and its output end is connected to the second end of the control unit 51.

[0318] The control unit 51 is used to adjust the voltage of the second end of the control unit 51 according to the feedback signal so that the change value of the current of the control unit 51 with the change of the first parameter is within a first range, and the first parameter includes at least one of the manufacturing process, power supply voltage and operating temperature of the control circuit. The third end of the control unit 51 is connected to the first power supply end, and the fourth end of the control unit 51 is connected to the negative power supply end.

[0319] Specifically, the first range is a smaller range, for example, a range close to 0, such as 1% or 3% or 5%, so that the current of the control unit 41 changes less with the change of the first parameter.

[0320] Fig.46 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.46 As shown, this embodiment and Fig.45 The difference between the illustrated embodiment is that the third terminal of the control unit 51 is connected to the second power supply terminal, and the fourth terminal of the control unit 51 is connected to the ground terminal Vgg.

[0321] Fig.45 and Fig.46 The control circuit shown is provided with a control unit and a feedback unit, wherein the feedback unit is used to output a feedback signal according to the voltage of the control unit and a reference voltage, and the control unit is used to adjust the voltage of the second end of the control unit according to the feedback signal so that the change value of the current of the control unit with the change of the first parameter is within a first range, and the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process, so that the second end of the control unit can output a voltage that changes with any one of the power supply voltage, the operating temperature and the manufacturing process.

[0322] Fig.47 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.47 As shown, the control circuit of this embodiment is Fig.45 On the basis of the circuit shown, further, the control unit 51 may include an inverter 511 and a constant current source 512, the first end of the inverter 511 is connected to the first power supply end, the first end of the constant current source 512 is connected to the second end of the inverter 511, the second end of the constant current source 512 is connected to the negative power supply end, and the input end of the inverter 511 is short-circuited with the output end of the inverter 511.

[0323] Fig.48 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.48 As shown, the control circuit of this embodiment is Fig.47 On the basis of the circuit shown, further, the inverter 411 includes a first transistor T1 and a second transistor T2, the substrate end of the first transistor T1 is connected to the first power supply end, and the substrate end of the second transistor T2 is connected to the output end of the feedback unit 52;

[0324] A first terminal of the first transistor T1 is connected to a first power supply terminal, a second terminal of the first transistor T1 is connected to a first terminal of the second transistor T2, a control terminal of the first transistor T1 is connected to a control terminal of the second transistor T2, and a second terminal of the second transistor T2 is connected to a first terminal of a constant current source.

[0325] In this embodiment, the control unit 41 is used to adjust the voltage at the substrate terminal of the second transistor T2 according to the feedback signal.

[0326] The control circuit provided in this embodiment, the control unit is used to adjust the voltage of the substrate terminal of the second transistor according to the feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within a first range, and the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process. Therefore, the substrate terminal of the second transistor can output a voltage that changes with the change of any one of the power supply voltage, the operating temperature and the manufacturing process.

[0327] Fig.49 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.49 As shown, the control circuit of this embodiment is Fig.46 On the basis of the circuit shown, further, the control unit 51 may include an inverter 511 and a constant current source 512, wherein a first end of the inverter 511 is connected to a ground end, a first end of the constant current source 512 is connected to a second end of the inverter 511, a second end of the constant current source 512 is connected to a second power supply end, and an input end of the inverter 511 is short-circuited with an output end of the inverter 511.

[0328] Fig.50 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.50 As shown, the control circuit of this embodiment is Fig.49 On the basis of the circuit shown, further, the inverter 511 includes a first transistor T1 and a second transistor T2, the substrate end of the first transistor T1 is connected to the output end of the feedback unit, and the substrate end of the second transistor is connected to the ground end;

[0329] The first end of the first transistor T1 is connected to the first end of the constant current source, the second end of the first transistor T1 is connected to the first end of the second transistor T2, the control end of the first transistor T1 is connected to the control end of the second transistor T2, and the second end of the second transistor T2 is connected to the ground end.

[0330] In this embodiment, the control unit 51 is used to adjust the voltage at the substrate terminal of the first transistor T1 according to the feedback signal.

[0331] The control circuit provided in this embodiment, the control unit is used to adjust the voltage of the substrate terminal of the first transistor according to the feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within a first range, and the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process. Therefore, the substrate terminal of the first transistor can output a voltage that changes with the change of any one of the power supply voltage, the operating temperature and the manufacturing process.

[0332] exist Fig.48 and Fig.50 In the control circuit shown, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0333] The specific implementable structure of the feedback unit is described in detail below with reference to the accompanying drawings.

[0334] Fig.51 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.51 As shown, the control circuit of this embodiment is Fig.48 On the basis of the circuit shown, further, the feedback unit 52 includes an error amplifier 521, the negative input terminal of the error amplifier 521 is connected to the first end of the constant current source 512 and the second end of the second transistor T2, the positive input terminal of the error amplifier 521 is the reference voltage input terminal, and the output terminal of the error amplifier 521 is connected to the substrate terminal of the second transistor T2.

[0335] Fig.52 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.52 As shown, the control circuit of this embodiment is Fig.51 Based on the circuit shown, further, it can also include:

[0336] The buffer 53 is connected to the substrate terminal of the second transistor T2 and outputs a first substrate voltage, wherein the value of the first substrate voltage is equal to the voltage value of the substrate terminal of the second transistor T2.

[0337] Fig.53 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.53 As shown, the control circuit of this embodiment is Fig.50On the basis of the circuit shown, further, the feedback unit 52 includes an error amplifier 521, the negative input terminal of the error amplifier 521 is connected to the first end of the constant current source 512 and the first end of the first transistor T1, the negative input terminal of the error amplifier 521 is the reference voltage input terminal, and the output terminal of the error amplifier 521 is connected to the substrate terminal of the first transistor T1.

[0338] Fig.54 A schematic diagram of a control circuit provided in an embodiment of the present application is shown in FIG. Fig.54 As shown, the control circuit of this embodiment is Fig.53 On the basis of the circuit shown, it can further include: a buffer 53, the buffer 53 is connected to the substrate end of the first transistor T1, and outputs a second substrate voltage, the value of the second substrate voltage is equal to the voltage value of the substrate end of the first transistor T1.

[0339] It should be noted that in Figure 45-Figure 54 In the control circuit shown, the voltage of the first power supply terminal is, for example, Vcc, the second reference voltage may be Vcc / 2, the voltage of the negative power supply terminal may be 0 or less than 0, and the first reference voltage may be 0.

[0340] The voltage of the second power supply terminal is greater than the voltage of the first reference voltage, and the value of the second reference voltage can be half of the first reference voltage. For example, the voltage of the second power supply terminal is Vdd, the first reference voltage is Vcc, Vdd is greater than Vcc, and the value of the second reference voltage can be Vcc / 2.

[0341] The structure of the control circuit of the present application is described below in conjunction with specific embodiments. The specific structure of the control circuit of the present application is not limited to any of the following structures.

[0342] Specifically, the specific structure of the control circuit of this embodiment can be seen in Fig.26 and Fig. 27 The circuit structure shown, Fig.26 and Fig. 27 The potential generating circuit shown is the control circuit in this embodiment, and the working principle is the same. For details, please refer to Fig.26 and Fig. 27 The description of the illustrated embodiment will not be repeated here.

[0343] The present application also provides a delay circuit, comprising: Figure 45-Figure 54 Any of the control circuits and delay units shown, wherein the second end of the control unit is connected to the first end of the delay unit, and the control circuit is used to control the rising edge delay time and / or falling edge delay time of the delay unit so that the change value thereof changes with the first parameter within a first range.

[0344] Optionally, the delay unit includes an inverter, the inverter includes a fourth transistor and a fifth transistor, and the second end of the control unit is connected to the substrate end of the fourth transistor or the substrate end of the fifth transistor.

[0345] Optionally, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0346] When the fifth terminal of the control unit is connected to the negative power supply terminal, the second terminal of the control unit is connected to the substrate terminal of the fifth transistor.

[0347] The third terminal of the control unit is connected to the second power supply terminal, the fourth terminal of the control unit is connected to the ground terminal, and the second terminal of the control unit is connected to the substrate terminal of the fourth transistor.

[0348] In this embodiment, optionally, the control circuit in the delay circuit is Fig.48 or Fig.50 or Figure 51-54 In any of the control circuits shown, the ratio of the channel length of the first transistor to the channel length of the fourth transistor is H, the ratio of the channel length of the second transistor to the channel length of the fifth transistor is L, the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M, the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N, H is equal to L, and M is equal to N.

[0349] In the delay circuit provided in this embodiment, since the second end of the control unit can output a voltage that changes with the first parameter (which is any one of the power supply voltage, the operating temperature and the manufacturing process), the first substrate voltage that changes with the first parameter can be provided to the substrate end of the fourth transistor, so that the change value of the current flowing through the fourth transistor of the inverter with the change of the first parameter can be adjusted within the first range, and the change value of the current flowing through the fourth transistor of the inverter is compensated, so that the change of the rising edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the accuracy of the rising edge delay time is improved.

[0350] Alternatively, a first substrate voltage that changes with the first parameter can be provided to the substrate end of the fifth transistor, so that the change value of the current flowing through the fifth transistor of the inverter as the first parameter changes can be adjusted within a first range, and the change value of the current flowing through the fifth transistor of the inverter is compensated, so that the change of the falling edge delay time T of the delay circuit is smaller, thereby improving the control ability of the delay circuit on the accuracy of the falling edge delay time.

[0351] It should be noted that the delay circuit provided in the embodiment of the present application can set the connection relationship between the control circuit shown in the above two embodiments and the inverter in the delay unit according to the rising edge delay and / or falling edge delay realized by the delay unit. For example, a certain delay circuit realizes the rising edge delay, and the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. Then, a first control circuit is set in the delay circuit, and the first control circuit can adjust the voltage at the substrate end of the P-type transistor in the inverter, thereby adjusting the current flowing through the P-type transistor in the inverter, so that the change value of the current flowing through the P-type transistor in the inverter with the change of the first parameter is within a first range, and the change value of the current flowing through the P-type transistor in the inverter is compensated, so that the change of the rising edge delay time T of the delay circuit is smaller. For another example, a delay circuit implements falling edge delay, and the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. A second control circuit is set in the delay circuit, and the second control circuit can adjust the voltage at the substrate end of the N-type transistor in the inverter, thereby adjusting the current flowing through the N-type transistor in the inverter, so that the change value of the current flowing through the N-type transistor in the inverter with the change of the first parameter is within a first range, and the change value of the current flowing through the N-type transistor in the inverter is compensated, so that the change of the falling edge delay time T of the delay circuit is smaller. For another example, a certain delay circuit realizes delay of both rising edge and falling edge, and the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. Then, a first control circuit and a second control circuit are set in the delay circuit, and the first control circuit can adjust the voltage of the substrate terminal of the P-type transistor in the inverter, thereby adjusting the current flowing through the P-type transistor in the inverter, so that the change value of the current flowing through the P-type transistor in the inverter with the change of the first parameter is within a first range, and the change value of the current flowing through the P-type transistor in the inverter is compensated, so that the change of the rising edge delay time T of the delay circuit is small, and the second control circuit can adjust the voltage of the substrate terminal of the N-type transistor in the inverter, thereby adjusting the current flowing through the N-type transistor in the inverter, so that the change value of the current flowing through the N-type transistor in the inverter with the change of the first parameter is within a first range, and the change value of the current flowing through the N-type transistor in the inverter is compensated, so that the change of the falling edge delay time T of the delay circuit is small. Thus, the change of the rising edge delay time T and the falling edge delay time T of the delay circuit can be small. Improve the delay circuit's ability to control the accuracy of delay time (including rising edge delay time and falling edge delay time).

[0352] Figure 28-Figure 30 Two examples of delay circuits are given, which are also applicable to this embodiment. Figure 28-Figure 30 The potential generating circuit shown in is the specific control circuit in this embodiment, which can be seen in Figure 28-Figure 30The specific description in will not be repeated here.

[0353] The constant current source in the above embodiment may be a mirror current source, for example. The current at the mirror end may be a current that is independent of the temperature coefficient, or the current may be independent of temperature, voltage, etc. The constant current source in the above embodiment may also be implemented in other ways.

[0354] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A potential generating circuit, characterized in that: include: a first transistor, wherein the potential of a substrate terminal of the first transistor changes with a first parameter, and the first parameter is any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit; a second transistor, wherein a potential at a substrate terminal of the second transistor changes as the first parameter changes; Wherein, the gate terminal of the first transistor is connected to the drain terminal of the first transistor, and the substrate terminal of the first transistor serves as the first output terminal of the potential generating circuit; the gate terminal of the second transistor is connected to the drain terminal of the second transistor, and the substrate terminal of the second transistor serves as the second output terminal of the potential generating circuit; The first transistor is a P-type transistor, and the second transistor is an N-type transistor; the source terminal of the first transistor is connected to a first voltage node, the source terminal of the second transistor is connected to a second voltage node, and the drain terminal of the first transistor is connected to the drain terminal of the second transistor; The potential generating circuit further includes a constant current source, a first end of the constant current source is connected to the second voltage node, and a second end of the constant current source is connected to a third voltage node.

2. The potential generating circuit according to claim 1, characterized in that: The first parameter is a supply voltage or an operating temperature of the potential generating circuit, and the potential of the substrate terminal of the first transistor increases as the first parameter increases, and the potential of the substrate terminal of the first transistor decreases as the first parameter decreases; The potential of the substrate terminal of the second transistor decreases as the first parameter increases, and the potential of the substrate terminal of the second transistor increases as the first parameter decreases.

3. The potential generating circuit according to claim 1, characterized in that: Also includes: A first error amplifier, forming a first feedback loop with the second transistor, wherein a substrate terminal of the second transistor is connected to a voltage node of the first feedback loop; A second error amplifier and a third transistor, wherein the second error amplifier and the third transistor form a second feedback loop, and a substrate terminal of the first transistor is connected to a voltage node of the second feedback loop.

4. The potential generating circuit according to claim 3, characterized in that: A negative input terminal of the first error amplifier is connected to the second voltage node, a positive input terminal of the first error amplifier is connected to a first reference voltage, and an output terminal of the first error amplifier is connected to a substrate terminal of the second transistor; The negative input terminal of the second error amplifier is connected to the second reference voltage, the positive input terminal of the second error amplifier is connected to the fourth voltage node, the output terminal of the second error amplifier is connected to the gate terminal of the third transistor, the source terminal of the third transistor is connected to the first voltage node, the drain terminal of the third transistor is coupled to the fourth voltage node through a first resistor, and the output terminal of the first error amplifier is coupled to the fourth voltage node through a second resistor.

5. The potential generating circuit according to claim 4, characterized in that: The first voltage node is connected to a power supply terminal, the first reference voltage is connected to a ground terminal, and a potential of the third voltage node is lower than a potential of the first reference voltage.

6. A potential generating circuit, characterized in that: include: a first transistor, wherein the potential of a substrate terminal of the first transistor changes with a first parameter, and the first parameter is any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit; a second transistor, wherein a potential at a substrate terminal of the second transistor changes as the first parameter changes; Wherein, the gate terminal of the first transistor is connected to the drain terminal of the first transistor, and the substrate terminal of the first transistor serves as the first output terminal of the potential generating circuit; the gate terminal of the second transistor is connected to the drain terminal of the second transistor, and the substrate terminal of the second transistor serves as the second output terminal of the potential generating circuit; The first transistor is a P-type transistor, and the second transistor is an N-type transistor; the source terminal of the first transistor is connected to a first voltage node, the source terminal of the second transistor is connected to a second voltage node, and the drain terminal of the first transistor is connected to the drain terminal of the second transistor; The potential generating circuit further includes a constant current source, a first end of the constant current source is connected to the third voltage node, and a second end of the constant current source is connected to the first voltage node.

7. The potential generating circuit according to claim 6, characterized in that: Also includes: A first error amplifier, forming a first feedback loop with the first transistor, wherein a substrate terminal of the first transistor is connected to a voltage node of the first feedback loop; A second error amplifier and a third transistor, wherein the second error amplifier and the third transistor form a second feedback loop, and a substrate terminal of the second transistor is connected to a voltage node of the second feedback loop.

8. The potential generating circuit according to claim 7, characterized in that: A negative input terminal of the first error amplifier is connected to the first voltage node, a positive input terminal of the first error amplifier is connected to a first reference voltage, and an output terminal of the first error amplifier is connected to a substrate terminal of the first transistor; The negative input terminal of the second error amplifier is connected to the second reference voltage, the positive input terminal of the second error amplifier is connected to the fourth voltage node, the output terminal of the second error amplifier is connected to the gate terminal of the third transistor, the source terminal of the third transistor is connected to the second voltage node, the drain terminal of the third transistor is coupled to the fourth voltage node through the second resistor, and the output terminal of the first error amplifier is coupled to the fourth voltage node through the first resistor.

9. The potential generating circuit according to claim 8, characterized in that: The second voltage node is connected to the ground terminal, the first reference voltage is connected to the power supply terminal, and the potential of the third voltage node is greater than the potential of the first reference voltage.

10. The potential generating circuit according to any one of claims 1 to 9, characterized in that: Also includes: a first buffer connected to the first output terminal and outputting a first substrate potential, wherein a value of the first substrate potential is equal to a potential value of a substrate terminal of the first transistor; A second buffer is connected to the second output terminal and outputs a second substrate potential, wherein a value of the second substrate potential is equal to a potential value of a substrate terminal of the second transistor.

11. A delay circuit, characterized in that: include: The potential generating circuit according to any one of claims 1 to 9; A delay unit, the delay unit comprising a first inverter, the first inverter comprising a fourth transistor and a fifth transistor, a substrate terminal of the fourth transistor being connected to the potential of the substrate terminal of the first transistor, and a substrate terminal of the fifth transistor being connected to the potential of the substrate terminal of the second transistor; or, The potential generating circuit as claimed in claim 10; A delay unit, wherein the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the first substrate potential, and the substrate end of the fifth transistor is connected to the second substrate potential.

12. The delay circuit according to claim 11, characterized in that: Let the ratio of the channel length of the first transistor to the channel length of the fourth transistor be H, let the ratio of the channel length of the second transistor to the channel length of the fifth transistor be L, let the ratio of the channel width of the first transistor to the channel width of the fourth transistor be M, let the ratio of the channel width of the second transistor to the channel width of the fifth transistor be N, wherein H is equal to L, and M is equal to N.

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