Method and system for performing automatic routing

Abstract

A method, system, and non-transitory computer readable medium for wafer-level packaging routing are provided. The method includes performing triangulation on a set of nets to generate a routing resource graph. During the triangulation, objects of the set of nets are represented by corresponding center points. The method also includes generating routing between objects of the set of nets based at least on a total cost. The total cost is determined based at least on the routing resource graph. The method also includes: changing routing based on a determination that a constraint rule is not satisfied, and outputting routing information, the routing information including routing for the set of nets.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 885,504, filed August 12, 2019, which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The present disclosure relates to automated integrated fan-out wafer-level packaging routing. Background Art

[0004] Integrated fan-out (InFO) wafer-level packaging eliminates the substrate from traditional electronic packaging, enabling smaller size, lower power, and higher interconnect density. It also facilitates the integration of logic, memory, and passive components in a compact format. InFO technology is becoming increasingly popular in mobile applications and other mid- to high-end applications.

[0005] The InFO package design cycle involves many steps, including pin assignment, signal routing, power / ground routing, power / ground plane generation, and teardrop creation. Routing is a major part of the design cycle. Due to the complex design rules and the increasing number of I / O pins used in InFO packages, existing package redistribution layer (RDL) routers or printed circuit board (PCB) routers do not have the capacity or capability to perform fully automated routing. Significant manual intervention is required. Summary of the Invention

[0006] In one aspect, a method includes triangulating a set of nets to generate a routing resource graph. During the triangulation, objects of the set of nets are represented by corresponding center points. The method further includes generating routing between the objects of the set of nets based at least on a total cost. The total cost is determined based at least on the routing resource graph. The method further includes changing routing based on a determination that a constraint rule is not satisfied, and outputting routing information, the routing information including routing for the set of nets.

[0007] In one aspect, a system includes a memory storing instructions and a processor coupled to the memory and executing the instructions. When executed, the instructions cause the processor to: triangulate a set of nets to generate a routing resource graph; generate routing between objects in the set of nets based at least on a total cost; change the routing based on a determination that a constraint rule is not satisfied; and output routing information, the routing information including routing for the set of nets. During triangulation, the objects in the set of nets are represented by corresponding center points. The total cost is determined based at least on the routing resource graph.

[0008] In one aspect, a non-transitory computer-readable medium includes stored instructions that, when executed by a processor, cause the processor to: triangulate a set of nets to generate a routing resource graph, wherein during the triangulation, objects of the set of nets are represented by corresponding center points; generate routing between the objects of the set of nets based on at least a total cost, wherein the total cost is determined based on at least the routing resource graph; change routing based on a determination that a constraint rule is not satisfied; and output routing information, the routing information including routing for the set of nets. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure will be more fully understood based on the detailed description given below and the accompanying drawings according to embodiments of the present disclosure. The accompanying drawings are intended to provide knowledge and understanding of the embodiments of the present disclosure and are not intended to limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0010] Figure 1 An integrated fan-out (InFO) package routing flow according to one embodiment of the present disclosure is depicted.

[0011] Figure 2A Depicted is an actual layout shape according to one embodiment of the present disclosure.

[0012] Figure 2B Depicts the use of octagons to approximate a circular shape.

[0013] Figure 2C Depicted is the use of a center point to represent a circular shape according to one embodiment of the present disclosure.

[0014] Figure 3 A routing channel according to one embodiment of the present disclosure is depicted.

[0015] Figure 4 Depicted are search graph nodes and edges according to one embodiment of the present disclosure.

[0016] Figure 5 Capacity adjustment taking into account obstacle size according to one embodiment of the present disclosure is depicted.

[0017] Figure 6 Capacity adjustment taking into account obstacle size according to one embodiment of the present disclosure is depicted.

[0018] Figure 7 Capacity adjustment taking into account existing pre-wiring according to one embodiment of the present disclosure is depicted.

[0019] Figure 8 Capacity adjustment taking into account existing pre-wiring according to one embodiment of the present disclosure is depicted.

[0020] Figure 9Depicted is a pin-out routing example according to one embodiment of the present disclosure.

[0021] Figure 10 A pin-out routing flow according to one embodiment of the present disclosure is depicted.

[0022] Figure 11 An example of intersection detection according to one embodiment of the present disclosure is depicted.

[0023] Figure 12 Depicted is an example of repairing a sharp angle in the middle of a connection according to one embodiment of the present disclosure.

[0024] Figure 13 Depicted is the repair of a sharp angle occurring at the beginning or end of a connection according to one embodiment of the present disclosure.

[0025] Figure 14 Depicted is a power / ground routing example according to one embodiment of the present disclosure.

[0026] Figure 15 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure.

[0027] Figure 16 An abstract diagram of an example computer system is depicted in which embodiments may operate. DETAILED DESCRIPTION

[0028] Aspects of the present disclosure relate to methods and systems for performing automated integrated fan-out wafer-level packaging routing.

[0029] Conventional integrated fan-out (InFO) package routing can require multiple iterations due to unexpected requirements changes, netlist changes, or failure to pass all signoff checks. Each iteration can require a long run time, which increases with the number of I / O pins and routing layers available for InFO technology.

[0030] Conventional package routing solutions are typically limited to automatic routing at 45 or 90 degrees. Some package routers or printed circuit board (PCB) routers can resolve any-angle routing interactively, but not in batch mode. As the number of layers and pins in InFO packages increases, it is crucial to have accurate routing resource estimates and appropriate layer assignments for each net to achieve successful routing and enable automatic any-angle routing.

[0031] This paper describes a method for automating the routing of InFO wafer-level packages. Compared to conventional electronic packaging, the described automated routing method achieves smaller size, lower power, and higher interconnect density while improving design productivity. "Any-angle" routing can be used to maximize the utilization of routing resources (e.g., floorplans). The method described herein accurately models the resource estimates required for any-angle paths and supports automated any-angle routing. In addition, the method described herein provides a deterministic, universal repair solution for sharp angle violations between intersecting paths in a systematic manner.

[0032] This article describes the autorouting flow. The autorouting flow breaks down the complex InFO routing problem into multiple steps. It describes methods for accurate routing resource estimation for any angle path, pinout routing while respecting stacked via rules, crossover cost / length cost considerations during rough routing, sharp corner repair during detailed routing, and power / ground routing while respecting disjoint power / ground planes.

[0033] Conventional routing resource planning (global planning) involves partitioning the available routing area into a set of non-intersecting global routing cells (gcells) and analyzing the supply / demand at the boundaries of each gcell. Typical InFO designs have a high pin count and small space between adjacent pins, which can accommodate at most some minimum width routing traces. If the partitioning creates too many gcells, the size of the gcell may be too small to accommodate even one package routing trace. The method described in this article provides a way to avoid excessive destruction of routing resources relative to pins or obstacles and to reserve a large block of routing resources as one gcell. In the following, a gcell may also be referred to as a routing channel.

[0034] In one embodiment, after global planning, coarse routing is performed, which sequentially generates routes for two-pin nets. Crossover costs are introduced to make coarse routing less sensitive to the order in which the nets are routed. Coarse routing also takes into account user-defined constraints (e.g., length matching constraints). The output of coarse routing defines the exact topology of each two-pin connection relative to existing pins or obstacles (i.e., after coarse routing, determines the relative relationship of the connection to the left or right of the pin or obstacle).

[0035] In one embodiment, the detailed router can straighten the coarse routing results without violating the design rules. The detailed router described herein provides a general solution to fix sharp angles between two intersecting routing paths, which may occur in package routing and require a lot of manual effort to fix them by adding patches.

[0036] In one embodiment, power / ground plane awareness and power / ground routing are performed. The power / ground routing is optimized to the routing pattern of the corresponding power / ground plane and connects non-intersecting planes of the same net.

[0037] Figure 1 An InFO package routing flow 100 according to one embodiment of the present disclosure is depicted. The routing flow 100 outputs routing paths / vias that connect all nets and satisfy design rules and user constraints while minimizing the total wire length and via count of the InFO design, including bump sets, I / O pins, and macro pins.

[0038] At step 102, short wiring is generated between adjacent pins. Short wiring is performed before the wiring resource modeling. In other words, the short connection is connected before the wiring resource modeling. When two pins are directly adjacent on the same layer (i.e., there is no third pin between the two pins) and can be connected by a very short wire, the two pins are considered to be adjacent. When two pins overlap in x / y position (i.e., horizontal position or positioning in the layer) but are located on adjacent layers and can be connected by a via, the two pins are also considered to be adjacent.

[0039] At step 104, triangulation (e.g., Delaunay triangulation) is performed on the bump set, pins, and / or vias to construct a routing resource graph (i.e., a routing search graph). Triangulation is a technique used in package routing to divide the routing area into non-intersecting routing regions, each of which is a triangle. Triangulation takes a set of points as input and outputs a set of triangles such that the union of the triangles equals the routing area. The triangles do not overlap with each other except at the boundary where two adjacent triangles share a common edge. The method described herein minimizes the number of triangles created from the triangulation by modeling circular or nearly circular pin / via objects, which simplifies the global planning at step 108.

[0040] At step 106, a trial routing is performed to determine the primary routing layer for each two-pin net. Package routing is primarily single-layer routing. Limited routing on other layers may be added to reach source or target pins located on different layers. The trial routing is performed sequentially on the nets. The routing order of the nets may be based on the criticality of the nets. For example, a net with shielding / matching / timing constraints has a higher criticality and may be routed before other nets. The output of the trial routing assigns a routing layer (i.e., the primary routing layer) to each two-pin net.

[0041] At step 108, global planning is performed for each signal net, independent of the routing order of each routing layer. The routing capacity and routing cost due to congestion for all edges of the routing search graph are determined as described further below. The method described herein accurately determines the routing capacity of all edges of the routing search graph for any angle path routing, regardless of the presence of existing pre-routing.

[0042] At step 110, sequential coarse routing is performed on each two-pin net to identify all triangle edges where the two-pin net connections intersect. Pin-out routing is performed, which performs short routing from the pin layer to the designated routing layer established in step 106. The single-layer coarse router can perform a minimum cost search based on the routing search graph established in step 108. The coarse routing output has a deterministic topology for the existing pins / obstacles of each two-pin net.

[0043] At step 112, detailed routing is performed to straighten each roughly routed connection without violating the design rules. For each intersecting edge, the precise coordinates of the intersection point are determined, minimizing wire length while meeting the design rules. The roughly routed result may have unnecessary bends. Detailed routing straightens / tightens loose connections without violating the design rules.

[0044] At step 114, routing is performed on the power / ground nets to connect the power / ground pins to the nearest power / ground plane, or to connect two non-intersecting power / ground planes. The power / ground routing method described herein handles connections between non-intersecting power / ground planes, which, as described further below, are not handled by conventional package routers.

[0045] In one embodiment, as further described below, the routing is changed based on a determination that a constraint rule (eg, a sharp angle) is not satisfied. Additionally, routing information may be output, the routing information including the routing for the net.

[0046] It should be understood that Figure 1 Some of the steps in the flowcharts of FIG. 1 may be performed or executed in a different order or sequence than that shown and described in the figures. In addition, some of the steps may be executed much earlier than other steps, or may be performed or executed substantially simultaneously or in parallel. For example, step 106 and step 108 may be executed simultaneously.

[0047] Figure 2AThe actual layout shape of the bumps or pins in the InFO package design according to one embodiment of the present disclosure is depicted. In the InFO package design, the bumps or pins are usually circular (e.g., 202a, 202b, 202c) or close to circular (e.g., rectangular). Since the input of the triangulation is usually a set of points, each layout polygon is converted to a point before triangulation. Usually, the vertices of the polygon are selected as the input of the triangulation. Traditionally, circular bumps / pins are approximated by octagons. Constrained Delaunay triangulation (CDT) is performed on the vertices of the octagon to decompose the free routing area into many small triangles, such as Figure 2B As shown in .

[0048] Figure 2B The diagram depicts the use of octagons 204a, 204b, and 204c to approximate a circular shape. Executing CDT generates many small triangles between the three circular objects (e.g., 202a, 202b, and 202c). Each triangle (e.g., 208) is a gcell. The small triangles enable resource planning ( Figure 1 Step 108) is more difficult and less efficient because the small triangle may not even be able to accommodate one package routing trace. In a typical InFO package design with a high pin count and a small package size, the space between two adjacent pins can accommodate at most a pair of minimum width traces.

[0049] Figure 2C The use of center points to represent circular shapes according to one embodiment of the present disclosure is depicted. Circular shapes 202a, 202b, 202c are represented using the center points 206a, 206b, 206c of the circular shapes. CDT is performed on the center points. Performing CDT on the center points 206a, 206b, 206c results in a simpler triangulation. Triangle 210 is simpler than Figure 2B The triangles in (e.g., triangle 208) are much larger. Larger triangles are beneficial for global resource planning (e.g., in Figure 1 In other words, the routing area between the three circular objects is reserved as one gcell.

[0050] When determining the edge capacity of the routing resource graph, the effect on routing resources due to the size of the circular shape is taken into account, as described below.

[0051] (For example, in Figure 1 One of the goals of global planning (performed at step 108) is to establish a routing capacity value that determines the number of traces that can simultaneously cross the edges of a triangle without causing shorts or spacing violations for all triangles created at step 104. Each triangle generated at step 104 represents a routing channel.

[0052] Figure 3 A routing channel 300 according to one embodiment of the present disclosure is depicted. AD, BE, and CF are the heights of the corresponding bases of routing channel 300. Based on the pairs of intersecting edges, there are three possible ways to route through triangular channel 300. For each pair of edges, a channel capacity is determined. Three channel capacity numbers are associated with routing channel 300. For example, channel capacities are determined for the pairs AB and AC, BC and BA, and CA and CB.

[0053] In one embodiment, when the obstacles (objects A, B, C) have zero size, the following relationships hold true when the wiring is perpendicular to the high line: The capacity of the pair AB and AC is equal to the length of AD. The capacity of the pair BC and BA is equal to the length of BE. The capacity of the pair CA and CB is equal to the length of CF.

[0054] Figure 4 Depicts search graph nodes and edges according to one embodiment of the present disclosure. The wiring search graph nodes include (e.g., Figure 1 The midpoint of each triangle generated from the CDT at step 104 of FIG. 104 and including (e.g., Figure 1 The source / target nodes generated by CDT at step 104 of FIG. For the routing search graph 400, edge (v1, v2) represents a routing wire that enters routing channel 300 from edge AB and leaves the triangle at edge AC. Edge (v1, v3) represents a routing wire that enters routing channel 300 from edge AB and leaves routing channel 300 from edge BC. Edge (v2, v3) represents a routing wire that enters routing channel 300 from edge AC and leaves routing channel 300 from edge BC.

[0055] Figure 5 Capacity adjustment that takes into account obstacle size, according to one embodiment of the present disclosure, is depicted. Routing channel capacity is also determined as a function of obstacle size. Obstacle A is a circular object with a radius of C. Assuming A is a point, let C(R1) be the capacity of routing R1. Considering A is a circle, let C'(R1) be the actual capacity of R1. Therefore, C'(R1) = C(R1) - C(circle).

[0056] Figure 6 Capacity adjustment considering obstacle size according to one embodiment of the present disclosure is depicted. In one embodiment, C(circle A), C(circle B), and C(circle C) represent the radii of the circular obstacle shapes at vertices A, B, and C, respectively. Considering the sizes of obstacles A, B, and C, the actual capacity of R1 is C”(R1) = C(R1) - C(circle A) - max(C(circle B), C(circle C)), where C(R1) is the capacity of routing R1 when obstacles A, B, and C are single points.

[0057] In one embodiment, the InFO design may include existing wires / vias (ie, pre-routing). When the existing pre-routing cannot be moved or modified, the remaining channel capacity is determined based on the existing pre-routing in the triangular channel.

[0058] Figure 7 Capacity adjustment based on existing pre-routing according to one embodiment of the present disclosure is depicted. Schematic 700 shows pre-routing a-a' parallel to BC and b-b' (R2) parallel to AC. R1 and R2 represent routing that runs in different directions. R1 represents routing that intersects edges AB and AC. R2 represents routing that intersects edges AB and BC.

[0059] Let C(R1|R2) represent the remaining capacity of R1 in the presence of pre-wiring R2, then C(R1|R2)=C(R1)-F(R2), where C(R1) is the total capacity of R1 in the absence of R2, and F(R2) is the capacity reduced due to the presence of R2.

[0060] Figure 8 Capacity adjustment taking into account existing pre-wiring according to one embodiment of the present disclosure is depicted. Schematic 800 shows that the pre-wiring a-a' is parallel to BC, b-b' is parallel to AC, and c-c' is parallel to AB. R1 represents the wiring that crosses edges AB and AC. R2 represents the wiring that crosses edges AB and BC. R3 represents the wiring that crosses edges AC and BC. Let C(R1|{R2,R3}) be the remaining capacity of R1 in the presence of pre-wiring R2 and R3, then C(R1|{R2,R3})=C(R1)-max(F(R2),F(R3)), where C(R1) is the total capacity of R1 in the absence of R2 / R3, F(R2) is the capacity reduced due to the presence of R2, and F(R3) is the capacity reduced due to the presence of R3.

[0061] Rough wiring ( Figure 1 Step 110) includes Figure 1 The pin lead wiring and single layer wiring on the main wiring layer determined at step 106. The purpose of the pin lead wiring is to Figure 1 The two-pin net created in step 106 creates a short connection (i.e., a test route) from the pin to the main routing layer. The pin-out routing described herein takes into account the via stacking rules and any angle requirements to reach the specified layer of a specific net while optimizing the connection length.

[0062] Figure 9An example of pin-out routing according to one embodiment of the present disclosure is depicted. In one example, M3 pin A can be routed toward M1 pin B, as shown in 902. In one example, M3-M2 and M2-M1 have non-stacked via rules. Figure 1 Before performing general single-layer routing in step 110 (ie, rough routing), pin lead routing is first performed on pin A to lead it from M3 to M1.

[0063] In one embodiment, M3 may require a zigzag 45 degree non-stacked via, and M2 may require an arbitrary angle non-stacked via. For the lead-out from M3 to M2, since the rule may require a zigzag pattern, the pin-out router creates a 45 degree zigzag path toward pin B that is design rule check (DRC) compliant, and creates the M3-M2 via at A'. Note that if any shape has a DRC violation, the pin-out router creates other alternative zigzag paths with the shortest wire length. After the M3-M2 via is created as shown by 904, the pin-out router continues to create the lead-out path and vias toward pin B. The lead-out process is repeated from A' toward pin B, with the difference that M2 has an arbitrary angle rule instead of a zigzag 45 degree rule. Therefore, the router creates a straight path toward pin B and creates the M2-M1 via at A", and completes the pin-out process, as shown in 906.

[0064] Figure 10 A pin-out routing process 1000 is depicted according to one embodiment of the present disclosure. In one embodiment, the pin-out routing process is performed before the rough routing. The target layer is Figure 1 The designated layer of the two-stitch line net determined at step 106 in FIG.

[0065] At step 1002, the current shape is set as the starting stitch.

[0066] At step 1004 , it is determined whether the current shape is on the target layer. In response to determining that the current shape is on the target layer, the process ends. In response to determining that the current shape is not on the target layer, the process proceeds to step 1006 .

[0067] At step 1006 , it is determined whether the starting stitch can be stacked. In response to determining that the starting stitch can be stacked, the process proceeds to step 1014 . In response to determining that the stitch cannot be stacked, the process proceeds to step 1008 .

[0068] At step 1008 , the extraction path with the shortest wire length is selected.

[0069] At step 1014 , a via is created at the center of the current shape.

[0070] At step 1010 , a DRC (Design Rule Check) check is performed. In response to determining that the DRC is compliant, the process proceeds to step 1012 . In response to determining that the DRC is not compliant, the process returns to step 1018 .

[0071] At step 1012 , a via is created at the end of the lead path pattern. The process then proceeds to step 1016 . At step 1016 , the current shape is set to a via. The process then returns to step 1004 .

[0072] Single-layer coarse wiring is coarse wiring (i.e., Figure 1 The second step in step 110 in FIG. 4 is to prevent crossover between connections from different nets routed on the same layer. The coarse routing described herein has built-in crossover and length costs to optimize the overall routing pattern under length matching and shielding constraints.

[0073] The coarse router is a cost-based router that Figure 4 The search graph described in

[15] searches from the source node to the target node. Each search graph edge has its initial capacity, which is determined by Figure 6 This initial capacity is calculated using the equation described in , or when there is existing pre-wiring, Figure 7 and Figure 8 The initial capacity is calculated as described in

[15] . Nets are routed by searching for graph edges. The routing spacing of the nets increases the demand on the search graph edges. Coarse routing can route all nets one by one in sequence. The following costs are taken into account: estimated routing wire length, estimated wire length required from the current point to the target, detours, overflows, crossings and length matching. Shielding constraints add additional demand calculated by shield settings (such as gaps, spacing, etc.), which can be modeled by overflow costs.

[0074] The cost includes the crossing cost and the length matching cost. The crossing between two nets is detected by checking the wiring order recorded on the search graph nodes.

[0075] Figure 11 An example of intersection detection according to one embodiment of the present disclosure is depicted. In one example, net A is routed first, as shown in diagram 1102. When net B is routed to node 1 through search graph node 3, the coarse router checks the current and previous triangulation mesh search graph nodes (i.e., nodes 1 to 5) to determine if the current routing will result in an intersection with a previously routed net. In diagram 1104, since each search graph node records the order of routed nets, checking search graph nodes 1 to 5 can detect that net B intersects net A. When an intersection is detected, the intersection is modeled as a cost.

[0076] The length matching cost is modeled by calculating the difference between the current estimated wire length and the target wire length at a given search graph node. In one example, two nets A and B have length matching constraints. Net A has a pin-to-pin distance of 10, and Net B has a pin-to-pin distance of 5. Net B then has a target wire length of 10. When determining the cost for the search graph node for Net B, the coarse router can first calculate the estimated wire length L for Net B, from the source node through the current node to the target node. The coarse router can then calculate the absolute difference between L and the pin-to-pin distance of Net A as the cost.

[0077] A sharp angle between two intersecting paths is generally considered a design rule violation in package routing. A sharp angle is an angle greater than 0° but less than 90°. Sharp angles may be generated in detailed routing (e.g., Figure 1 112 in step 114). This paper describes a two-stage sharp corner repair heuristic that removes sharp corners from routing while satisfying minimum segment length or spacing rules.

[0078] Figure 12 An example of repairing an acute angle in the middle of a connection according to one embodiment of the present disclosure is depicted. During detailed routing, an acute angle ∠ABC is generated in the middle of the connection. The acute angle can be repaired by adding a third line segment B1-B2. The length of B-B1 is equal to the length of B-B2. In addition, the length of the third line segment B1-B2 is not less than the minimum process pitch or the minimum process line segment length. The newly formed path A-B1-B2-C has no acute angles. Angle BB1B2 and angle BB2B1 are both acute angles. Therefore, angle CB2B1 = angle AB1B2 = 180° - angle BB1B2 > 90°.

[0079] Figure 13 The repair of a sharp angle occurring at the beginning or end of a connection according to one embodiment of the present disclosure is depicted. It is assumed that CD is a pre-existing line segment and cannot be modified. A new connection AB is being generated. Connection AB intersects CD at point B. In one example, the resulting angle ABD is an acute angle. The acute angle can be repaired by adding a series of adjacent repair segments B1B1', B2B2', B3B3', etc., such that length (BBi) = length (BBi') (i = 1, 2, 3...). The repair process stops when the last segment BiBi' has a length BiBi' that is not less than the minimum process spacing or the minimum process segment length.

[0080] This article describes a power / ground plane-aware power / ground router that optimizes power / ground routing patterns to achieve short connections directly to planes and to connect non-intersecting planes of the same net using heuristics.

[0081] Figure 14An example of power / ground routing according to one embodiment of the present disclosure is depicted. In one example, a design may require two power planes for a power domain, an M1 plane guide 1402 and an M2 plane guide 1404. The M2 power pins are in the M1 plane guide 1402, and the M3 power pins are in the M2 plane guide 1404.

[0082] The power / ground router can be used first Figure 10 The pin-out routing method shown and described in , routes the power pins individually to the nearest plane. The router can then identify the pins to use as sources and can create virtual pins as targets connecting non-intersecting planes. Routing from source to target uses the same routing techniques as described in coarse routing (i.e., Figure 1 110 in step 110).

[0083] Figure 15 An example set 1500 of processes used during the design, verification, and manufacture of an article of manufacture, such as an integrated circuit, is illustrated for converting and verifying design data and instructions representing the integrated circuit. Each of these processes can be structured and implemented as multiple modules or operations. The term 'EDA' stands for the term 'electronic design automation'. These processes begin with creating a product concept 1510 using information provided by a designer, which is converted to produce an article of manufacture using a set of EDA processes 1512. When the design is completed, the design is taped out 1534, which is when the artwork (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to produce a mask set, which is then used to manufacture the integrated circuit. After tapeout, the semiconductor die is manufactured 1536, and packaging and assembly processes 1538 are performed to produce the finished integrated circuit 1540.

[0084] The specification of a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. Circuits and systems can be designed using a high level of abstraction using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL or OpenVera. The HDL description can be converted to a register transfer level ('RTL') description at the logic level, a gate level description, a layout level description or a mask level description. Each lower level of abstraction (i.e. less abstract description) adds more useful detail to the design description, for example more detail for the modules that comprise the description. The lower levels of abstraction (i.e. less abstract descriptions) may be computer generated, derived from a design library or created by another design automation process. An example of a specification language for a lower level of abstraction language that specifies more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is implemented for use by the corresponding tools for that layer (e.g. formal verification tools). The design process may use Figure 15 The sequence described in . The described process is implemented by EDA products (or tools).

[0085] During system design 1514, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0086] During logic design and functional verification 1516, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of a circuit can be verified to generate outputs that match the requirements of the specifications of the circuit or system being designed. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, specialized systems of components called "emulators" or "prototyping systems" are used to accelerate functional verification.

[0087] During synthesis and design for testing 1518, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit operates according to the specified design during manufacturing. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that the integrated circuit meets the specifications.

[0088] During netlist verification 1520, the netlist is checked for consistency with timing constraints and correspondence with HDL code. During design planning 1522, the overall floorplan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0089] During layout or physical implementation 1524, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components through multiple conductors) are performed, and selection of cells from a library to implement specific logic functions can be performed. As used herein, the term "cell" can specify a group of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are implemented as physical structures and in simulation. Parameters, such as size, are specified for the selected cells (based on "standard cells"), and the parameters are made accessible in a database for use by EDA products.

[0090] During analysis and extraction 1526, circuit functionality is verified at the layout level, which allows for refinement of the layout design. During physical verification 1528, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, and lithography constraints, are correct, and that the circuit functionality matches the HDL design specifications. During resolution enhancement 1530, the layout geometry is transformed to improve the fabrication of the circuit design.

[0091] During tape-out, data is created for the production of lithographic masks (after applying lithographic enhancements where appropriate).During mask data preparation 1532, the "tape-out" data is used to produce lithographic masks, which are used to produce finished integrated circuits.

[0092] Computer systems (such as Figure 16 The storage subsystem of the computer system 1600) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and physical and logical design products that use the libraries.

[0093] Figure 16 An example computer system 1600 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0094] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is shown, the term "machine" should also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0095] The example computer system 1600 includes a processing device 1602, a main memory 1604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 1606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1618, which communicate with each other via a bus 1630.

[0096] The processing device 1602 represents one or more processors, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1602 may be configured to execute instructions 1626 for performing the operations and steps described herein.

[0097] The computer system 1600 may also include a network interface device 1608 for communicating over a network 1620. The computer system 1600 may also include a video display unit 1610 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1612 (e.g., a keyboard), a cursor control device 1614 (e.g., a mouse), a graphics processing unit 1622, a signal generating device 1616 (e.g., a speaker), the graphics processing unit 1622, a video processing unit 1628, and an audio processing unit 1632.

[0098] The data storage device 1618 may include a machine-readable storage medium 1624 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1626 or software embodying any one or more of the methodologies or functionality described herein. The instructions 1626 may also reside, completely or at least partially, within the main memory 1604 and / or within the processing device 1602 during execution by the computer system 1600, with the main memory 1604 and the processing device 1602 also constituting machine-readable storage media.

[0099] In some implementations, the instructions 1626 include instructions for implementing functionality corresponding to the present disclosure. Although the machine-readable storage medium 1624 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine and processing device 1602 to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0100] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0101] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise stated, as will be apparent from this disclosure, it should be understood that throughout this specification certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0102] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or the apparatus may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0103] The algorithms and displays proposed herein are not inherently related to any particular computer or other device. Various other systems can be used together with the programs taught herein, or it may prove convenient to construct more specialized equipment to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0104] The present disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0105] In the foregoing disclosure, implementations of the present disclosure have been described with reference to specific example implementations thereof. It is apparent that various modifications may be made to these implementations without departing from the scope and broad spirit of the embodiments of the present disclosure as set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and identical elements are marked with the same numerals. Therefore, the present disclosure and the accompanying drawings should be considered in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: performing triangulation on the set of nets by one or more processing devices to generate a routing resource graph, wherein during the triangulation, objects of the set of nets are represented by corresponding center points; generating, by the one or more processing devices, routing between the objects of the set of wire nets based at least on a total cost, wherein the total cost is determined based at least on the routing resource map, wherein generating the routing further comprises determining a pin lead-out routing from the object to a routing layer based on a via stacking rule and an angle requirement, and wherein generating the pin lead-out routing comprises selecting a lead-out path with a shortest wire length when the object cannot be stacked, and wherein the lead-out path has an arbitrary angle rule; changing, by the one or more processing devices, the routing based on a determination that a constraint rule is not satisfied; as well as Routing information is outputted by the one or more processing devices, the routing information including the routing for the set of nets.

2. The method according to claim 1, further comprising: Before performing the triangulation, a short wiring is generated between a first object and a second object, the first object and the second object being adjacent on a layer, or the first object and the second object having the same horizontal position on two adjacent layers.

3. The method of claim 1 , wherein determining the pin-out routing comprises: associating the current shape with said object; When the objects can be stacked based on the via stacking rule, creating a via at the center of the current shape; as well as When the object cannot be stacked based on the via stacking rule, an extraction path is generated and a second via is created at an end of the extraction path. The method according to claim 1 , wherein the total cost comprises a crossover cost and a length matching cost.

5. The method according to claim 4, further comprising: Performing a check on the routing resource graph to determine whether a current routing intersects with a routed net; as well as When the current route crosses the routed net, the crossing is modeled as the crossing cost.

6. The method according to claim 4, further comprising: The length matching cost is determined from a difference between an estimated wire length and a target wire length for the routing resource map. The method of claim 1 , wherein generating a route is based on the total cost and a route capacity. The method of claim 7 , wherein the routing capacity is based on obstacle size and pre-routing.

9. The method of claim 1, wherein changing the wiring further comprises: determining whether an angle between a first line segment and a second line segment violates a design rule, the first line segment and the second line segment being continuous on a route between the objects; as well as A third line segment is inserted between the first line segment and the second line segment, wherein a length of the third line segment satisfies a minimum line segment length of the design rule.

10. The method of claim 1, wherein changing the wiring further comprises: determining whether an angle between an existing connection and a connection generated by the routing violates a design rule; said angle being at a distal end of said connection; as well as When the angle violates the design rule, one or more repair line segments are added.

11. The method according to claim 1, further comprising: Perform power / ground routing by bringing the power pins out to the plane; as well as Disjoint planes are connected by connecting the power pins to dummy pins.

12. A system comprising: Memory, which stores instructions; as well as a processor coupled to the memory and executing the instructions, which when executed cause the processor to: Performing triangulation on the set of nets to generate a routing resource graph, wherein during the triangulation, objects of the set of nets are represented by corresponding center points; generating routing between the objects of the set of nets based at least on a total cost, wherein the total cost is determined based at least on the routing resource map, wherein generating the routing further comprises determining a pin lead-out routing from the object to a routing layer based on a via stacking rule and an angle requirement, and wherein generating the pin lead-out routing comprises selecting a lead-out path with a shortest wire length when the object cannot be stacked, and wherein the lead-out path has an arbitrary angle rule; Based on a determination that the constraint rule is not satisfied, changing the routing; as well as Outputting routing information, wherein the routing information includes the routing for the net set.

13. The system of claim 12, wherein the processor is further configured to perform operations comprising: Before performing the triangulation, a short wiring is generated between a first object and a second object, the first object and the second object being adjacent on a layer, or the first object and the second object having the same horizontal position on two adjacent layers.

14. The system of claim 12, wherein determining the pin-out routing comprises: associating the current shape with said object; When the objects can be stacked based on the via stacking rule, creating a via at the center of the current shape; as well as When the object cannot be stacked based on the via stacking rule, an extraction path is generated and a second via is created at an end of the extraction path.

15. The system of claim 12, wherein the total cost comprises a crossing cost and a length matching cost.

16. The system of claim 15, wherein the processor is further configured to perform operations comprising: Performing a check on the routing resource graph to determine whether a current routing crosses an already routed net; and When the current route crosses the routed net, the crossing is modeled as the crossing cost.

17. The system of claim 15, wherein the processor is further configured to perform operations comprising: A difference between an estimated wire length and a target wire length for the routing resource map is determined.

18. A non-transitory computer readable medium comprising stored instructions which, when executed by a processor, cause the processor to: Performing triangulation on the set of nets to generate a routing resource graph, wherein during the triangulation, objects of the set of nets are represented by corresponding center points; generating routing between the objects of the set of nets based at least on a total cost, wherein the total cost is determined based at least on the routing resource map, wherein generating the routing further comprises determining a pin lead-out routing from the object to a routing layer based on a via stacking rule and an angle requirement, and wherein generating the pin lead-out routing comprises selecting a lead-out path with a shortest wire length when the object cannot be stacked, and wherein the lead-out path has an arbitrary angle rule; Based on a determination that the constraint rule is not satisfied, changing the routing; as well as Outputting routing information, wherein the routing information includes the routing for the net set.

Images