A debugging method and device for tracing a heterogeneous multi-core processor system

Abstract

A debugging method and device for tracing a heterogeneous multi-core processor system, the method comprising the following steps: step S1: register preconfiguration; step S2: running the program; step S3: recording the current PC value of the i-th specified program segment as PC_Value i ; If PC_Value i &Trig_MaskReg i ==Trig_Reg i , called a PC trigger of the i-th specified program segment, and then proceed to step S4; Step S4: trigger a write operation to TraceBuffer; each write content is a TraceItem, which is compressed and written to TraceBuffer; record the number of triggers CNT i ; Step S5: If CNT i ==End_Reg i , then terminate the PC trigger operation of the i-th designated program segment, and proceed to step S6; Step S6: All designated program segment PC triggers have been recorded, then proceed to step S7; Step S7: The parsing software running on the debugging host reads the TraceBuffer content through the simulator to parse the program running control flow. The device is used to implement the above method. The present invention has the advantages of simple principle, simple operation, and improved accuracy and efficiency.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of microprocessor verification and debugging, and in particular to a debugging method and device for tracing a heterogeneous multi-core processor system. Background Art

[0002] With the rapid development of chip technology, the integration of embedded microprocessors is getting higher and higher. The complexity of the system on chip (SoC) based on microprocessors for solving various tasks is also increasing. The verifiability and debuggability of the system are becoming more and more important. During functional verification, if it is inconsistent with the design, debugging is required to detect and correct errors. The high complexity of SoC makes debugging difficult. How to complete embedded debugging tasks simply and efficiently is of great significance to the design and development of embedded microprocessor systems.

[0003] The field of microprocessor verification and debugging has gone through several stages of development. Currently, academic and engineering fields focus on non-intrusive debugging, that is, debugging technology based on tracing. This debugging method is implemented using a system-on-chip, which records the program control flow in real time, allowing programmers to record the information of interest in a shared memory (shared RAM). During the debugging process, programmers can read this information and analyze the multi-core real-time running data and events of the processor through software tools.

[0004] When implementing non-intrusive debugging, the specific design of the tracing process and the tracing structure restricts the on-chip tracing system, and the existing technology has also studied the tracing process and structure.

[0005] Some practitioners have proposed a method and system for a multi-layer tracing architecture (Chinese patent application 201310734379.4), which divides the original tracing information into high-bandwidth tracing information and low-bandwidth tracing information, which are provided to the on-chip buffer trigger and the off-chip tracing interface respectively. The low-bandwidth tracing information is provided in parallel to the off-chip tracing interface, which means that the on-chip tracing system needs to implement the write function to the off-chip storage in real time. If the tracing information is mostly low-bandwidth, the overall resource utilization will decrease instead of increase.

[0006] Or by cascading multiple tracking modules in the chip (Chinese patent application 201711403774.9), the storage space for debugging a single module can be expanded to improve utilization. However, this invention does not take into account the overall resource limitations in actual engineering, and a single chip only integrates a single tracking module. In addition, if a multi-core system that performs multiple tasks is tracked, the cascading of multiple modules will make it impossible to determine which specific task the tracked data belongs to.

[0007] To achieve system behavior visibility, another researcher proposed a bus tracking method to monitor all information transmitted by AHB and constructed a 96-bit loop tracking memory. This study did not take into account that in the actual debugging process, only focusing on specific instruction behavior, recording all information will cause serious resource waste, and the loop memory has nonlinear security.

[0008] Some people have also proposed a method and apparatus for triggering and tracking system-on-chip structure transactions in a primary adjustable structure (Chinese patent application 201410160222.x), in which the structure tracking hook in the test system monitors the predetermined point-to-point transactions of the agent, and the transactions to be monitored are determined by the mask / trigger register. This method is based on the Intel IOSF and IntelPSF specifications, tracks the specific behavior of the transaction, and realizes full data capture. For non-complex systems, this method is cumbersome and not universal. In the actual tracking process, you may only care about whether the behavior is executed rather than how it is executed.

[0009] In general, existing research focuses on two aspects: trace buffer efficiency and trace signal selection. In practical projects, the trace module resources that can be synthesized into FPGA are limited. Summary of the invention

[0010] The technical problem to be solved by the present invention is: in view of the technical problems existing in the prior art, the present invention provides a debugging method and device for tracing a heterogeneous multi-core processor system which has a simple principle, is easy to operate, and can improve accuracy and efficiency.

[0011] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0012] A debugging method for tracing a heterogeneous multi-core processor system, the steps of which include:

[0013] Step S1: register pre-configuration;

[0014] Step S2: running the program;

[0015] Step S3: Record the current PC value of the i-th specified program segment as PC_Value i ; If PC_Value i &Trig_MaskReg i ==Trig_Reg i , which is called a PC trigger of the i-th specified program segment, and the execution proceeds to step S4, otherwise it proceeds to step S2;

[0016] Step S4: trigger a write operation to TraceBuffer; each write content is a TraceItem, whose format is coreID+PCTrigID+TimeStamp, which is compressed and written to TraceBuffer; record the triggering number CNT i ;

[0017] Step S5: If CNT i ==End_Reg i , then terminate the PC trigger operation of the i-th specified program segment and proceed to step S6, otherwise proceed to step S2;

[0018] Step S6: If all the PC triggers of the designated program segments have been recorded, the process proceeds to step S7, otherwise the process proceeds to step S2;

[0019] Step S7: The parsing software running on the debugging host reads the TraceBuffer content through the simulator and parses the control flow of the program execution.

[0020] As a further improvement of the debugging method of the present invention: when executing step S3, a shared PC stream mode is adopted to determine whether the current PC needs to be tracked according to the pre-configuration of the control register; that is, PC_Value and Trig_MaskReg i The bitwise AND operation is performed and the result is equal to Trig_Reg i The comparator determines whether they are equal, if they are equal, it is 1, otherwise it is 0; in each core, the logical calculations of each pair of Trig_Reg and Trig_MaskReg are independent and performed synchronously.

[0021] As a further improvement of the debugging method of the present invention: the step S4 comprises:

[0022] Step S401: trigger a write operation to TraceBuffer; monitor TraceBuffer in real time, and when it is not full, trigger the write operation to TraceBuffer normally; when it is full, determine the next execution process by the value of TB_Cfg_Reg, if TB_Cfg_Reg is 0, perform the "wrap overwrite" operation, and write to TraceBuffer cyclically; in the later analysis, determine the sequence of TraceItem according to the timestamp; if TB_Cfg_Reg is 1, perform the "pause and wait" operation, the program is paused, and the content of TraceBuffer is read out. When the reading and writing are completed, continue to run the program, and execute the tracking and debugging of each program segment;

[0023] Step S402: Record the trigger count CNT; record the trigger count in each core by category, recorded as CNT i, a pair of logic judgments of Trig_Reg and Trig_MaskReg is a type of trigger.

[0024] As a further improvement of the debugging method of the present invention: in step S5, the triggering number CNT is input i and End_Reg i When the comparator output is 1, the i-th PC type trigger operation is terminated, and no other tracking process will be executed for this type of situation.

[0025] As a further improvement of the debugging method of the present invention: in the step S1, when the register is pre-configured, Trig_Reg and Trig_MaskReg are set according to the instruction; according to the mask rule, when Trig_MaskReg is "0xFFFFFFFF", only the execution of the instruction is tracked, and Trig_Reg is the PC value of the instruction of concern at this time; if the adjacent segment of the specified instruction is concerned, the relevant bit of Trig_MaskReg is set to zero, the corresponding bit of Trig_Reg is set to zero, and the remaining bits are consistent with the PC value of the instruction; TB_Cfg_Reg is set to "0" or "1" as required to implement different functions.

[0026] The present invention further provides a debugging device for tracing a heterogeneous multi-core processor system, which comprises:

[0027] Timestamp module, used to record the running time of a specific program segment;

[0028] Control register module, each processor core contains Trig_Reg and Trig_MaskReg, which are used to determine whether to trigger the write operation to TraceBuffer; it contains the end control register End_Reg, which is used to determine whether to end the trigger; each Trig_Reg and its corresponding Trig_MaskReg and End_Reg form a trigger register group Trig_Reg_Group, and a Trig_Reg_Group controls the complete Trace behavior of a specified program segment, including whether the current PC generates a trigger and whether to end the Trace process of the program segment;

[0029] Control processing module, used to complete counting comparison function and data compression function;

[0030] The trace buffer module is used to correctly store TraceItem throughout the trace process.

[0031] As a further improvement of the debugging device of the present invention: the timestamp module includes a timestamp frequency division register and a timestamp counter; the input clock of the timestamp module is the processor main clock, and the main clock is passed through the timestamp frequency division register to obtain a timestamp clock after division; the timestamp counter is driven by the timestamp clock, and the output is a timestamp.

[0032] As a further improvement of the debugging device of the present invention: the trace buffer module includes a TraceBuffer storage unit and a monitoring control unit, TraceItem is written into the TraceBuffer storage unit via a private buffer, connected to the Trace bus, and output to the outside of the chip; the monitoring control unit monitors in real time whether the TraceBuffer is full, and if it is full, the control specifically executes "wrap overwrite" or "pause and wait".

[0033] As a further improvement of the debugging device of the present invention: the control processing module includes a counting comparison unit and a data compression unit, the control register module sends the pre-configuration information to the counting comparison unit, and obtains the current PC value from the bus; the data compression unit is used to complete the generation and compression of TraceItem.

[0034] As a further improvement of the debugging device of the present invention: the counting and comparison unit is used to record the triggering times of a specific PC of a specified program segment in each core, and compare it with the end control register set before the program is executed; the data compression unit is used to splice the specified PC-Trace data into TraceItem in a fixed format, and send it to TraceBuffer after compression.

[0035] As a further improvement of the debugging device of the present invention: the counting and comparing unit outputs two pieces of information and sends them to the data compression unit: one is CNT i ==End_Reg i The comparison result is used to decide whether to continue the trigger operation; the second is PCTrigID, which is used by the data compression unit to generate TraceItem.

[0036] Compared with the prior art, the advantages of the present invention are:

[0037] 1. The debugging method and device for tracing heterogeneous multi-core processor systems of the present invention can realize online real-time debugging of multi-core microprocessors, and can improve accuracy and efficiency; the present invention allows programmers to record the running time (timestamp) of multiple specified program segments (program pointer (PC) addresses) in a shared memory (shared RAM) through precise control register bit settings. During the debugging process, programmers can read this information and obtain the multi-core real-time running data and events of the processor through software tool analysis. The present invention allows programmers to obtain the real-time execution information of the entire multi-core processor non-invasively, thereby improving verification and debugging efficiency.

[0038] 2. The debugging method and device for tracing a heterogeneous multi-core processor system of the present invention are provided with 16 Trig_Reg_Groups in each processor core, which can realize the tracing of 16 specified program segments at the same time; the tracing function is expanded by using the trigger mask register Trig_MaskReg, and the mask rule is adopted to mask some bits of the current PC value (PC_Value), and in conjunction with the trigger register Trig_Reg, the tracing of the adjacent segments of the specified PC can be realized, which is convenient for the later analysis of the specific situation before and after the execution of the instruction.

[0039] 3. The debugging method and device for tracing a heterogeneous multi-core processor system of the present invention provides a private buffer unit for each TraceItem class, and uses a monitoring control unit to monitor TraceBuffer, thereby ensuring the data integrity before and after entering TraceBuffer.

[0040] 4. The heterogeneous multi-core processor system tracking debugging method and device of the present invention is concerned with the instruction execution process, and the sequence of program pointer (PC) addresses determines the specific behavior of the instructions. The present invention is an on-chip tracking debugging method and structure that accurately and efficiently realizes real-time recording of multi-core system program control flow. Through precise control register bit settings, it allows programmers to record the running time (timestamp) of multiple specified program segments (PC) in a shared memory for later analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a flow chart of the debugging method of the present invention in a specific application example.

[0042] Figure 2 It is a schematic diagram of the topological structure principle of the debugging device of the present invention in a specific application example.

[0043] Figure 3 It is a schematic diagram of the structural principle of the time stamp module of the debugging device of the present invention in a specific application example.

[0044] Figure 4It is a schematic diagram of the structural principle of a tracking buffer module of the debugging device of the present invention in a specific application example.

[0045] Figure 5 It is a schematic diagram of the structural principle of the control processing module of the debugging device of the present invention in a specific application example. DETAILED DESCRIPTION

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] like Figure 1 As shown, a debugging method for tracing a heterogeneous multi-core processor system of the present invention comprises the following steps:

[0048] Step S1: register pre-configuration;

[0049] Before running the program, configure the trigger register (Trig_Reg), trigger mask register (Trig_MaskReg), and end control register (End_Reg) in the IDE.

[0050] Step S2: running the program;

[0051] Step S3: Record the current PC value of the i-th specified program segment as PC_Value i , if PC_Value i &Trig_MaskReg i ==Trig_Reg i , which is called a PC trigger of the i-th specified program segment, and the execution proceeds to step S4, otherwise it proceeds to step S2;

[0052] Step S4: trigger a write operation to TraceBuffer;

[0053] In the specific application example, each write content is a TraceItem, whose format is coreID+PCTrigID+TimeStamp, which is compressed and written to TraceBuffer; the trigger count CNT is recorded. i ;

[0054] Step S5: If CNT i ==End_Reg i , then terminate the PC trigger operation of the i-th specified program segment and proceed to step S6, otherwise proceed to step S2;

[0055] Step S6: If all the PC triggers of the designated program segments have been recorded, the process proceeds to step S7, otherwise the process proceeds to step S2;

[0056] Step S7: The parsing software running on the debugging host reads the TraceBuffer content through the simulator and analyzes the program source code to implement the parsing of the program running control flow.

[0057] In a specific application example, in step S1, when registers are preconfigured, Trig_Reg and Trig_MaskReg are set according to the instruction of interest. According to the mask rule, when Trig_MaskReg is "0xFFFFFFFF", only the execution of the instruction is tracked, and Trig_Reg is the PC value of the instruction of interest; if the adjacent segment of the specified instruction is concerned, the relevant bit of Trig_MaskReg needs to be set to zero, the corresponding bit of Trig_Reg is set to zero, and the remaining bits are consistent with the PC value of the instruction. TB_Cfg_Reg is set to "0" or "1" according to requirements to achieve different functions.

[0058] In a specific application example, in step S2, the program is allowed to receive an interrupt signal to interrupt the execution of the program.

[0059] In a specific application example, each register and TraceBuffer can be accessed by a processor core program and can also be accessed by an ET (Emulation / Test) unit.

[0060] In a specific application example, the PC stream is shared. When executing step S3, it is determined whether the current PC needs to be tracked according to the pre-configuration of the control register. The specific process can be: first, PC_Value and Trig_MaskReg i The bitwise AND operation is performed and the result is equal to Trig_Reg i The comparator determines whether they are equal, if they are equal, it is 1, otherwise it is 0; in each core of this step, the logic calculations of each pair of Trig_Reg and Trig_MaskReg are independent of each other, do not interfere with each other, and can be performed synchronously.

[0061] As a preferred embodiment, in step S4, the present invention further pre-configures the TraceBuffer configuration register (TB_Cfg_Reg) before the program runs to monitor the TraceBuffer. When the TraceBuffer is full, the configuration register controls whether to "wrap around" or "pause and wait". The "wrap around" operation does not clear the buffer, and adopts a circular write mode. In the later analysis, the TimeStamp is used to identify the order of data; "pause and wait" forces the program to pause, and after all the TraceBuffer data is written off-chip, the program execution continues.

[0062] In a specific application example, the process of step S4 includes:

[0063] Step S401: trigger a write operation to TraceBuffer. This process requires real-time monitoring of TraceBuffer. When it is not full, the write operation to TraceBuffer is triggered normally. When it is full, the next execution process is determined by the value of TB_Cfg_Reg. If TB_Cfg_Reg is 0, the "wrap overwrite" operation is performed to write to TraceBuffer in a loop. In the later analysis, the sequence of TraceItem is determined according to the timestamp. If TB_Cfg_Reg is 1, the "pause and wait" operation is performed, the program is paused, and the contents of TraceBuffer are read out. When the reading and writing are completed, the program continues to run and the tracking and debugging of each program segment is executed.

[0064] Step S402: Record the trigger count CNT. This process records the trigger counts in each core by category, recorded as CNT i , the logic judgment of a pair of Trig_Reg and Trig_MaskReg is a type of trigger, and there are a maximum of 16 types of trigger conditions in each core.

[0065] In a specific application example, in step S5, the triggering number CNT is input. i and End_Reg i When the comparator output is 1, the i-th PC type trigger operation is terminated, and no other tracking process will be executed for this type of situation.

[0066] like Figure 2 As shown, the present invention further includes a debugging device for tracing a heterogeneous multi-core processor system, comprising:

[0067] The timestamp module (TimeStamp) is used to record the running time of a specific program segment;

[0068] Control register module, each processor core contains 16 32-bit Trig_Reg and 16 corresponding 32-bit Trig_MaskReg, which are used to determine whether to trigger the write operation to TraceBuffer. PCTrig_Reg is numbered 0-15, recorded as PCTrigID (4 bits); it contains 16 32-bit end control registers (End_Reg) to determine whether to end the trigger; the module must be configured before the program starts. Each Trig_Reg and its corresponding Trig_MaskReg and End_Reg form a trigger register group (Trig_Reg_Group). A Trig_Reg_Group controls the complete Trace behavior of a specified program segment, including whether the current PC generates a trigger and whether to end the Trace process of the program segment.

[0069] Control processing module, used to complete counting comparison function and data compression function;

[0070] The trace buffer module is used to correctly store TraceItem throughout the trace process.

[0071] As a further improvement of the structure of the present invention: after the PC trigger operation of the i-th designated program segment is terminated, no logical operation will be performed with the i-th register group to reduce resource and time overhead.

[0072] For specific application examples, see Figure 3 The timestamp module includes a timestamp frequency division register with a bit width of 48 bits and a timestamp counter with a bit width of 24 bits. The input clock of the timestamp module is the processor main clock, and the main clock is divided by the timestamp frequency division register to obtain the timestamp clock; the timestamp counter is driven by the timestamp clock and outputs the timestamp. The module supports trace monitoring at the scale of "days". The timestamp counter is maintained by the chip's unique time system module, and the input is the output clock of the timestamp frequency division register.

[0073] See also Figure 4 In a specific application example, the trace buffer module includes a TraceBuffer storage unit and a monitoring control unit. TraceItem is written into the TraceBuffer storage unit via a private buffer, connected to the Trace bus, and output to the outside of the chip. The monitoring control unit monitors in real time whether the TraceBuffer is full. If it is full, TB_Cfg_Reg[0] controls the specific execution of "wrap overwrite" or "pause and wait". Among them:

[0074] TraceBuffer storage unit, a shared TraceBuffer is set in the whole chip. It is a multi-port memory with a depth of K rows (depending on the processor area) and a width of M bits, which is used to store TraceItem;

[0075] The monitoring control unit sets a 32-bit TraceBuffer configuration register (TB_Cfg_Reg) to monitor in real time whether the TraceBuffer is full; if it is full, a "wrap-over" operation is performed when TB_Cfg_Reg

[31] ==0, and a "pause-wait" operation is performed when TB_Cfg_Reg

[31] ==1. It can be understood that in other embodiments, the register can also be expanded to other functions.

[0076] Furthermore, in a preferred embodiment, in order to avoid data loss when multiple events write to TraceBuffer at the same time, the TraceBuffer storage unit also includes a private buffer unit, and the TraceItem of each event corresponds to its own private buffer.

[0077] Further, in a preferred embodiment, in the TraceBuffer storage unit, in order to ensure the data integrity after the TraceItem is written, the "full" state in the TraceBuffer storage unit of the present invention is a "not completely full" state, and the TraceBuffer storage unit adopts a reserved space (RS), the size of which is determined according to the actual situation and determined by TB_Cfg_Reg; when a given threshold (Nth) is reached, TB_Cfg_Reg controls the next operation, and at this time, the TraceItem can continue to be written to the reserved space; in an actual processor system, the monitoring and control unit monitors the TraceBuffer, generates relevant control instructions and transmits them to the corresponding position, which has a certain time overhead. If the module is "completely full", data loss will occur during this period; TB_Cfg_Reg specifies the TraceBuffer reserved space size NRS when writing TraceItem, and the space size is equal to the TraceBuffer size minus the threshold, that is, NRS=NTB-Nth.

[0078] See also Figure 5 In a specific application example, the control processing module includes a counting comparison unit and a data compression unit. The control register module sends the pre-configured information to the counting comparison unit and obtains the current PC value from the bus. The counting comparison unit outputs two pieces of information and sends them to the data compression unit: one is CNT i ==End_Reg i The comparison result (0 / 1) is used to decide whether to continue the trigger operation; the second is PCTrigID, a total of 4 bits, which is used by the data compression unit to generate TraceItem. The data compression unit is used to complete the generation and compression of TraceItem. In this example, the TraceItem format is coreID+PCTrigID+TimeStamp, where coreID is determined by the core where the executed instruction is located, PCTrigID is provided by the counting comparison unit, and TimeStamp is provided by the timestamp module. Among them:

[0079] The counting and comparison unit is used to record the number of times a specific PC of a specified program segment in each core is triggered and compare it with the end control register set before program execution;

[0080] The data compression unit is used to splice the specified PC-Trace data into TraceItem according to a fixed format, and send it to TraceBuffer after compression.

[0081] The above are only preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A debugging method for tracing a heterogeneous multi-core processor system, characterized in that the steps include: Step S1: register pre-configuration; Step S2: running the program; Step S3: Record the current PC value of the i-th specified program segment as PC_Value i ; If PC_Value i &Trig_MaskReg i ==Trig_Reg i , which is called a PC trigger of the i-th specified program segment, and the execution proceeds to step S4, otherwise it proceeds to step S2; Step S4: trigger a write operation to TraceBuffer; each write content is a TraceItem, whose format is coreID+PCTrigID+TimeStamp, which is compressed and written to TraceBuffer; record the triggering number CNT i ; Step S5: If CNT i ==End_Reg i , then terminate the PC trigger operation of the i-th specified program segment and proceed to step S6, otherwise proceed to step S2; Step S6: If all the PC triggers of the designated program segments have been recorded, the process proceeds to step S7, otherwise the process proceeds to step S2; Step S7: The parsing software running on the debugging host reads the TraceBuffer content through the simulator and parses the control flow of the program execution.

2. The method for debugging heterogeneous multi-core processor system tracing according to claim 1, characterized in that: When executing step S3, a shared PC stream mode is adopted to determine whether the current PC needs to be tracked according to the pre-configuration of the control register; that is, PC_Value and Trig_MaskReg i The bitwise AND operation is performed and the result is equal to Trig_Reg i The comparator determines whether they are equal, if they are equal, it is 1, otherwise it is 0; in each core, the logical calculations of each pair of Trig_Reg and Trig_MaskReg are independent and performed synchronously.

3. The method for debugging heterogeneous multi-core processor system tracing according to claim 1, characterized in that: The step S4 comprises: Step S401: trigger a write operation to TraceBuffer; monitor TraceBuffer in real time, and when it is not full, trigger the write operation to TraceBuffer normally; when it is full, determine the next execution process by the value of TB_Cfg_Reg, if TB_Cfg_Reg is 0, perform the "wrap overwrite" operation, and write to TraceBuffer cyclically; in the later analysis, determine the sequence of TraceItem according to the timestamp; if TB_Cfg_Reg is 1, perform the "pause and wait" operation, the program is paused, and the content of TraceBuffer is read out. When the reading and writing are completed, continue to run the program, and execute the tracking and debugging of each program segment; Step S402: Record the trigger count CNT; record the trigger count in each core by category, recorded as CNT i , a pair of logic judgments of Trig_Reg and Trig_MaskReg is a type of trigger.

4. The method for debugging heterogeneous multi-core processor system tracing according to claim 1, characterized in that: In step S5, the trigger count CNT is input. i and End_Reg i When the comparator output is 1, the i-th PC type trigger operation is terminated, and no other tracking process will be executed for this type of situation.

5. The method for debugging a heterogeneous multi-core processor system according to any one of claims 1 to 4, characterized in that: In the step S1, when the register is pre-configured, Trig_Reg and Trig_MaskReg are set according to the instruction; according to the mask rule, when Trig_MaskReg is "0xFFFFFFFF", only the execution of the instruction is tracked, and Trig_Reg is the PC value of the instruction of interest at this time; if the adjacent segment of the specified instruction is concerned, the relevant bit of Trig_MaskReg is set to zero, the corresponding bit of Trig_Reg is set to zero, and the remaining bits are consistent with the PC value of the instruction; TB_Cfg_Reg is set to "0" or "1" according to requirements to achieve different functions.

6. A debugging device for tracing a heterogeneous multi-core processor system, characterized in that: include: Timestamp module, used to record the running time of a specific program segment; Control register module, each processor core contains Trig_Reg and Trig_MaskReg, which are used to determine whether to trigger the write operation to TraceBuffer; it contains the end control register End_Reg, which is used to determine whether to end the trigger; each Trig_Reg and its corresponding Trig_MaskReg and End_Reg form a trigger register group Trig_Reg_Group, and a Trig_Reg_Group controls the complete Trace behavior of a specified program segment, including whether the current PC generates a trigger and whether to end the Trace process of the program segment; Control processing module, used to complete counting comparison function and data compression function; The trace buffer module is used to correctly store TraceItem throughout the trace process.

7. The debugging device for tracing a heterogeneous multi-core processor system according to claim 6, characterized in that: The timestamp module includes a timestamp frequency division register and a timestamp counter; the input clock of the timestamp module is the processor main clock, and the main clock is passed through the timestamp frequency division register to obtain the timestamp clock after frequency division; The timestamp counter is driven by a timestamp clock, and the output is a timestamp.

8. The debugging device for tracing a heterogeneous multi-core processor system according to claim 6, characterized in that: The trace buffer module includes a TraceBuffer storage unit and a monitoring control unit. TraceItem is written into the TraceBuffer storage unit via a private buffer, connected to the Trace bus, and output to the outside of the chip. The monitoring control unit monitors in real time whether the TraceBuffer is full. If it is full, the control unit specifically executes "wrap overwrite" or "pause and wait".

9. The debugging device for tracing a heterogeneous multi-core processor system according to any one of claims 6 to 8, characterized in that: The control processing module includes a counting comparison unit and a data compression unit. The control register module sends pre-configured information to the counting comparison unit and obtains the current PC value from the bus. The data compression unit is used to complete the generation and compression of TraceItem.

10. The debugging device for tracing a heterogeneous multi-core processor system according to claim 9, characterized in that: The counting and comparing unit outputs two pieces of information and sends them to the data compression unit: one is CNT i ==End_Reg i The comparison result is used to decide whether to continue the trigger operation; the second is PCTrigID, which is used by the data compression unit to generate TraceItem.

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