MOS device for electrostatic discharge protection and method of manufacturing the same

Abstract

The application provides a MOS device for electrostatic discharge protection and a preparation method thereof, wherein the method comprises the following steps: forming first lightly doped drain regions in the low-voltage device area by using a first mask, wherein first windows are formed between the first lightly doped drain regions; forming second lightly doped drain regions in the high-voltage device area and the low-voltage device area by using a second mask. The application forms the patterned first lightly doped drain regions by using the first mask, then forms the second lightly doped drain regions in the first windows, and finally forms a first drain end on the first lightly doped drain regions and the second lightly doped drain regions, so that the ESD ion implantation area at the bottom of the first drain end can be formed at the same time when the first lightly doped drain regions and the second lightly doped drain regions are formed, thereby saving the manufacturing cost of the MOS device without increasing the ESD ion implantation process at the bottom of the first drain end, reducing the trigger voltage of the device, and improving the robustness of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of ESD device manufacturing, in particular to a MOS device for electrostatic discharge protection and a preparation method thereof. BACKGROUND

[0002] In order to overcome the reliability problem caused by hot carriers in deep submicron process, LDD process and structure are developed. In the current GGNMOS device for electrostatic discharge protection, the trigger voltage of the GGNMOS device is mainly determined by the breakdown voltage of N+ / PW, and the breakdown voltage is relatively high, so there is a situation that the protected device is damaged by ESD without triggering. Under a strong electric field, the NLDD (N-type lightly doped drain region) of the drain end (Drain) has a sharp tip discharge phenomenon, which can damage the device in advance and reduce the robustness of the GGNMOS device.

[0003] At present, in order to reduce the trigger voltage and improve the robustness, after the source end and the drain end are formed, an ESD implant process is added to form an ESD ion implant region at the bottom of the drain end. However, the addition of an ESD implant process requires an additional mask plate (photomask), which not only increases the manufacturing cost of the ESD GGNMOS device, but also increases the manufacturing process of the GGNMOS device. SUMMARY

[0004] The present application provides a MOS device for electrostatic discharge protection and a preparation method thereof, which can solve the problems of high manufacturing cost, complicated manufacturing process, high trigger voltage and poor robustness in the manufacturing process of the existing ESD MOS device.

[0005] In one aspect, the present application provides a preparation method of a MOS device for electrostatic discharge protection, the MOS device comprising: a high-voltage device region and a low-voltage device region, the preparation method of the MOS device for electrostatic discharge protection comprising:

[0006] providing a substrate, a plurality of spaced shallow trench isolation structures are formed in the substrate, the low-voltage device region and the high-voltage device region are separated by the shallow trench isolation structure, a first well region is formed in the substrate of the low-voltage device region, and a second well region is formed in the substrate of the high-voltage device region;

[0007] forming two spaced gate electrodes on the surface of the first well region of the low-voltage device region and the surface of the second well region of the high-voltage device;

[0008] performing ion implantation process on the substrate by using a first mask to form first lightly doped drain regions in the first well regions on both sides of the gate electrodes of the low voltage device region, wherein the first lightly doped drain regions between the two adjacent gate electrodes of the low voltage device region form first windows;

[0009] performing ion implantation process on the substrate by using a second mask to form second lightly doped drain regions in the second well regions on both sides of the gate electrodes of the high voltage device region and in the first well regions at the positions of the first windows of the low voltage device region;

[0010] performing ion implantation process on the substrate to form a first source terminal, a first drain terminal in the first well regions of the low voltage device region and a first heavily doped region in the second well regions of the high voltage device region, wherein the first drain terminal covers part of the first lightly doped drain regions and part of the second lightly doped drain regions between the two gate electrodes; and,

[0011] performing ion implantation process on the substrate to form a second heavily doped region in the first well regions of the low voltage device region and a second source terminal, a second drain terminal in the second lightly doped drain regions of the high voltage device region.

[0012] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection,

[0013] in the process of performing ion implantation process on the substrate by using a first mask to form first lightly doped drain regions in the first well regions on both sides of the gate electrodes of the low voltage device region, wherein the first lightly doped drain regions between the two adjacent gate electrodes of the low voltage device region form first windows, the method for manufacturing the MOS device for electrostatic discharge protection further comprises:

[0014] performing ion implantation process on the substrate of the high voltage device region by using the first mask to form first lightly doped drain regions in the second well regions between the two adjacent gate electrodes of the high voltage device region, wherein the second windows are formed between the gate electrodes and the first lightly doped drain regions.

[0015] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection,

[0016] in the process of performing ion implantation process on the substrate by using a second mask to form second lightly doped drain regions in the second well regions on both sides of the gate electrodes of the high voltage device region and in the first well regions at the positions of the first windows of the low voltage device region, the method for manufacturing the MOS device for electrostatic discharge protection further comprises:

[0017] performing ion implantation process on the substrate of the high voltage device region by using the second mask to form second lightly doped drain regions in the second well regions on both sides of the gate electrodes of the high voltage device region and in the second windows.

[0018] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection, in the process of performing ion implantation on the substrate to form the second heavily doped region in the first well region of the low-voltage device region and to form the second source terminal and the second drain terminal in the second well region of the high-voltage device region, in the high-voltage device region, the second drain terminal covers part of the first lightly doped drain region and part of the second lightly doped drain region between two gates.

[0019] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection, the height of the second lightly doped drain region is greater than the height of the first drain terminal, so that the first drain terminal covers part of the thickness of the second lightly doped drain region.

[0020] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection, the width of the first drain terminal in the lateral direction is greater than or equal to the width of the first window in the lateral direction.

[0021] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection, in the low-voltage device region, each of the first lightly doped drain regions extends a certain width into the first well region at the bottom of the gate in the lateral direction.

[0022] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection, after performing ion implantation on the substrate to form the second heavily doped region in the first well region of the low-voltage device region and to form the second source terminal and the second drain terminal in the second well region of the high-voltage device region, the method for manufacturing the MOS device for electrostatic discharge protection further comprises:

[0023] forming a metal silicide barrier layer covering the interface between the first drain terminal and the gate of the low-voltage device region and the interface between the second drain terminal and the gate of the high-voltage device region.

[0024] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection, the conductivity type of the substrate is P-type.

[0025] Optionally, in the method for manufacturing the MOS device for electrostatic discharge protection, in the low-voltage device region, the conductivity type of the first well region, the second lightly doped drain region, and the second heavily doped region is P-type; the conductivity type of the first lightly doped drain region, the first source terminal, and the first drain terminal is N-type; the second heavily doped region, the first source terminal, and the gate are all connected to the negative terminal of an external power supply; and the first drain terminal is connected to the positive terminal of the external power supply.

[0026] In the high-voltage device region, the second well region, the first heavily doped region are N-type, the second lightly doped drain region, the second source terminal and the second drain terminal are P-type, the first heavily doped region, the second source terminal and the gate are connected to the positive pole of an external power supply, and the second drain terminal is connected to the negative pole of the external power supply.

[0027] In another aspect, the embodiments of the present application also provide a MOS device for electrostatic discharge protection, which comprises a high-voltage device region and a low-voltage device region, and the MOS device for electrostatic discharge protection comprises:

[0028] a substrate, a plurality of spaced shallow trench isolation structures are formed in the substrate, the low-voltage device region and the high-voltage device region are separated by the shallow trench isolation structures, a first well region is formed in the substrate of the low-voltage device region, and a second well region is formed in the substrate of the high-voltage device region;

[0029] a gate, which is spaced apart from the surface of the first well region of the low-voltage device region and the surface of the second well region of the high-voltage device;

[0030] a first lightly doped drain region, which is located in the first well region on both sides of the gate of the low-voltage device region;

[0031] a second lightly doped drain region, which is located in the first well region on both sides of the gate of the low-voltage device region and in the second well region on both sides of the gate of the high-voltage device region;

[0032] a first heavily doped region, which is located in the second well region of the high-voltage device region;

[0033] a first source terminal and a first drain terminal, which are located in the first well region of the low-voltage device region, wherein the second lightly doped drain region between two adjacent gates is located at the bottom of the first drain terminal;

[0034] a second heavily doped region, which is located in the first well region of the low-voltage device region;

[0035] a second source terminal and a second drain terminal, which are located in the second lightly doped drain region of the high-voltage device region.

[0036] The technical scheme of the present application has at least the following advantages:

[0037] The application provides a MOS device for electrostatic discharge protection and a preparation method thereof, wherein the method comprises the following steps: performing ion implantation on the substrate by using a first mask to form a patterned first lightly doped drain region in the low-voltage device area, wherein a first window is formed between the first lightly doped drain regions; performing ion implantation on the substrate by using a second mask to form a second lightly doped drain region in the second well region on both sides of the gate of the high-voltage device area and in the first well region at the position of the first window of the low-voltage device area. In the low-voltage device area, the first lightly doped drain region is formed by using the first mask, then the second lightly doped drain region is formed in the first window, and finally the first drain end is formed on the first lightly doped drain region and the second lightly doped drain region, so that the second lightly doped drain region (ESD ion implantation region) can be formed at the same time as the first lightly doped drain region and the second lightly doped drain region are formed, thereby saving the mask and reducing the manufacturing cost of the MOS device, and the trigger voltage of the device is reduced and the robustness of the device is improved without increasing the ESD ion implantation process at the bottom of the first drain end. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0039] Figures 1-8 is a semiconductor structure schematic diagram in each process step of preparing the MOS device of the first embodiment of the present application;

[0040] Figures 9-16 is a semiconductor structure schematic diagram in each process step of preparing the MOS device of the second embodiment of the present application;

[0041] In the drawings, the reference signs are explained as follows:

[0042] 100-substrate, 101-shallow trench isolation structure, 102-first well region, 103-first lightly doped drain region, 104-second lightly doped drain region, 105-first source end, 106-first drain end, 107-first heavily doped region, 108-second heavily doped region, 109-second well region, 110-gate, 211-second source end, 212-second drain end, 220-metal silicide barrier layer, 300-first window;

[0043] 10-substrate, 11-shallow trench isolation structure, 12-first well region, 13-second well region, 14-first lightly doped drain region, 15-second lightly doped drain region, 16-first source terminal, 17-first drain terminal, 18-first heavily doped region, 19-second heavily doped region, 20-gate, 21-second source terminal, 22-second drain terminal, 30-metal silicide barrier layer, 40-first window, 50-second window. DETAILED DESCRIPTION

[0044] The technical solutions in the application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the application, but not all of them. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the application.

[0045] In the description of the application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0046] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0047] In addition, the technical features involved in the different embodiments of the application described below can be combined with each other as long as they do not conflict with each other.

[0048] Embodiment one

[0049] The embodiment of the application provides a preparation method of a MOS device for electrostatic discharge protection. The MOS device includes a high-voltage device region and a low-voltage device region. The trigger voltage of the low-voltage device region can be 1.2V or 2.5V. The trigger voltage of the high-voltage device region can be 5V. Please refer to Figures 1-8Next, the preparation method of the MOS device for electrostatic discharge protection is introduced in detail.

[0050] First, as shown in Figure 1 , a substrate 100 is provided, the left side of the substrate 100 is a low-voltage device area; the right side of the substrate 100 is a high-voltage device area; a plurality of spaced shallow trench isolation structures (STI) 101 are formed in the substrate 100, the low-voltage device area and the high-voltage device area can be isolated by the shallow trench isolation structure 101, a first well region 102 is formed in the substrate 100 of the low-voltage device area, and a second well region 109 is formed in the substrate 100 of the high-voltage device area. Among them, a plurality of spaced shallow trench isolation structures 101 are also formed in the first well region 102; a plurality of spaced shallow trench isolation structures 101 are also formed in the second well region 109. The conductivity type of the substrate 100 is P type, the conductivity type of the first well region 102 can be P type, that is, the first well region 102 is LV PW; the conductivity type of the second well region 109 can be N type, that is, the second well region 109 is LV NW.

[0051] Then, as shown in Figure 2 , two spaced gate electrodes 110 are formed on the surface of the first well region 102 of the low-voltage device area and the surface of the second well region 109 of the high-voltage device.

[0052] Next, as shown in Figure 3 , the substrate 100 is subjected to ion implantation process by using a first mask, so as to form a first lightly doped drain region 103 in the first well region 102 on both sides of the gate electrode 110 of the low-voltage device area, wherein the first lightly doped drain region 103 between the two adjacent gate electrodes 110 of the low-voltage device area forms a first window 300. Specifically, in the low-voltage device area, each of the first lightly doped drain regions 103 extends to the first well region 102 at the bottom of the gate electrode 110 in the lateral direction, and the two adjacent first lightly doped drain regions 103 do not contact each other in the first well region 102 at the bottom of the gate electrode 110. The conductivity type of the first lightly doped drain region 103 can be N type.

[0053] Further, as shown in Figure 4 , the substrate 100 is subjected to ion implantation process by using a second mask, so as to form a second lightly doped drain region 104 in the second well region 109 on both sides of the gate electrode 110 of the high-voltage device area and the first well region 102 at the position of the first window 300 of the low-voltage device area. Specifically, the conductivity type of the second lightly doped drain region 104 can be P type.

[0054] Next, as shown in Figure 5As shown, the substrate 100 undergoes an ion implantation process to form a first source terminal 105 and a first drain terminal 106 in the first well region 102 of the low-voltage device region, and two first heavily doped regions 107 in the second well region 109 of the high-voltage device region. The first drain terminal 106 covers a portion of the first lightly doped drain region 103 and a portion of the second lightly doped drain region 104 between the two gates 110. Specifically, the two first heavily doped regions 107 are located between the two shallow channel isolation structures 101 located away from the center of the high-voltage device region. The conductivity type of the first heavily doped region 107, the first source terminal 105, and the first drain terminal 106 can all be N-type.

[0055] In this embodiment, as Figure 5 As shown, in the low-voltage device region, the height of the second lightly doped drain region 104 is greater than the height of the first drain end 106, so that the first drain end 106 covers a portion of the thickness of the second lightly doped drain region 104. Furthermore, the width of the first drain end 106 in the lateral direction is greater than or equal to the width of the first window 300 in the lateral direction.

[0056] Finally, as Figure 6 As shown, the substrate 100 undergoes an ion implantation process to form two heavily doped regions 108 in the first well region 102 of the low-voltage device region and a second source terminal 211 and a second drain terminal 212 in the second lightly doped drain region 104 of the high-voltage device region. Specifically, the two heavily doped regions 108 are located between the two shallow channel isolation structures 101 located away from the center of the low-voltage device region. The conductivity type of the second heavily doped regions 108, the second source terminal 211, and the second drain terminal 212 can all be P-type.

[0057] The application forms the first light-doped drain region 103 in the low-voltage device region by using the first mask, then forms the second light-doped drain region 104 in the first window 300, and finally forms the first drain end 106 on the first light-doped drain region 103 and the second light-doped drain region 104 between the gates 110, so that the second light-doped drain region (ESD ion implantation region) at the bottom of the first drain end 106 can be formed at the same time as the first light-doped drain region 103 and the second light-doped drain region 104, thereby saving the mask and the manufacturing cost of the MOS device, and the longitudinal depth of the second light-doped drain region (ESD ion implantation region) 104 is deeper than the longitudinal depth of the first drain end 106 (heavily doped N+), so that the breakdown junction of the first drain end 106 becomes N+ 106 / (PW 102+ second doped region 104), which improves the P-type doping concentration below the second light-doped drain region 104, reduces the trigger voltage of the device, and the ESD current is discharged from the low trigger voltage interface first, so that the first light-doped drain region (N-type LDD) 103 of the first drain end 106 will not fail first due to the tip discharge, thereby improving the robustness of the device and meeting the ESD protection while considering the economic benefits.

[0058] Further, as shown in Figure 7 After the second heavily doped region 108, the second source end 211 and the second drain end 212 are formed, the method for manufacturing the MOS device for electrostatic discharge protection further comprises: forming a metal silicide barrier layer 220 covering the interface between the first drain end 106 and the gate 110 in the low-voltage device region and the interface between the second drain end 212 and the gate 110 in the high-voltage device region, mainly to prevent the formation of metal silicide on the surface of the first light-doped drain region 103 (substrate) inside the interface position between the first drain end 106 and the gate 110, and to prevent the formation of metal silicide on the surface of the second light-doped drain region 104 (substrate) inside the interface position between the second drain end 212 and the gate 110.

[0059] In the embodiment, as shown in Figure 8 In the low-voltage device region, the second heavily doped region 108, the first source end 105 and the gate 110 are connected to the negative pole of the external power supply; the first drain end 106 is connected to the positive pole of the external power supply; in the high-voltage device region, the first heavily doped region 107, the second source end 211 and the gate 110 are connected to the positive pole of the external power supply, and the second drain end 212 is connected to the negative pole of the external power supply.

[0060] Based on the same inventive concept, the embodiment of the present application also provides a MOS device for electrostatic discharge protection, as shown in Figure 5 The MOS device for electrostatic discharge protection comprises:

[0061] a substrate 100, in which a plurality of shallow trench isolation structures 101 are formed at intervals, and the low-voltage device region and the high-voltage device region are separated by the shallow trench isolation structures 101, the substrate 100 of the low-voltage device region is formed with a first well region 102, and the substrate 100 of the high-voltage device region is formed with a second well region 109;

[0062] a gate 110, which is arranged at intervals on the surface of the first well region 102 of the low-voltage device region and the surface of the second well region 109 of the high-voltage device region;

[0063] a first lightly doped drain region 103, which is located in the first well region 102 on both sides of the gate 110 of the low-voltage device region;

[0064] a second lightly doped drain region 104, which is located in the second well region 109 on both sides of the gate 110 of the high-voltage device region and in the first well region 102 on both sides of the gate 110 of the low-voltage device region;

[0065] a first heavily doped region 107, which is located in the second well region 109 of the high-voltage device region;

[0066] a first source end 105 and a first drain end 106, which are located in the first well region 102 of the low-voltage device region, and the second lightly doped drain region 103 between two adjacent gates 110 is located at the bottom of the first drain end 106;

[0067] a second heavily doped region 108, which is located in the first well region 102 of the low-voltage device region;

[0068] a second source end 211 and a second drain end 212, which are located in the second lightly doped drain region 104 of the high-voltage device region.

[0069] Embodiment two

[0070] Please refer to Figures 9-16 The embodiment details another preparation method of a MOS device for electrostatic discharge protection.

[0071] First, as shown in Figure 9As shown in FIG. 1, a substrate 10 is provided, the left side of the substrate 10 is a first high-voltage device region; the right side of the substrate 10 is a second high-voltage device region; a plurality of spaced shallow trench isolation structures (STI) 11 are formed in the substrate 10, the first high-voltage device region and the second high-voltage device region can be isolated by the shallow trench isolation structures 11, a first well region 12 is formed in the substrate 10 of the first high-voltage device region, and a second well region 13 is formed in the substrate 10 of the second high-voltage device region. Among them, a plurality of spaced shallow trench isolation structures 11 are also formed in the first well region 12; a plurality of spaced shallow trench isolation structures 11 are also formed in the second well region 13. The conductivity type of the substrate 10 is P type, the conductivity type of the first well region 12 can be P type, that is, the first well region 12 is HV PW; the conductivity type of the second well region 13 can be N type, that is, the second well region 13 is HV NW.

[0072] Then, as shown in FIG. 2, ion implantation process is performed on the substrate 10 by using a first mask to form a first lightly doped drain region 14 in the first well region 12 on both sides of the gate 20 of the first high-voltage device region and in the second well region 13 between the adjacent two gates 20 of the second high-voltage device region, wherein a first window 40 is formed between the first lightly doped drain regions 14 of the first high-voltage device region, and a second window 50 is formed between the gate 20 and the first lightly doped drain region 104 of the second high-voltage device region. The conductivity type of the first lightly doped drain region 14 can be N type. Figure 10

[0073] Then, as shown in FIG. 3, ion implantation process is performed on the substrate 10 by using a second mask to form a second lightly doped drain region 15 in the second well region 13 on both sides of the gate 20 of the second high-voltage device region and in the first well region 12 at the position of the first window 40 of the first high-voltage device region. Specifically, the conductivity type of the second lightly doped drain region 15 can be P type. Figure 11

[0074] Further, as shown in FIG. 4, ion implantation process is performed on the substrate 10 by using a third mask to form a third lightly doped drain region 16 in the first well region 12 on both sides of the gate 20 of the first high-voltage device region and in the second well region 13 at the position of the second window 50 of the second high-voltage device region. Specifically, the conductivity type of the third lightly doped drain region 16 can be N type. Figure 12

[0075] Then, as shown in FIG. 5, ion implantation process is performed on the substrate 10 by using a fourth mask to form a fourth lightly doped drain region 17 in the first well region 12 on both sides of the gate 20 of the first high-voltage device region and in the second well region 13 at the position of the first window 40 of the first high-voltage device region. Specifically, the conductivity type of the fourth lightly doped drain region 17 can be P type. Figure 13 ​​​As shown, the substrate 10 undergoes an ion implantation process to form a first source terminal 16 and a first drain terminal 17 in the first well region 12 of the first high-voltage device region, and two first heavily doped regions 18 in the second well region 13 of the second high-voltage device region. The first drain terminal 17 covers a portion of the first lightly doped drain region 14 and a portion of the second lightly doped drain region 15 between the two gates 20. Specifically, the two first heavily doped regions 18 are located between the two shallow channel isolation structures 11 located away from the center of the second high-voltage device region. The conductivity type of the first heavily doped region 18, the first source terminal 16, and the first drain terminal 17 can all be N-type.

[0076] Finally, as Figure 14 As shown, the substrate 10 undergoes an ion implantation process to form two heavily doped regions 19 in the first well region 12 of the first high-voltage device region and a second source terminal 21 and a second drain terminal 22 in the second lightly doped drain region 15 of the second high-voltage device region. Specifically, the two heavily doped regions 19 are located between the two shallow channel isolation structures 11 located away from the center of the first high-voltage device region. The second drain terminal 22 covers a portion of the first lightly doped drain region 14 and a portion of the second lightly doped drain region 15 between the two gates 20. The conductivity type of the second heavily doped region 19, the second source terminal 21, and the second drain terminal 22 can all be P-type.

[0077] Similarly, such as Figure 15 As shown, after forming the second heavily doped region 19, the second source terminal 21, and the second drain terminal 22, the fabrication method of the MOS device for electrostatic discharge protection further includes: forming a metal silicide barrier layer 30, wherein the metal silicide barrier layer 30 covers the interface between the first drain terminal 17 and the gate terminal 20 of the first high-voltage device region and the interface between the second drain terminal 22 and the gate terminal 20 of the second high-voltage device region.

[0078] In this embodiment, as Figure 16 As shown, in the first high-voltage device region, the second heavily doped region 19, the first source terminal 16, and the gate 20 are all connected to the negative terminal of the external power supply; the first drain terminal 17 is connected to the positive terminal of the external power supply; in the second high-voltage device region, the first heavily doped region 18, the second source terminal 21, and the gate 20 are all connected to the positive terminal of the external power supply, and the second drain terminal 22 is connected to the negative terminal of the external power supply.

[0079] In the embodiment, the first lightly doped drain region 14 at the bottom of the first drain end 22 of the second high-voltage device region is obtained by using the first mask, and the second lightly doped drain region 15 at the bottom of the first drain end 17 of the first high-voltage device region is obtained by using the second mask. The second lightly doped drain region (ESD ion implantation region) can be directly formed at the same time when the first lightly doped drain region 14 and the second lightly doped drain region 15 are formed. Therefore, the mask is saved, the manufacturing cost of the MOS device is indirectly saved, the trigger voltage of the device is reduced, and the robustness of the device is improved without additional ESD ion implantation processes at the bottom of the first / second drain end.

[0080] Obviously, the above embodiment is only an example for clearly illustrating but not limiting the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. All the embodiments do not need to be exhausted here. The changes or variations derived therefrom are still within the protection scope of the application.

Claims

1. A method for fabricating a MOS device for electrostatic discharge protection, characterized by, The MOS device comprises a high-voltage device region and a low-voltage device region, and the method for manufacturing the MOS device for electrostatic discharge protection comprises: providing a substrate, a plurality of spaced shallow trench isolation structures are formed in the substrate, the low-voltage device region and the high-voltage device region are separated by the shallow trench isolation structures, a first well region is formed in the substrate of the low-voltage device region, and a second well region is formed in the substrate of the high-voltage device region; forming two spaced gate electrodes on the surface of the first well region of the low-voltage device region and the surface of the second well region of the high-voltage device; performing ion implantation on the substrate by using a first mask to form first lightly doped drain regions in the first well region on both sides of the gate electrodes of the low-voltage device region, wherein the first lightly doped drain regions between the two adjacent gate electrodes of the low-voltage device region form a first window; performing ion implantation on the substrate by using a second mask to form second lightly doped drain regions in the second well region on both sides of the gate electrodes of the high-voltage device region and in the first well region at the position of the first window of the low-voltage device region; performing ion implantation on the substrate to form a first source terminal and a first drain terminal in the first well region of the low-voltage device region and a first heavily doped region in the second well region of the high-voltage device region, wherein the first drain terminal covers part of the first lightly doped drain regions and part of the second lightly doped drain regions between the two gate electrodes; and performing ion implantation on the substrate to form a second heavily doped region in the first well region of the low-voltage device region and a second source terminal and a second drain terminal in the second lightly doped drain region of the high-voltage device region.

2. The method of claim 1, wherein the MOS device is a n-channel MOS device. In the process of performing ion implantation on the substrate by using a first mask to form first lightly doped drain regions in the first well region on both sides of the gate electrodes of the low-voltage device region, wherein the first lightly doped drain regions between the two adjacent gate electrodes of the low-voltage device region form a first window, the method for manufacturing the MOS device for electrostatic discharge protection further comprises: performing ion implantation on the substrate of the high-voltage device region by using the first mask to form first lightly doped drain regions in the second well region between the two adjacent gate electrodes of the high-voltage device region, wherein a second window is formed between the gate electrodes and the first lightly doped drain regions.

3. The method of claim 2, wherein the method further comprises: In the process of performing ion implantation on the substrate by using a second mask to form second lightly doped drain regions in the second well region on both sides of the gate electrodes of the high-voltage device region and in the first well region at the position of the first window of the low-voltage device region, the method for manufacturing the MOS device for electrostatic discharge protection further comprises: performing ion implantation on the substrate of the high-voltage device region by using the second mask to form second lightly doped drain regions in the second well region at the position of the second window and the gate electrodes of the high-voltage device region.

4. The method of claim 3, wherein the method further comprises: In the process of performing ion implantation on the substrate to form a second heavily doped region in the first well region of the low-voltage device region and to form a second source terminal and a second drain terminal in the second well region of the high-voltage device region, in the high-voltage device region, the second drain terminal covers part of the first lightly doped drain region and part of the second lightly doped drain region between two gates.

5. The method of claim 1, wherein the MOS device is a n-channel MOS device. The height of the second lightly doped drain region is greater than the height of the first drain terminal, so that the first drain terminal covers part of the thickness of the second lightly doped drain region.

6. The method of claim 1, wherein the MOS device is a n-channel MOS device. The width of the first drain terminal in the lateral direction is greater than or equal to the width of the first window in the lateral direction.

7. The method of claim 1, wherein the MOS device is a n-channel MOS device. In the low-voltage device region, each of the first lightly doped drain regions extends a certain width into the first well region at the bottom of the gate in the lateral direction.

8. The method of claim 1, wherein the MOS device is a n-channel MOS device. After performing ion implantation on the substrate to form a second heavily doped region in the first well region of the low-voltage device region and to form a second source terminal and a second drain terminal in the second well region of the high-voltage device region, the method for manufacturing the MOS device for electrostatic discharge protection further comprises: forming a metal silicide barrier layer covering the interface between the first drain terminal and the gate of the low-voltage device region and the interface between the second drain terminal and the gate of the high-voltage device region.

9. The method of claim 1 to 8, wherein, The conductivity type of the substrate is P-type.

10. The method of claim 9, wherein the method further comprises: In the low-voltage device region, the conductivity types of the first well region, the second lightly doped drain region, and the second heavily doped region are P-type; the conductivity types of the first lightly doped drain region, the first source terminal, and the first drain terminal are N-type; the second heavily doped region, the first source terminal, and the gate are all connected to the negative terminal of an external power supply; and the first drain terminal is connected to the positive terminal of the external power supply. In the high-voltage device region, the conductivity types of the second well region and the first heavily doped region are N-type; the conductivity types of the second lightly doped drain region, the second source terminal, and the second drain terminal are P-type; the first heavily doped region, the second source terminal, and the gate are all connected to the positive terminal of an external power supply; and the second drain terminal is connected to the negative terminal of the external power supply.

11. A MOS device for electrostatic discharge protection, characterized by The MOS device comprises a high-voltage device region and a low-voltage device region, and the MOS device for electrostatic discharge protection comprises: a substrate in which a plurality of spaced shallow trench isolation structures are formed, the low-voltage device region and the high-voltage device region being separated by the shallow trench isolation structures, a first well region being formed in the substrate of the low-voltage device region, and a second well region being formed in the substrate of the high-voltage device region; two spaced gates, one of the gates being arranged on the surface of the first well region of the low-voltage device region, and the other of the gates being arranged on the surface of the second well region of the high-voltage device; a first lightly doped drain region located in the first well region on both sides of the gate of the low-voltage device region; a second lightly doped drain region located in the second well region on both sides of the gate of the high-voltage device region and in the first well region on both sides of the gate of the low-voltage device region; a first heavily doped region located in the second well region of the high-voltage device region; and a second heavily doped region located in the first well region of the low-voltage device region. a first source end and a first drain end in a first well region of the low voltage device region, wherein a second lightly doped drain region between two adjacent gates is at a bottom of the first drain end; a second heavily doped region in the first well region of the low voltage device region; a second source end and a second drain end in the second lightly doped drain region of the high voltage device region.

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