Electronic device

Abstract

The present application provides an electronic device, which comprises a level conversion circuit including a first voltage domain circuit and a second voltage domain circuit. The second voltage domain circuit converts an input signal of the first voltage domain circuit into an output signal of the second voltage domain. The input signal switches between a first high level potential and a first low level potential, and the output signal switches between a second high level potential and a second low level potential. The second voltage domain circuit comprises a plurality of transistors, which form an input unit, a control unit and an output unit. The control unit clamps the voltage domains of the input unit and the output unit in a preset range according to a first control voltage and a second control voltage, so as to avoid the same type of transistors in the second voltage domain circuit from being broken down. The present application also provides an electronic device.

Description

Technical Field

[0001] This invention relates to signal transmission between different voltage domains, and more particularly to an electronic device. Background Technology

[0002] A typical display includes a display panel and display driver circuitry for driving the display panel to display images. Driver circuitry located outside the display area usually includes level shifting circuitry. Level shifting circuitry is used to convert signals from low-voltage domains to high-voltage domains or vice versa, enabling signal transmission between different voltage domains. Level shifting circuitry includes input circuitry, output circuitry, and control circuitry connecting the input and output circuits. Input circuitry includes a positive input terminal and a negative input terminal, each with a pair of input transistors. Output circuitry includes a positive output terminal and a negative output terminal, each with a pair of output transistors. In existing circuit architectures, level shifting circuitry is mainly used for switching between different voltage domains. The withstand voltage of the transistors in the level shifting circuitry needs to be greater than the operating voltage. The difference between the converted high-level and low-level potentials cannot exceed the breakdown voltage range (including gate oxide breakdown, drain-to-substrate breakdown, source-drain breakdown, etc.). Exceeding the breakdown voltage range will cause device breakdown, requiring replacement of the device type (e.g., replacing a low-voltage MOS with a medium / high-voltage MOS) to increase the withstand voltage, adding extra manufacturing processes and increasing chip costs. Furthermore, if the voltage domain is divided into more levels for conversion, the circuit area will be too large, resulting in excessive delay in signal transmission and thus limiting the level conversion speed. Summary of the Invention

[0003] In view of this, it is necessary to provide a level conversion circuit and electronic device to solve the technical problems of excessive circuit area and excessive signal transmission delay when using multi-stage circuits for voltage domain conversion in the prior art.

[0004] A level conversion circuit is used to convert a signal in a first voltage domain into a signal in a second voltage domain; the level conversion circuit includes:

[0005] A first voltage domain circuit receives an input signal in a first voltage domain; the input signal switches between a first high-level potential and a first low-level potential.

[0006] A second voltage domain circuit is used to convert the input signal into an output signal in the second voltage domain; wherein the second voltage domain signal switches between a second high-level potential and a second low-level potential; the first high-level potential and the second high-level potential are different, the first low-level potential and the second low-level potential are different, and the second high-level potential is less than or equal to the first low-level potential.

[0007] The second voltage domain circuit includes multiple transistors, which constitute an input unit, a control unit, and an output unit. The control unit is used to clamp the voltage domain of the input unit and the output unit within a preset range according to a first control voltage and a second control voltage, so as to prevent the transistors of the same type in the second voltage domain circuit from being broken down to their breakdown voltage values.

[0008] An electronic device includes a level conversion circuit; the level conversion circuit is used to convert a signal in a first voltage domain into a signal in a second voltage domain; the level conversion circuit includes:

[0009] A first voltage domain circuit receives an input signal in a first voltage domain; the input signal switches between a first high-level potential and a first low-level potential.

[0010] A second voltage domain circuit is used to convert the input signal into an output signal in the second voltage domain; wherein the second voltage domain signal switches between a second high-level potential and a second low-level potential; the first high-level potential and the second high-level potential are different, the first low-level potential and the second low-level potential are different, and the second high-level potential is less than or equal to the first low-level potential.

[0011] The second voltage domain circuit includes multiple transistors, which constitute an input unit, a control unit, and an output unit. The control unit is used to clamp the voltage domains of the input unit and the output unit within a preset range according to a first control voltage and a second control voltage, so as to prevent the transistors of the same type in the second voltage domain circuit from being broken down.

[0012] The aforementioned level conversion circuit and electronic device achieve voltage conversion from high voltage domain to low voltage domain through a separate second voltage domain circuit, reducing the complexity of the level conversion circuit, improving signal conversion speed, and reducing signal delay time. At the same time, the control unit clamps the voltage domains of the input and output units, avoiding the risk of transistors of the same type being damaged in the second voltage domain circuit, reducing production costs while ensuring the normal operation of the system. Attached Figure Description

[0013] Figure 1 This is a three-dimensional schematic diagram of an electronic device according to a preferred embodiment of the present invention.

[0014] Figure 2 for Figure 1 A schematic diagram of the electronic device according to a preferred embodiment.

[0015] Figure 3 for Figure 2 The circuit diagram of the level conversion circuit described in the document is shown.

[0016] Figure 4 This is a circuit diagram of the first control voltage generation circuit according to the first embodiment.

[0017] Figure 5 This is a circuit diagram of the first control voltage generation circuit in the second embodiment.

[0018] Explanation of main component symbols

[0019]

[0020]

[0021] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that allows for mutual communication; it can be a direct connection or an indirect connection through an intermediate connection; it can be a connection within two components or an interaction between two components. Those skilled in the art can readily understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0024] The terms "first," "second," and "third," etc., used in the specification and accompanying drawings of this invention are for distinguishing different objects, not for describing a specific order. Furthermore, the term "comprising," and any variations thereof, are intended to cover non-exclusive inclusion.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0026] The specific embodiments of the level conversion circuit and electronic device of the present invention will be described below with reference to the accompanying drawings.

[0027] Please refer to Figure 1 This is a perspective view of an electronic device 1 according to an embodiment of the present invention. In at least one embodiment of the present invention, the electronic device 1 can be a mobile device such as a personal computer, tablet computer, smartphone, personal digital assistant (PDA), game console, interactive network television (Internet Protocol Television, IPTV), smart wearable device, navigation device, etc., or a fixed device such as a desktop computer, server, digital television, etc. The electronic device 1 may have one or more of the following functions: touch function, display function, fingerprint recognition function, and camera function.

[0028] The electronic device 1 includes a cover plate 11, a first functional layer 12, and a second functional layer 13.

[0029] The cover plate 11 is made of a transparent material. The cover plate 11 can be a glass substrate or other transparent substrate made of a high-strength, high-hardness material. In at least one embodiment of the present invention, the cover plate 11 can be made of materials such as polycarbonate (PC), polyester (PET), polymethyl methacrylate (PMMA), cycloolefin copolymer (COC), or polyether sulfone (PES).

[0030] The first functional layer 12 is used to identify a user's touch operation and / or biometrics. The first functional layer 12 is disposed below the cover plate 11. The first functional layer 12 also covers and is disposed above the second functional layer 13. In at least one embodiment of the present invention, the first functional layer 12 may be a touch layer (not shown) to identify at least one or a combination of touch position and touch pressure. In at least one embodiment of the present invention, the first functional layer 12 is a single-layer interconductive touch structure. The first functional layer 12 is made of a conductive material. In at least one embodiment of the present invention, the first functional layer 12 may further include a biometric identification layer (not shown) to identify a user's biometrics. In at least one embodiment of the present invention, the biometrics may be fingerprints, faces, irises, etc., but are not limited to these.

[0031] The second functional layer 13 is disposed below the first functional layer 12. The second functional layer 13 is used to display image information. In at least one embodiment of the present invention, the second functional layer 13 may be a liquid crystal display (LCD), a light emitting diode (LED) display layer, an organic light emitting diode (OLED) display layer, an active-matrix organic light emitting diode (AMOLED) display layer, an electrophoretic display layer, etc., but is not limited thereto. The second functional layer 13 is made of a conductive material and may be patterned to form multiple pixel electrodes. In other embodiments, the second functional layer 13 may also form multiple photosensitive elements (not shown), such as charge-coupled devices (CCD) or complementary metal-oxide-semiconductor (CMOS) elements, to sense changes in light and generate a response signal (not shown).

[0032] Please refer to the following: Figure 2 This is a schematic diagram of the electronic device 1. The electronic device 1 defines a display area 101 and a non-display area 103 surrounding the display area 101. The display area 101 includes multiple scan lines S1-Sn and multiple data lines D1-Dm. Here, n and m are positive integers. The multiple scan lines S1-Sn extend along a first direction X and are arranged parallel to each other, and the multiple data lines D1-Dm extend along a second direction Y and are arranged parallel to each other. The multiple scan lines S1-Sn and the multiple data lines D1-Dm are insulated from each other and arranged in a grid pattern, defining multiple pixel units 20 arranged in a matrix.

[0033] Electronic device 1 includes a scan drive circuit 110, a data drive circuit 120, and a timing controller 130. Each column of pixel units 20 is electrically connected to the scan drive circuit 110 via a scan line Sn, and each row of pixel units 20 is electrically connected to the data drive circuit 120 via a data line Dm. The timing controller 130 is electrically connected to both the scan drive circuit 110 and the data drive circuit 120. The timing controller 130 generates multiple synchronization control signals for the scan drive circuit 110 and the data drive circuit 120. The multiple synchronization control signals may include periodic synchronization control signals and aperiodic synchronization control signals. The multiple synchronization control signals include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a data enable signal (DE). In this embodiment, the timing controller 130 provides a clock signal to the scan drive circuit 110. The scan drive circuit 110 provides scan signals to multiple scan lines S1-Sn to scan the pixel units 20. The data driving circuit 120 provides image signals to multiple data lines D1-Dm for image display. The image signals are digital signals, consisting of low levels (e.g., logic 0) and high levels (e.g., logic 1). In at least one embodiment of the present invention, the scan driving circuit 110 is disposed above the display area, and the data driving circuit 120 is disposed to the left of the display area.

[0034] The data driving circuit 120 includes a level conversion circuit 200. The level conversion circuit 200 converts an input signal in a first voltage domain into an output signal in a second voltage domain, ensuring that the voltage difference generated by all transistors within the level conversion circuit 200 during voltage conversion is less than the withstand voltage threshold corresponding to the transistor. In at least one embodiment of the present invention, a first high-level potential VDDH in the first voltage domain is greater than a second high-level potential VDDL in the second voltage domain, and a voltage difference exists between them; and a first low-level potential VSSH in the first voltage domain is greater than a second low-level potential VSSL in the second voltage domain, and a voltage difference exists between them. Simultaneously, the second high-level potential VDDL in the second voltage domain is less than or equal to the first low-level potential VSSH in the first voltage domain. The withstand voltage threshold is the minimum value among the source-drain withstand voltage, gate withstand voltage, and substrate source-drain withstand voltage of the transistor. The source-drain withstand voltage is the voltage difference between the source and drain of the transistor. The gate withstand voltage includes the voltage difference between the gate and source of the transistor and the voltage difference between the gate and drain of the transistor. The substrate source-drain withstand voltage includes the voltage difference between the substrate and drain of the transistor and the voltage difference between the substrate and source of the transistor. If the voltage difference between the source and drain of the transistor exceeds the withstand voltage threshold, the transistor is broken down. In other embodiments, the level conversion circuit 200 can also be applied to the scan drive circuit 110.

[0035] Please refer to the following: Figure 3 This is a circuit diagram of the level conversion circuit 200. The level conversion circuit 200 includes a first voltage domain circuit 21 and a second voltage domain circuit 23.

[0036] The first voltage domain circuit 21 outputs the received input signal in the first voltage domain to the second voltage domain circuit 23. In at least one embodiment of the present invention, the first voltage domain circuit 21 outputs a first output signal IN and a second output signal INB of the first voltage domain to the second voltage domain circuit 23. The first output signal IN and the second output signal INB are inverted signals. In an embodiment of the present invention, the input signal of the first voltage domain can be a first high-level potential VDDH or a first low-level potential VSSH in the first voltage domain. The first voltage domain circuit 21 includes an input terminal DIN, a first inverter INT1, and a second inverter INT2. The input terminal DIN receives the input signal. The first inverter INT1 and the second inverter INT2 are connected in series between the input terminal DIN and the second voltage domain circuit 23. The input terminal of the first inverter INT1 is electrically connected to the input terminal DIN, and the output terminal of the first inverter INT1 is electrically connected to the input terminal of the second inverter INT2 and the second voltage domain circuit 23. The input terminal of the second inverter INT2 is electrically connected to the output terminal of the first inverter INT1, and the output terminal of the second inverter INT2 is electrically connected to the second voltage domain circuit 23.

[0037] The second voltage domain circuit 23 is used to convert the received input signal in the first voltage domain into an output signal in the second voltage domain and output it. In an embodiment of the present invention, the output signal in the second voltage domain can be a second high-level potential VDDL in the second voltage domain or a second low-level potential VSSL in the first voltage domain.

[0038] The second voltage domain circuit 23 includes an input unit 231, a control unit 232, and an output unit 234. The input unit 231 receives the input signal of the first voltage domain. The input unit 231 includes a first input transistor MN1 and a second input transistor MN2. The control terminal of the first input transistor MN1 is electrically connected to the output terminal of the second inverter INT2 to receive the first output signal IN, and the control terminal of the second input transistor MN2 is electrically connected to the output terminal of the first inverter INT1 to receive the second output signal INB. The first connection terminals of the first input transistor MN1 and the second input transistor MN2 receive the second high-level potential VDDL, and the second connection terminals of the first input transistor MN1 and the second input transistor MN2 are electrically connected to the control unit 232. In at least one embodiment of the present invention, the first input transistor MN1 and the second input transistor MN2 are NMOS transistors, the control terminal is the gate, the first connection terminal is the source, and the second connection terminal is the drain.

[0039] The control unit 232 is configured to clamp the voltage domains of the input unit 231 and the output unit 234 within a preset range according to a first control voltage VRN1 and a second control voltage VRN2, so as to prevent the same type of transistors in the second voltage domain from being broken down. Among them, the first control voltage VRN1 is less than the second control voltage VRN2. In at least one embodiment of the present invention, the first control voltage VRN1 is greater than a first value and less than a second value. Wherein, the first value is the value obtained by subtracting the first threshold voltage VTHP and then subtracting the second threshold voltage VTHN from the first low-level potential VSSH; the second value is the value obtained by subtracting the first threshold voltage VTHP and then subtracting the second threshold voltage VTHN from the second high-level potential VDDL. That is, the first control voltage VRN1 satisfies the following condition 1:

[0040] VSSH - VTHP - VTHN < VRN1 ≤ VDDL - VTHP - VTHN Condition 1

[0041] In at least one embodiment of the present invention, the first threshold voltage VTHP is the threshold voltage corresponding to the PMOS transistor, and the second threshold voltage VTHN is the threshold voltage corresponding to the NMOS transistor.

[0042] The second control voltage VRN2 is greater than the sum of the first threshold voltage VTHN and the second low-level potential VSSL. That is, the second control voltage VRN2 satisfies the following condition 2:

[0043] VRN2 > VTHN + VSSL Condition 2

[0044] Under the control of the control unit 232, transistors of the same type in the first input unit 231, the control unit 232, and the output unit 234 have the same withstand voltage value, reducing the production cost of the level conversion circuit 200. The control unit 232 includes a first control transistor MP1, a second control transistor MP2, a third control transistor MN3, and a fourth control transistor MN4. During the operation of the level conversion circuit 200, the third control transistor MN3 and the fourth control transistor MN4 are always in the on state. Simultaneously, the first control voltage VRN1 dynamically adjusts the static current within the level conversion circuit 200 based on the first threshold voltage of the second input transistor MN2 and the second threshold voltage of the second control transistor MP2. The control terminals of the first control transistor MP1 and the second control transistor MP2 receive the first control voltage VRN1. The first connection terminal of the first control transistor MP1 is electrically connected to the second connection terminal of the first input transistor MN1, and the first connection terminal of the second control transistor MP2 is electrically connected to the second connection terminal of the second input transistor MN2. The second connection terminal of the first control transistor MP1 is electrically connected to the first connection terminal of the third control transistor MN3 through the positive output terminal Q, and the second connection terminal of the second control transistor MP2 is electrically connected to the first connection terminal of the fourth control transistor MN4 through the inverted output terminal QB. The control terminals of the third control transistor MN3 and the fourth control transistor MN4 receive the second control voltage VRN2, and the second connection terminals of the third control transistor MN3 and the fourth control transistor MN4 are electrically connected to the output unit 234. In at least one embodiment of the present invention, the first control transistor MP1 and the second control transistor MP2 are PMOS transistors, the third control transistor MN3 and the fourth control transistor MN4 are NMOS transistors, the control terminal is the gate, the first connection terminal is the source, and the second connection terminal is the drain. In at least one embodiment of the present invention, the first threshold voltage is the threshold voltage of the second input transistor MN2, and the second threshold voltage is the threshold voltage of the second control transistor MP2.

[0045] The output unit 234 is used to output the converted output signal in the second voltage domain. The output unit 234 includes a first output transistor MN5 and a second output transistor MN6. The control terminal of the first output transistor MN5 is electrically connected to the inverting output terminal QB, and the first connection terminal of the first output transistor MN5 is electrically connected to the second connection terminal of the third control transistor MN3. The second connection terminal of the first output transistor MN5 receives the second low-level potential VSSL. The control terminal of the second output transistor MN6 is electrically connected to the positive output terminal Q, and the first connection terminal of the second output transistor MN6 is electrically connected to the second connection terminal of the fourth control transistor MN4, receiving the second low-level potential VSSL. In at least one embodiment of the present invention, the first output transistor MN5 and the second output transistor MN6 can be NMOS transistors, with the control terminal being the gate, the first connection terminal being the source, and the second connection terminal being the drain.

[0046] Please see Figure 4 This is a circuit diagram of the first control voltage generation circuit 300a according to the first embodiment. The first control voltage generation circuit 300a is used to generate the first control voltage VRN1. The first control voltage VRN1 is a dynamic voltage. The first control voltage generation circuit 300a includes a first transistor MNR1, a second transistor MPR1, and a reference current source IREF. The control terminal and the first connection terminal of the first transistor MNR1 are electrically connected to the second high-level potential VDDL, and the second connection terminal of the first transistor MNR1 is electrically connected to the first connection terminal of the second transistor MPR1. The control terminal of the second transistor MPR1 is electrically connected to the second connection terminal of the second transistor MPR1, and the control terminal of the second transistor MPR1 further serves as the output terminal of the first control voltage VRN1. The second connection terminal of the second transistor MPR1 is electrically connected to the second low-level potential VSSL through the reference current source IREF. In at least one embodiment of the present invention, the first transistor MNR1 is an NMOS transistor, and the second transistor MPR1 is a PMOS transistor.

[0047] In at least one embodiment of the present invention, the first control voltage VRN1 satisfies the following formula:

[0048] VRN1 = VDDL - VTHP - VTHN (Formula 1)

[0049] Wherein, VRN1 represents the first control voltage VRN1, VDDL represents the second high-level potential; VTHN represents the threshold voltage of the second input transistor MN2, and VTHP represents the threshold voltage of the second control transistor MP2.

[0050] Please see Figure 5 This is a circuit diagram of the first control voltage generation circuit 300b according to the second embodiment. The first control voltage generation circuit 300b is used to generate the first control voltage VRN1. The first control voltage generation circuit 300b includes a first transistor MNR1, a second transistor MPR1, and a reference current source IREF. The control terminal of the first transistor MNR1 is electrically connected to the control terminal of the second transistor MPR1, and further serves as the output terminal of the first control voltage VRN1. The first connection terminal of the first transistor MNR1 is electrically connected to the second connection terminal and the control terminal of the second transistor MPR1, and the second connection terminal of the first transistor MNR1 is electrically connected to the second low-level potential VSSL. The first connection terminal of the second transistor MPR1 is electrically connected to the second high-level potential VDDL. In at least one embodiment of the present invention, the first transistor MNR1 is an NMOS transistor, and the second transistor MPR1 is a PMOS transistor.

[0051] The working principle of the level conversion circuit 200 is as follows:

[0052] When the input terminal DIN receives the first low-level potential VSSH of the first voltage domain, the control terminal of the first input transistor MN1 receives the first low-level potential VSSH of the first voltage domain, and the first input transistor MN1 is in the off state. The control terminal of the second input transistor MN2 receives the first high-level potential VDDH of the first voltage domain, and the second input transistor MN2 is in the on state. The voltage at the first connection terminal of the second control transistor MP2 is the difference between the second high-level potential VDDL and the first threshold voltage. Since the first control voltage VRN1 is less than the difference between the second high-level potential VDDL and the first threshold voltage, the second control transistor MP2 is in the on state. The third control transistor MN3 and the fourth control transistor MN4 are in the on state under the control of the second control voltage VRN2. The first output transistor MN5 is in the on state, and the second output transistor MN6 is in the off state. The potential of the positive output terminal Q is the second low-level potential VSSL.

[0053] When the input terminal DIN receives the first high-level potential VDDH of the first voltage domain, the control terminal of the first input transistor MN1 receives the first high-level potential VDDH of the first voltage domain, and the first input transistor MN1 is in the on state. The voltage at the first connection terminal of the first control transistor MP1 is the difference between the second high-level potential VDDL and the first threshold voltage. The control terminal of the second input transistor MN2 receives the first low-level potential VSSH of the first voltage domain, and the second input transistor MN2 is in the off state. Since the first control voltage VRN1 is less than the difference between the second high-level potential VDDL and the first threshold voltage, the first control transistor MP1 is in the on state. The third control transistor MN3 and the fourth control transistor MN4 are in the on state under the control of the second control voltage VRN2. The first output transistor MN5 is in the off state, and the second output transistor MN6 is in the on state. The potential of the positive output terminal Q is the second high-level potential VDDL.

[0054] The level conversion circuit 200 and electronic device 1 described above use a separate second voltage domain circuit 23 to directly convert the input signal from the first voltage domain to the second voltage domain, reducing the complexity of the level conversion circuit 200, improving signal conversion speed, and reducing signal delay time. Simultaneously, the control unit 232 clamps the voltage domains of the input unit 231 and the output unit 234, preventing transistors of the same type in the second voltage domain circuit 23 from being damaged, reducing production costs while ensuring normal system operation. Furthermore, by associating the first control voltage VRN1 with the first threshold voltage and the second threshold voltage within the second voltage domain circuit 23, the problem of excessive static current caused by process deviations can be reduced.

[0055] Those skilled in the art should recognize that the above embodiments are merely illustrative of the present invention and are not intended to limit the present invention. Any appropriate changes and variations made to the above embodiments within the essential spirit and scope of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. An electronic device, characterized in that, The level conversion circuit and the first control voltage generation circuit are included. The level conversion circuit is configured to convert a signal in a first voltage domain into a signal in a second voltage domain. The level conversion circuit includes: A first voltage domain circuit configured to receive an input signal in a first voltage domain; the input signal is switched between a first high level potential and a first low level potential; A second voltage domain circuit configured to convert the input signal into an output signal in a second voltage domain; the second voltage domain signal is switched between a second high level potential and a second low level potential; the first high level potential is different from the second high level potential, the first low level potential is different from the second low level potential, and the second high level potential is less than or equal to the first low level potential; The second voltage domain circuit includes a plurality of transistors, which form an input unit, a control unit, and an output unit; the control unit is configured to clamp the voltage domains of the input unit and the output unit in a preset range according to a first control voltage and a second control voltage, so as to avoid the same type of transistors in the second voltage domain circuit from being broken down; The first control voltage is generated by the first control voltage generation circuit, which includes a first transistor, a second transistor, and a reference current source; the control end and the first connection end of the first transistor are electrically connected with the second high level potential, and the second connection end of the first transistor is electrically connected with the first connection end of the second transistor; the control end of the second transistor is electrically connected with the second connection end of the second transistor, and the control end of the second transistor further serves as an output end of the first control voltage; the second connection end of the second transistor is electrically connected with the second low level potential through the reference current source; the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor; The lower limit threshold of the preset range is a difference between the first control voltage and a first threshold voltage, and the upper limit threshold of the preset range is a difference between the second control voltage and a second threshold voltage. The control unit comprises a first control transistor, a second control transistor, a third control transistor and a fourth control transistor; during operation of the level conversion circuit, the third control transistor and the fourth control transistor are always in an on state; a control end of the first control transistor and a control end of the second control transistor receive the first control voltage, a first connection end of the first control transistor is electrically connected with the input unit, a first connection end of the second control transistor is electrically connected with the input unit, a second connection end of the first control transistor is electrically connected with a first connection end of the third control transistor through a forward output end, and a second connection end of the second control transistor is electrically connected with a first connection end of the fourth control transistor through a reverse output end; a control end of the third control transistor and a control end of the fourth control transistor receive the second control voltage, and a second connection end of the third control transistor and a second connection end of the fourth control transistor are electrically connected with the output unit. 2.The electronic device of claim 1, wherein, The first control voltage is a dynamic voltage, which is used to dynamically adjust a static current in the level conversion circuit according to a first threshold voltage of the transistor in the input unit and a second threshold voltage of the transistor in the control unit. 3.The electronic device of claim 2, wherein, The input unit comprises a first input transistor and a second input transistor; a control end of the first input transistor receives a first output signal output by the first voltage domain circuit, a control end of the second input transistor receives a second output signal output by the first voltage domain circuit, a first connection end of the first input transistor and a first connection end of the second input transistor receive the second high-level potential, a second connection end of the first input transistor is electrically connected with a first connection end of the first control transistor, and a second connection end of the second input transistor is electrically connected with a first connection end of the second control transistor. 4.The electronic device of claim 3, wherein, The first control voltage satisfies the formula: VRN1=VDDL-VTHP-VTHN; wherein VRN1 represents the first control voltage VRN1, VDDL represents the second high-level potential, VTHN represents a threshold voltage of the second input transistor, and VTHP represents a threshold voltage of the second control transistor. 5.The electronic device of claim 3, wherein, The first control voltage is greater than a first numerical value and less than a second numerical value; the first numerical value is obtained by subtracting a first threshold voltage from the first low-level potential and then subtracting a second threshold voltage; the second numerical value is obtained by subtracting the first threshold voltage from the second high-level potential and then subtracting the second threshold voltage; and the second control voltage is greater than a sum of the first threshold voltage and the second low-level potential.

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