Semiconductor element with programmable cell and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element includes a substrate, a first conductive layer over the substrate, a bottom conductive layer over the first conductive layer and electrically coupled to the first conductive layer, a programmable insulating layer over the bottom conductive layer, a top conductive layer over the programmable insulating layer, and a redistribution structure over the first conductive layer and electrically coupled to the first conductive layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together form a programmable cell.

Description

[0001] Cross-referencing

[0002] This disclosure claims priority and benefits to U.S. Official Application No. 17 / 107,001, filed November 30, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having a programmable unit and a method for fabricating the same. Background Technology

[0004] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demand for computing power. However, various problems arise during the miniaturization process, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device, including: a substrate; a first conductive layer located above the substrate; a bottom conductive layer located above the first conductive layer and electrically coupled to the first conductive layer; a programmable insulating layer located on the bottom conductive layer; a top conductive layer located on the programmable insulating layer; and a redistribution structure located above the first conductive layer and electrically coupled to the first conductive layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together constitute a programmable unit.

[0007] In some embodiments, the bottom conductive layer and the redistribution structure are at the same vertical level.

[0008] In some embodiments, the bottom conductive layer and the programmable insulating layer have the same width.

[0009] In some embodiments, the width of the programmable insulating layer is equal to or greater than the width of the bottom conductive layer.

[0010] In some embodiments, the semiconductor device includes a spike portion located on the bottom conductive layer. The programmable insulating layer is located on the bottom conductive layer and the spike portion.

[0011] In some embodiments, a vertical level of the redistribution structure is higher than a vertical level of the programmable unit.

[0012] In some embodiments, the redistribution structure includes a redistribution conductive layer and a heat release layer. The redistribution conductive layer is located above and electrically coupled to the first conductive layer, and the heat release layer is located on the redistribution conductive layer.

[0013] In some embodiments, the redistribution conductive layer includes a seed layer and an electroplated layer. The seed layer is located above and electrically coupled to the first conductive layer, and the electroplated layer is located on the seed layer.

[0014] In some embodiments, the heat release layer comprises an organic material that is interstitially mixed with a plurality of carbon nanotubes.

[0015] In some embodiments, the heat release layer comprises a fluoropolymer material intermittently mixed with a plurality of carbon nanotubes.

[0016] In some embodiments, the aspect ratio of these carbon nanotubes is between about 1:1 and about 1:100.

[0017] In some embodiments, the semiconductor device includes a barrier layer located beneath the redistribution conductive layer. The barrier layer includes titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof.

[0018] In some embodiments, the thickness of the barrier layer is between about 10 angstroms and about 15 angstroms.

[0019] In some embodiments, the semiconductor device includes an adjustment layer located between the barrier layer and the redistribution conductive layer. The adjustment layer includes graphene or graphite.

[0020] In some embodiments, the heat release layer is configured to maintain a thermal resistance between about 0.04 °C / cm². 2 / Watt to approximately 0.25℃cm 2 Between / Watt.

[0021] In some embodiments, the redistribution conductive layer comprises tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof.

[0022] Another embodiment of this disclosure provides a semiconductor device, including: a substrate; a first conductive layer located above the substrate; a second conductive layer located at the same vertical level as the first conductive layer; a bottom conductive layer located above the second conductive layer and electrically coupled to the second conductive layer; a programmable insulating layer located on the bottom conductive layer; a top conductive layer located on the programmable insulating layer; and a redistribution structure located above the first conductive layer and electrically coupled to the first conductive layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together constitute a programmable unit.

[0023] Another embodiment of this disclosure provides a semiconductor device, including: a substrate; a first conductive layer located above the substrate; a second conductive layer located at the same vertical level as the first conductive layer; a redistribution structure including a redistribution overlap portion located on the first conductive layer, a redistribution contact portion located on the second conductive layer, and a redistribution connection portion connecting the redistribution overlap portion and the redistribution contact portion; a programmable insulating layer located on the redistribution overlap portion; and a top conductive layer located on the programmable insulating layer. The redistribution overlap portion, the programmable insulating layer, and the top conductive layer together constitute a programmable unit.

[0024] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a first conductive layer over the substrate; simultaneously forming a bottom conductive layer and a redistribution structure over the first conductive layer; forming a programmable insulating layer on the bottom conductive layer; and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together constitute a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.

[0025] In some embodiments, the programmable insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0026] Due to the design of the semiconductor device disclosed herein, programmable cells and redistribution structures can be integrated as programmable features of the semiconductor device. Furthermore, the presence of spikes improves the programming reliability of the semiconductor device.

[0027] The technical features and advantages of this disclosure have been summarized quite extensively above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages forming the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0028] This disclosure can be read in conjunction with the following figures and detailed description for better understanding. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0029] Figures 1 to 9 A schematic cross-sectional view of a semiconductor element exemplifying some embodiments of this disclosure is shown.

[0030] Figure 10 A flowchart illustrating a method for fabricating a semiconductor element according to some embodiments of this disclosure is provided.

[0031] Figures 11 to 15 A cross-sectional schematic diagram illustrating the fabrication process of a semiconductor device according to some embodiments of this disclosure.

[0032] Figures 16 to 18 A cross-sectional schematic diagram illustrating the fabrication process of a semiconductor device according to another embodiment of the present disclosure.

[0033] Figure 19 A flowchart illustrating a method for fabricating a semiconductor element according to another embodiment of this disclosure.

[0034] Figure 20 A cross-sectional schematic diagram illustrating a portion of the fabrication process of a semiconductor element according to another embodiment of the present disclosure.

[0035] Figure 21 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0036] Figure 22 show Figure 21 A close-up top view of the intermediate semiconductor element in the CU region.

[0037] Figure 23 It is along Figure 22 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0038] Figure 24 show Figure 21A close-up top view of the intermediate semiconductor element in the CU region.

[0039] Figure 25 It is along Figure 24 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0040] Figure 26 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0041] Figure 27 show Figure 26 A close-up top view of the intermediate semiconductor element in the CU region.

[0042] Figure 28 It is along Figure 27 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0043] Figure 29 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0044] Figure 30 show Figure 29 A close-up top view of the intermediate semiconductor element in the CU region.

[0045] Figure 31 It is along Figure 30 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0046] Figure 32 It is along Figure 30 A schematic diagram of the cross section drawn by line B-B' in the diagram.

[0047] Explanation of reference numerals in the attached figures:

[0048] 1A: Semiconductor components

[0049] 1B: Semiconductor components

[0050] 1C: Semiconductor components

[0051] 1D: Semiconductor components

[0052] 1E: Semiconductor components

[0053] 1F: Semiconductor components

[0054] 1G: Semiconductor components

[0055] 1H: Semiconductor components

[0056] 1I: Semiconductor components

[0057] 10: Preparation method

[0058] 20: Preparation method

[0059] 30: Programmable Unit

[0060] 40: Redistributed Structure

[0061] 101: Substrate

[0062] 103: Interlayer Structure

[0063] 105: Components and parts

[0064] 107-1: First conductive layer

[0065] 107-3: Second conductive layer

[0066] 107-5: Third conductive layer

[0067] 109-1: First conductive via

[0068] 109-3: Second conductive via

[0069] 201: Insulation layer

[0070] 203: Insulation layer

[0071] 205: Insulation layer

[0072] 207: Insulation layer

[0073] 209: Insulation layer

[0074] 209SW: Sidewall

[0075] 211: Intermediary Layer

[0076] 213: Overlay

[0077] 213BE: Bottom Edge

[0078] 213SW: Sidewall

[0079] 301: Bottom conductive layer

[0080] 303: Programmable insulating layer

[0081] 303-1: Flat section

[0082] 303-3: Coverage Area

[0083] 305: Top conductive layer

[0084] 307: Peak Section

[0085] 307-1: First minor plane

[0086] 307-3: Second minor plane

[0087] 307T: Vertex

[0088] 401: Redistribution of conductive layer

[0089] 401-1: Seed Layer

[0090] 401-3: Electroplating layer

[0091] 403: Barrier layer

[0092] 405: Adjustment Layer

[0093] 407: Heat release layer

[0094] 409: Redistribution of overlapping regions

[0095] 409CSW-1: First curved sidewall

[0096] 409CSW-3: Second curved sidewall

[0097] 409E-1: First Extension Section

[0098] 409E-3: Second Extension Section

[0099] 409SW-1: Third sidewall

[0100] 409SW-3: Fourth sidewall

[0101] 411: Redistributed Connectivity

[0102] 413: Redistribution contact portion

[0103] 501: First Opening

[0104] 503: Second opening

[0105] 503BE: Bottom Edge

[0106] 503TE: Top Edge

[0107] 601: First conductive material

[0108] 603: First mask layer

[0109] 605: Second Cover Layer

[0110] 605CSW-1: Higher bending sidewall

[0111] 605CSW-3: Lower bending sidewall

[0112] 605O: Curtain Opening

[0113] D1: Distance

[0114] D2: Distance

[0115] D3: Distance

[0116] D4: Distance

[0117] R1: First Region

[0118] R2: Second Region

[0119] S11: Steps

[0120] S13: Steps

[0121] S15: Steps

[0122] S21: Steps

[0123] S23: Steps

[0124] S25: Steps

[0125] S27: Steps

[0126] S29: Steps

[0127] W1: Width

[0128] W2: Width

[0129] W3: Width

[0130] X: Direction

[0131] Y: direction

[0132] Z: Direction Detailed Implementation

[0133] The following disclosure provides numerous different embodiments or examples of various components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to limit the relationship between the different embodiments and / or structures discussed.

[0134] Furthermore, spatial terms used here, such as "below," "below," "lower," "above," "higher," and similar terms, are used to facilitate the description of the relationship between one element or component shown in the accompanying drawings and another element or component. These spatial relation terms are used to cover different orientations of elements in use or operation, other than those depicted in the accompanying drawings. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial relation adjectives used therein can be interpreted in the same way.

[0135] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be a direct connection or coupling to another component or layer, or there may be an intermediate component or layer.

[0136] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0137] Unless the context otherwise indicates, the use of terms such as “same,” “equal,” “planar,” or “coplanar” in reference to orientation, layout, location, shape, size, quantity, or other measures does not necessarily imply identical orientation, layout, location, shape, size, quantity, or other measures, but is intended to cover orientation, layout, location, shape, size, quantity, or other measures that are substantially identical, for example, due to manufacturing processes, within acceptable variations. The term “substantially” may be used in this document to reflect this meaning. For example, items described as “substantially same,” “substantially equal,” or “substantially planar” may be exactly the same, equal, or planar, or may be the same, equal, or planar, for example, due to manufacturing processes, within acceptable variations.

[0138] Figure 1 A schematic cross-sectional view of a semiconductor device 1A illustrating some embodiments of this disclosure is shown. (Refer to...) Figure 1 Semiconductor element 1A may include substrate 101, interlayer structure 103, device elements 105, first conductive layer 107-1, first conductive via 109-1, second conductive via 109-3, insulating layers 201, 203, 205, 207, programmable unit 30, and redistribution structure 40.

[0139] Reference Figure 1The substrate 101 may be a bulk semiconductor substrate. For example, the bulk semiconductor substrate may include elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors.

[0140] Reference Figure 1 Interlayer structure 103 can be disposed on substrate 101. Interlayer structure 103 may include a dielectric, an insulating layer, and conductive components disposed on a bulk semiconductor substrate. The dielectric or insulating layer may include, for example, semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, tetraethylorthosilicate oxide, phosphosilica glass, borophosphosilicate glass, fluorinated silica glass, carbon-doped silicon oxide, amorphous fluorinated carbon, or combinations thereof. The conductive components may be wires, conductive vias, conductive contacts, or the like. The dielectric or insulating layer may act as an insulator to support and electrically isolate the conductive components.

[0141] In some embodiments, component 105 (only one is shown for clarity) may be disposed in interlayer structure 103. Component 105 may be, for example, bipolar junction transistors, metal-oxide-semiconductor field-effect transistors, diodes, system large-scale integration, flash memory, dynamic random access memory, static random access memory, electrically erasable programmable read-only memory, image sensors, microelectromechanical systems, active components, or passive components.

[0142] Reference Figure 1Insulating layers 201, 203, 205, and 207 may be stacked on the interlayer structure 103. In some embodiments, insulating layers 201, 203, 205, and 207 may include, for example, semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, tetraethoxysilane oxides, phosphosilicate glass, borosilicate glass, fluorosilicone glass, carbon-doped silicon oxide, amorphous fluorinated carbon, or combinations thereof. In some embodiments, insulating layers 201, 203, 205, and 207 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, polyimide, polybenzoxazole, phosphosilicate glass, undoped silicate glass, or fluorosilicone glass. In some embodiments, insulating layers 201, 203, 205, and 207 may be passivation layers of semiconductor device 1A. In some embodiments, insulating layer 207 may serve as a high vapor barrier to prevent moisture from entering from above.

[0143] Reference Figure 1 The first conductive layer 107-1 may be disposed within the insulating layer 201. The first conductive layer 107-1 may be electrically coupled to the element component 105 through the conductive components of the interlayer structure 103. In some embodiments, the first conductive layer 107-1 may be a pad layer of the semiconductor element 1A. In some embodiments, the first conductive layer 107-1 may include copper, aluminum, titanium, tungsten, similar materials, or combinations thereof. In some embodiments, the first conductive layer 107-1 may include, for example, aluminum, copper, aluminum-copper alloys, aluminum alloys, or copper alloys.

[0144] Reference Figure 1 The first conductive via 109-1 and the second conductive via 109-3 can be disposed in the insulating layer 203 and on the first conductive layer 107-1. The first conductive via 109-1 and the second conductive via 109-3 can be electrically connected to the first conductive layer 107-1, respectively. In some embodiments, the sidewalls of the first conductive via 109-1 and the second conductive via 109-3 can have an inclined cross-sectional profile. In some embodiments, the first conductive via 109-1 and the second conductive via 109-3 can include, for example, tungsten, copper, cobalt, ruthenium, molybdenum, titanium, tin, nickel, gold, aluminum, platinum, or combinations thereof.

[0145] Reference Figure 1The programmable unit 30 can be disposed on the first conductive via 109-1. The programmable unit 30 can include a bottom conductive layer 301, a programmable insulating layer 303, and a top conductive layer 305. The bottom conductive layer 301 can be disposed in the insulating layer 205 and disposed on the first conductive via 109-1. The bottom conductive layer 301 can be electrically coupled to the first conductive layer 107-1 through the first conductive via 109-1. The top surface of the bottom conductive layer 301 can be substantially coplanar with the top surface of the insulating layer 205. The bottom conductive layer 301 can include, for example, silicon, germanium, doped silicon, doped silicon-germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0146] Reference Figure 1 A programmable insulating layer 303 may be disposed on the bottom conductive layer 301 and within the insulating layer 207. The width W1 of the programmable insulating layer 303 may be the same as the width of the bottom conductive layer 301. In some embodiments, the thickness of the programmable insulating layer 303 may be between about 5 nm and about 100 nm. The thickness of the programmable insulating layer 303 may determine its programming current or programming voltage during the programming step. The programmable insulating layer 303 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or combinations thereof. Before programming the semiconductor device 1A, the programmable insulating layer 303 can electrically insulate or isolate the bottom conductive layer 301 and the top conductive layer 305.

[0147] Reference Figure 1 The top conductive layer 305 may be disposed on the programmable insulating layer 303. The top conductive layer 305 may have the same width as the programmable insulating layer 303. The top surface of the top conductive layer 305 may be substantially coplanar with the top surface of the insulating layer 207. The top conductive layer 305 may include, but is not limited to, the same material as the bottom conductive layer 301.

[0148] Reference Figure 1The redistribution structure 40 can be disposed in the insulating layer 205 and on the second conductive via 109-3. The redistribution structure 40 can be electrically coupled to the first conductive layer 107-1 through the second conductive via 109-3. The top surface of the redistribution structure 40 can be substantially coplanar with the top surface of the bottom conductive layer 301. In some embodiments, the redistribution structure 40 and the bottom conductive layer 301 can be formed simultaneously. That is, the redistribution structure 40 can include the same material as the bottom conductive layer 301. The redistribution structure 40 and the bottom conductive layer 301 can be configured horizontally. In some embodiments, the redistribution structure 40 can include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

[0149] The redistribution structure 40, the second conductive via 109-3, the first conductive layer 107-1, the first conductive via 109-1, and the programmable unit 30 together constitute a programmable component resembling an anti-fuse. The anti-fuse initially has high resistance and is designed to permanently generate conductive paths.

[0150] During programming of semiconductor element 1A, a programming voltage can be supplied and applied to semiconductor element 1A through redistribution structure 40 and top conductive layer 305. By applying a sufficient programming voltage, the electric field induced by the programming voltage can break down the programmable insulating layer 303 to form a break point in the programmable insulating layer 303. Accordingly, the resistance of programmable cell 30 can be reduced, and a conductive path can be permanently generated.

[0151] Figures 2 to 9 Schematic cross-sectional views of semiconductor elements 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I illustrating some embodiments of this disclosure. See also... Figure 2 Semiconductor element 1B can have similar characteristics to... Figure 1 The structure shown. Figure 2 Zhongyu Figure 1 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0152] like Figure 2 As shown, the width of the programmable insulating layer 303 can be greater than the width of the bottom conductive layer 301 and the width of the top conductive layer 305. For example, the programmable insulating layer 303 can be configured to simultaneously cover the bottom conductive layer 301 and a portion of the redistribution structure 40. As another example, the programmable insulating layer 303 can be configured to cover the entire insulating layer 205.

[0153] Reference Figure 3 Semiconductor element 1C can have similar characteristics to Figure 1 The structure shown. Figure 3 Zhongyu Figure 1Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0154] Reference Figure 3 The spike portion 307 may be disposed on the bottom conductive layer 301. The spike portion 307 may have a triangular cross-sectional profile and may include a first faceted plane 307-1 and a second faceted plane 307-3 that intersect each other. In some embodiments, the spike portion 307 may have a rhomboid, pentagonal, or cross-sectional profile with more than five sides. The spike portion 307 may include, for example, silicon, germanium, silicon germanium, silicon carbide, silicon germanium carbide, gallium, gallium arsenide, indium arsenide, indium phosphide, or other group IV-IV, III-V, or II-VI semiconductor materials.

[0155] Reference Figure 3 A programmable insulating layer 303 can be disposed on the spike portion 307. The programmable insulating layer 303 may include two flat portions 303-1 and a cover portion 303-3. The cover portion 303-3 can be disposed on the first small plane 307-1 and the second small plane 307-3. The two flat portions 303-1 can be respectively connected to the two ends of the cover portion 303-3. The two flat portions 303-1 can be disposed on the top surface of the bottom conductive layer 301. The thickness of the two flat portions 303-1 can be greater than or equal to the thickness of the cover portion 303-3.

[0156] During programming of semiconductor device 1C, the apex 307T of the spike portion 307 may be the most vulnerable part because the electric field is concentrated at the sharp contour. Since the apex 307T of the spike portion 307 receives the highest electric field, the programmable insulating layer 303 can be broken down to form a breakpoint in the cover portion 303-3 adjacent to the apex 307T of the spike portion 307, thereby inducing a decrease in resistance. Thus, semiconductor device 1C is burned out and programmed. During programming, the location of the breakpoint in the cover portion 303-3 can be easily limited to the location adjacent to the apex 307T of the spike portion 307 with the highest electric field. As a result, the programming reliability of semiconductor device 1C can be increased.

[0157] Reference Figure 4 In the semiconductor device 1D, the substrate 101, interlayer structure 103, device component 105, first conductive layer 107-1, first conductive via 109-1, insulating layers 201 and 203, and programmable unit 30 may have the same characteristics as those in the semiconductor device 1D. Figure 1 The structure shown can include structures similar to those described above. Figure 1 The same material as shown.

[0158] Reference Figure 4Insulating layers 205, 207, and 209 may be stacked on insulating layer 203. Programmable unit 30 may be disposed within insulating layer 205. The top surface of top conductive layer 305 may be substantially coplanar with the top surface of insulating layer 205. In some embodiments, insulating layers 205, 207, and 209 may be passivation layers of semiconductor device 1D. In some embodiments, insulating layers 205, 207, and 209 may comprise, but are not limited to, the same material as insulating layer 203.

[0159] Reference Figure 4 An intervening layer 211 may be disposed between insulating layers 205 and 207. In some embodiments, the intervening layer 211 may be an etch stop layer of the semiconductor device 1D. The intervening layer 211 may include, for example, carbon-doped oxide, carbon-containing silicon oxide, nitrogen-doped silicon carbide, or a combination thereof. In some embodiments, the thickness of the intervening layer 211 may be between about 10 nm and about 200 nm. In some embodiments, the thickness of the intervening layer 211 may be set to any range as appropriate.

[0160] Reference Figure 4 The second conductive via 109-3 can be disposed along the interposer layer 211, the insulating layer 205, and the insulating layer 203 and disposed on the first conductive layer 107-1. The second conductive via 109-3 can be electrically connected to the first conductive layer 107-1. The second conductive via 109-3 can include, but is not limited to, the same material as the first conductive via 109-1.

[0161] Reference Figure 4 The second conductive layer 107-3 can be disposed on the intermediate layer 211 and the second conductive via 109-3. In other words, the vertical level of the second conductive layer 107-3 can be higher than the vertical level of the programmable unit 30. The top surface of the second conductive layer 107-3 can be substantially coplanar with the top surface of the insulating layer 207. A portion of the top surface of the second conductive layer 107-3 can be exposed through an opening in the insulating layer 209. The second conductive layer 107-3 can include, but is not limited to, the same material as the first conductive layer 107-1. The second conductive layer 107-3 can be electrically coupled to the first conductive layer 107-1 through the second conductive via 109-3.

[0162] Reference Figure 4 The redistribution structure 40 can be conformally disposed on the second conductive layer 107-3 and the insulating layer 209. That is, the vertical level of the redistribution structure 40 can be higher than the vertical level of the programmable unit 30. The redistribution structure 40 can be electrically coupled to the first conductive layer 107-1 through the second conductive layer 107-3 and the second conductive via 109-3.

[0163] During programming of the semiconductor element 1D, a programming voltage can be supplied and applied to the semiconductor element 1D through the redistribution structure 40 and the top conductive layer 305. By applying a sufficient programming voltage, the electric field induced by the programming voltage can break down the programmable insulating layer 303 to form a break point in the programmable insulating layer 303. Accordingly, the resistance of the programmable cell 30 can be reduced, and a conductive path can be permanently generated.

[0164] Reference Figure 5 Semiconductor element 1E can have similar characteristics to Figure 4 The structure shown. Figure 5 Zhongyu Figure 4 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0165] Reference Figure 5 The redistribution structure 40 may include a redistribution conductive layer 401. The redistribution conductive layer 401 may be a stacked layer including a seed layer 401-1 and an electroplated layer 401-3. The seed layer 401-1 may be conformally disposed on the second conductive layer 107-3 and the insulating layer 209. The electroplated layer 401-3 may be disposed on the seed layer 401-1. The electroplated layer 401-3 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

[0166] Reference Figure 6 Semiconductor element 1F can have similar characteristics to Figure 5 The structure shown. Figure 6 Zhongyu Figure 5 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0167] Reference Figure 6 The redistribution structure 40 may include a barrier layer 403, an adjustment layer 405, and a redistribution conductive layer 401. The barrier layer 403 may be conformally disposed on the second conductive layer 107-3 and the insulating layer 209. In some embodiments, the thickness of the first barrier layer 401 may be between about 10 angstroms and about 15 angstroms. The barrier layer 403 may include, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or combinations thereof. The barrier layer 403 may serve as an adhesive layer between the second conductive layer 107-3 and the redistribution conductive layer 401.

[0168] Reference Figure 6An adjustment layer 405 may be disposed on the barrier layer 403. A redistribution conductive layer 401 may be disposed on the adjustment layer 405. In some embodiments, the adjustment layer 405 may include, for example, graphene, graphite, or similar materials. Because the adjustment layer 405 formed of graphene has good conductivity, the resistance between the redistribution conductive layer 401 and the second conductive layer 107-3 can be reduced. Therefore, the power consumption of the semiconductor device 1F can be reduced.

[0169] Reference Figure 7 Semiconductor element 1G can have similar characteristics to Figure 5 The structure shown. Figure 7 Zhongyu Figure 5 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0170] Reference Figure 7 The capping layer 213 may be conformally disposed on the insulating layer 209 to expose a portion of the top surface of the second conductive layer 107-3. The capping layer 213 may provide additional electrical isolation or insulation for conductive components beneath and above it. In some embodiments, the capping layer 213 may comprise a photosensitive polymer material, such as polyimide. In some embodiments, the capping layer 213 may comprise silicon oxide, silicon nitride, silicon carbide nitride, silicon nitride oxide, or silicon oxynitride.

[0171] Reference Figure 7 The redistribution structure 40 may include a redistribution conductive layer 401 and a heat release layer 407. The redistribution conductive layer 401 may be conformally disposed on the second conductive layer 107-3 and the capping layer 213. The heat release layer 407 may be disposed on the redistribution conductive layer 401. The heat release layer 407 may include a carbon material filled with a flexible material such as a polymer matrix. For example, the heat release layer 407 may include generally vertically oriented graphite and carbon nanotubes filled with a fluoropolymer rubber matrix. The aspect ratio of the carbon nanotubes may be between about 1:1 and about 1:100. As another example, the heat release layer 407 may include graphitic carbon.

[0172] In some embodiments, when the thickness of the heat release layer 407 is between about 250 μm and about 450 μm, its thermal resistance can be less than 0.2 °C / cm². 2 / Watt. In some embodiments, the thermal resistance of the heat release layer 407 may be between approximately 0.04 °C / cm. 2 / Watt to approximately 0.25℃cm 2 Between / Watt. The heat release layer 407 can improve the heat dissipation capability of the redistribution structure 40.

[0173] Reference Figure 8Semiconductor element 1H can have similar characteristics to Figure 4 The structure shown. Figure 8 Zhongyu Figure 4 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0174] Reference Figure 8 The third conductive layer 107-5 can be disposed within the insulating layer 201. The top surface of the third conductive layer 107-5 can be substantially coplanar with the top surface of the first conductive layer 107-1. The third conductive layer 107-5 can include the same material as the first conductive layer 107-1. The programmable unit 30 can be electrically coupled to the third conductive layer 107-5 through the first conductive via 109-1. During the programming step, the first conductive layer 107-1 and the third conductive layer 107-5 can be electrically coupled through some conductive components of the interlayer structure 103.

[0175] Reference Figure 9 In semiconductor device 1I, substrate 101, interlayer structure 103, device component 105, first conductive layer 107-1, and insulating layer 201 may have the same characteristics as those in semiconductor device 1I. Figure 1 A similar structure is shown. The second conductive layer 107-3 can be disposed in the insulating layer 201. The top surface of the second conductive layer 107-3 can be substantially coplanar with the top surface of the first conductive layer 107-1. The insulating layer 203 can be formed on the insulating layer 201 to expose a portion of the top surface of the first conductive layer 107-1 and a portion of the top surface of the second conductive layer 107-3, respectively.

[0176] Reference Figure 9 The redistribution structure 40 can be conformally disposed on the first conductive layer 107-1, the second conductive layer 107-3, and the insulating layer 203. The redistribution structure 40 may include a redistribution overlapping portion 409, a redistribution connecting portion 411, and a redistribution contact portion 413. The redistribution overlapping portion 409 can be disposed on the first conductive layer 107-1. The redistribution contact portion 413 can be disposed on the second conductive layer 107-3. The redistribution connecting portion 411 can connect the redistribution overlapping portion 409 and the redistribution contact portion 413. The top conductive layer 305 can be disposed on the redistribution overlapping portion 409.

[0177] Reference Figure 9 A programmable insulating layer 303 may be disposed between the redistribution overlap portion 409 and the top conductive layer 305. Before programming the semiconductor element 1I, the programmable insulating layer 303 can electrically insulate or isolate the redistribution overlap portion 409 and the top conductive layer 305.

[0178] The redistribution overlapping portion 409, the programmable insulating layer 303, and the top conductive layer 305 together form a programmable unit 30. The redistribution contact portion 413, the redistribution connection portion 411, and the programmable unit 30 together constitute a programmable component resembling an antifuse.

[0179] During programming of semiconductor element 1I, a programming voltage can be supplied and applied to semiconductor element 1I through redistribution contact portion 413 and top conductive layer 305. By applying a sufficient programming voltage, the electric field induced by the programming voltage can break down programmable insulating layer 303 to form a break point in programmable insulating layer 303. Accordingly, the resistance of programmable cell 30 can be reduced, and a conductive path can be permanently generated.

[0180] Figure 10 A flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to some embodiments of this disclosure is provided. Figures 11 to 15 A cross-sectional schematic diagram illustrating the fabrication process of a semiconductor element 1A according to some embodiments of this disclosure.

[0181] Reference Figure 10 and Figure 11 In step S11, a substrate 101 can be provided, an insulating layer 201 can be formed on the substrate 101, and a first opening 501 can be formed along the insulating layer 201.

[0182] Reference Figure 11 An interlayer structure 103 can be formed on the substrate 101. The interlayer structure 103 may include a dielectric, an insulating layer, and conductive components. Component 105 may be formed in the interlayer structure 103 and electrically coupled to the conductive components of the interlayer structure 103. An insulating layer 201 may be formed on the interlayer structure 103. A first opening 501 may be formed along the insulating layer 201 by a photolithography process and subsequent etching process.

[0183] In some embodiments, a cleaning process and a passivation process can be performed on the first opening 501. The cleaning process removes oxides oxidized by oxygen in the air from the top surface of the topmost conductive component of the interlayer structure 103 without damaging it. The cleaning process may include applying a mixture of hydrogen and argon as a remote plasma source to the first opening 501. The process temperature of the cleaning process may be between about 250°C and about 350°C. The process pressure of the cleaning process may be between about 1 Torr and about 10 Torr. A bias energy may be applied to the device performing the cleaning process. The bias energy may be between about 0 W and 200 W.

[0184] The passivation process may include immersing an intermediate semiconductor device in a precursor such as dimethylaminotrimethylsilane, tetramethylsilane, or similar substances at a process temperature between about 200°C and about 400°C. Ultraviolet radiation may be used to facilitate the passivation process. The passivation process can passivate the sidewalls of the insulating layer 201 exposed by the first opening 501 by sealing the surface pores of the insulating layer 201. The passivation process can reduce unwanted sidewall growth that may affect the electrical characteristics of the semiconductor device 1A. As a result, the performance and reliability of the semiconductor device 1A can be improved.

[0185] Reference Figure 10 and Figure 12 In step S13, a first conductive layer 107-1 can be formed in the first opening 501, and a bottom conductive layer 301 and a redistribution structure 40 can be formed above the first conductive layer 107-1 and can be electrically coupled to the first conductive layer 107-1.

[0186] Reference Figure 12 Insulating layers 203 and 205 can be sequentially formed on insulating layer 201. A first conductive via 109-1 and a second conductive via 109-3 can be formed in insulating layer 203 and can be electrically connected to the first conductive layer 107-1, respectively. A bottom conductive layer 301 can be formed on the first conductive via 109-1 and in insulating layer 205. A redistribution structure 40 can be formed on the second conductive via 109-3 and in insulating layer 205. In some embodiments, the first conductive via 109-1, the second conductive via 109-3, the bottom conductive layer 301, and the redistribution structure 40 can be formed separately. In some embodiments, the first conductive via 109-1, the second conductive via 109-3, the bottom conductive layer 301, and the redistribution structure 40 can be formed simultaneously. For example, the fabrication technique for the first conductive via 109-1, the second conductive via 109-3, the bottom conductive layer 301, and the redistribution structure 40 may include a dual damascene process. The top surfaces of the bottom conductive layer 301 and the redistribution structure 40 can be substantially coplanar. In other words, the redistribution structure 40 and the bottom conductive layer 301 can be located at the same vertical level.

[0187] Reference Figure 10 and Figures 13 to 15 In step S15, a programmable insulating layer 303 can be formed on the bottom conductive layer 301, and a top conductive layer 305 can be formed on the programmable insulating layer 303.

[0188] Please refer to Figure 13A programmable insulating layer 303 can be formed on the insulating layer 205 and cover the bottom conductive layer 301 and the redistribution structure 40. A first conductive material 601 can be formed on the programmable insulating layer 303. The first conductive material 601 may include, for example, doped silicon, doped silicon germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminum compound, or a combination thereof. A first mask layer 603 can be formed on the first conductive material 601. The first mask layer 603 may be a photoresist layer or a hard mask layer. The first mask layer 603 may have a pattern of programmable cells 30 and may be perpendicularly overlapped with the bottom conductive layer 301.

[0189] Reference Figure 14 An etching process, such as anisotropic dry etching, can be performed to remove a portion of the first conductive material 601 and the programmable insulating layer 303. After the etching process, the first conductive material 601 can be transformed into the top conductive layer 305, and the programmable insulating layer 303 can be trimmed. The bottom conductive layer 301, the programmable insulating layer 303, and the top conductive layer 305 together constitute the programmable unit 30.

[0190] Reference Figure 15 An insulating layer 207 can be formed on the insulating layer 205 to cover the redistribution structure 40 and the top conductive layer 305. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent process steps.

[0191] Figures 16 to 18 A cross-sectional schematic diagram illustrating the fabrication process of a semiconductor element 1C according to another embodiment of the present disclosure.

[0192] Reference Figure 16 It can be done through something like Figure 11 and Figure 12 The steps shown are used to fabricate the intermediate semiconductor device. The spike portion 307 can be formed on the bottom conductive layer 301 by, for example, an epitaxial growth process.

[0193] Reference Figure 17 It can be done through something like Figure 13 The steps shown are used to form a programmable insulating layer 303, a first conductive material 601 for that layer, and a first masking layer 603. Planarization processes such as chemical mechanical polishing can be performed to provide a substantially flat surface for subsequent process steps.

[0194] Reference Figure 18 It can be done through something like Figure 14 and Figure 15 The steps shown are used to form the programmable unit 30 and the insulating layer 207.

[0195] Figure 19 A flowchart illustrating a method 20 for fabricating a semiconductor element 1G according to another embodiment of this disclosure. Figure 20 A cross-sectional schematic diagram illustrating a portion of the fabrication process of a semiconductor element 1G according to another embodiment of the present disclosure.

[0196] Reference Figure 19 and Figure 20 In step S21, a substrate 101 can be provided, and a first conductive layer 107-1 can be formed on the substrate 101. A programmable unit 30 can be formed on the first conductive layer 107-1 and can be electrically connected to the first conductive layer 107-1 through a first conductive via 109-1. An intermediate layer 211 can be formed on the programmable unit 30, and a second conductive via 109-3 can be formed along the intermediate layer 211 to be electrically connected to the first conductive layer 107-1.

[0197] Reference Figure 20 It can be done through something like Figure 11 and Figure 12 The steps shown are used to form a substrate 101, an interlayer structure 103, a component 105, a first conductive layer 107-1, and an insulating layer 201. An insulating layer 203 may be formed on the insulating layer 201. A first conductive via 109-1 may be formed along the insulating layer 203 to be electrically connected to the first conductive layer 107-1. A programmable unit 30 may be formed on the first conductive via 109-1. The programmable unit 30 may include a bottom conductive layer 301, a programmable insulating layer 303, and a top conductive layer 305. This can be achieved through methods similar to... Figure 13 and Figure 14 The steps shown are used to form the programmable unit 30.

[0198] Reference Figure 20 An insulating layer 205 may be formed on the insulating layer 203 and cover the programmable cell 30. A planarization process, such as chemical mechanical polishing, may be performed until the top surface of the top conductive layer 305 is exposed to provide a substantially flat surface for subsequent process steps. An interposer layer 211 may be formed on the insulating layer 205 and the programmable cell 30. A second conductive via 109-3 may be formed along the interposer layer 211, the insulating layer 205, and the insulating layer 203 to electrically connect to the first conductive layer 107-1.

[0199] Figure 21 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 22 Example of another embodiment of this disclosure Figure 21 A close-up top view of the intermediate semiconductor element in the CU region. Figure 23 It is along Figure 22 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0200] Reference Figure 19 and Figures 21 to 23 In step S23, a second conductive layer 107-3 may be formed on the second conductive via 109-3, an insulating layer 209 may be formed on the second conductive layer 107-3, and a second opening 503 may be formed along the insulating layer 209 to expose the second conductive layer 107-3.

[0201] Reference Figures 21 to 23 An insulating layer 207 can be formed on the interposer 211. A second conductive layer 107-3 can be formed on the second conductive via 109-3 and in the insulating layer 207. The insulating layer 207 and the second conductive layer 107-3 can be formed by steps similar to those for the insulating layer 201 and the first conductive layer 107-1.

[0202] Reference Figures 21 to 23 An insulating layer 209 can be formed on the insulating layer 207 and the second conductive layer 107-3. A second opening 503 can be formed along the insulating layer 209 using a photolithography process and subsequent etching. A portion of the top surface of the second conductive layer 107-3 can be exposed through the second opening 503. In some embodiments, the second opening 503 may include tapered sidewalls 209SW. In some embodiments, in a cross-sectional perspective view, the tapered sidewalls 209SW may extend from the bottom edge 503BE of the second opening 503 to the top edge 503TE of the second opening 503. In a top perspective view, the bottom edge 503BE of the second opening 503 may be rectangular, and the top edge 503TE of the second opening 503 may also be rectangular. The bottom edge 503BE of the second opening 503 may define the exposed area of ​​the top surface of the second conductive layer 107-3.

[0203] Figure 24 Example of another embodiment of this disclosure Figure 21 A close-up top view of the intermediate semiconductor element in the CU region. Figure 25 It is along Figure 24 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0204] Reference Figure 19 , Figure 24 ,and Figure 25 In step S25, a cover layer 213 may be formed on the insulating layer 209 to expose the second conductive layer 107-3.

[0205] Reference Figure 24 and Figure 25The capping layer 213 may be conformally formed on the insulating layer 209 to expose the exposed top surface of the second conductive layer 107-3. The capping layer 213 may conformally cover the tapered sidewall 209SW of the second opening 503 to form a corresponding tapered sidewall 213SW. The bottom edge 213BE of the capping layer 213 may extend to cover the bottom edge 503BE of the second opening 503 and contact the edge of the exposed top surface of the second conductive layer 107-3.

[0206] Figure 26 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 27 Example of another embodiment of this disclosure Figure 26 A close-up top view of the intermediate semiconductor element in the CU region. Figure 28 It is along Figure 27 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0207] Reference Figure 19 and Figures 26 to 28 In step S27, a second cover layer 605 can be formed on the cover layer 213, and a cover opening 605O can be formed along the second cover layer 605.

[0208] Reference Figures 26 to 28 The second mask layer 605 can be a photoresist layer. Mask openings 605O can define the pattern of the redistribution structure 40. In a top perspective view, mask openings 605O can be spaced apart and can be configured along the Y direction. For ease of description, only one mask opening 605O is described.

[0209] Reference Figure 26 and Figure 27 In the top perspective view, the screen opening 605O may include a horizontally configured higher curved sidewall 605CSW-1 and a lower curved sidewall 605CSW-3. The higher curved sidewall 605CSW-1 may have a convex shape. The lower curved sidewall 605CSW-3 may have a concave shape. The vertical distance parallel to the Y direction between the higher curved sidewall 605CSW-1 and the lower curved sidewall 605CSW-3 may vary along the direction X perpendicular to the Y direction from a relatively narrow distance D1 to a relatively wide distance D2. Therefore, the width parallel to the Y direction between the higher curved sidewall 605CSW-1 of the screen opening 605O and the lower curved sidewall 605CSW-3 of an adjacent screen opening 605O may vary along the direction X from a relatively wide width W2 to a relatively narrow width W3.

[0210] The portion of the second cover layer 605 with a wider width W2 can provide additional structural support to prevent collapse or deformation. In contrast, the portion of the second cover layer 605 with a narrower width W3 may have relatively low resistance to collapse or deformation. That is, the portion of the second cover layer 605 with a narrower width W3 may be relatively fragile. However, the aforementioned structural support can compensate for the relatively fragile portion of the second cover layer 605, suppressing or reducing collapse or deformation of the second cover layer 605. In other words, even if some portions of the cover opening 605O are located on the tapered sidewall 213SW of the cover layer 213, such as... Figure 28 As shown, the second mask layer 605 and the mask opening 605O can be structurally stable. As a result, the subsequently fabricated redistribution structure 40 can have a larger planar area, which represents lower surface resistivity and better electrical transport performance.

[0211] Figure 29 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 30 Example of another embodiment of this disclosure Figure 29 A close-up top view of the intermediate semiconductor element in the CU region. Figure 31 It is along Figure 30 A schematic diagram of the cross section drawn by line A-A' in the diagram. Figure 32 It is along Figure 30 A schematic diagram of the cross section drawn by line B-B' in the diagram.

[0212] Reference Figure 19 and Figures 29 to 32 In step S29, a redistribution structure 40 can be formed in the curtain opening 605O.

[0213] Reference Figures 29 to 32 The redistribution structure 40 can be formed in the mask opening 605O and electrically coupled to the second conductive layer 107-3. In a top perspective view, each redistribution structure 40 can be a conductive pattern extending from a first region R1 to a second region R2. The first region R1 can be spaced apart from the second region R2. In some embodiments, the first region R1 can correspond to the central region of the semiconductor element 1G, and the second region R2 can correspond to the peripheral region or edge region of the semiconductor element 1G.

[0214] Reference Figure 29 and Figure 30In the top perspective view, each redistribution structure 40 may include a redistribution overlap portion 409, a redistribution connection portion 411, and a redistribution contact portion 413. The redistribution overlap portion 409 may be arranged in a row parallel to the Y direction and located in a first region R1. The redistribution contact portion 413 may be arranged in a row parallel to the Y direction and located in a second region R2. The redistribution connection portion 411 may connect the redistribution overlap portion 409 and the redistribution contact portion 413. The redistribution structure 40 may re-route the second conductive layer 107-3 to obtain more space for wiring or bumping and to prevent the second conductive layer 107-3 from being affected by wiring or bumping stress.

[0215] Reference Figure 31 and Figure 32 In a cross-sectional perspective view, each redistribution structure 40 may include a stacked structure. In some embodiments, each redistribution structure 40 may include a redistribution conductive layer 401 and a heat release layer 407. The heat release layer 407 may be formed on the redistribution conductive layer 401. The redistribution conductive layer 401 may include a lower portion of the redistribution overlap portion 409, a lower portion of the redistribution connection portion 411, and a lower portion of the redistribution contact portion 413. The heat release layer 407 may include a higher portion of the redistribution overlap portion 409, a higher portion of the redistribution connection portion 411, and a higher portion of the redistribution contact portion 413.

[0216] Reference Figures 29 to 32 In the top perspective view, the redistribution overlapping portion 409 may include a first curved sidewall 409CSW-1, a second curved sidewall 409CSW-3, a third sidewall 409SW-1, and a fourth sidewall 409SW-3. The first curved sidewall 409CSW-1 may be horizontally configured and may have a convex shape. The second curved sidewall 409CSW-3 may be opposite to the first curved sidewall 409CSW-1 and may have a concave shape. The vertical distance parallel to the direction Y between the first curved sidewall 409CSW-1 and the second curved sidewall 409CSW-3 of the adjacent redistribution overlapping portion 409 may vary along the direction X from a relatively narrow distance D3 to a relatively wide distance D4. The third sidewall 409SW-1 may connect the first edge of the first curved sidewall 409CSW-1 to the first edge of the second curved sidewall 409CSW-3. The fourth sidewall 409SW-3 can connect the second edge of the first curved sidewall 409CSW-1 to the second edge of the second curved sidewall 409CSW-3. The third sidewall 409SW-1 and the fourth sidewall 409SW-3 can be flat and parallel to the direction Y. The redistribution connection portion 411 can connect to the third sidewall 409SW-1.

[0217] Reference Figures 29 to 32 In the cross-sectional perspective view, the first curved sidewall 409CSW-1 can be positioned to overlap with the tapered sidewall 213SW between the top edge 503TE and the bottom edge 503BE. Although most of the first curved sidewall 409CSW-1 is formed to overlap with the tapered sidewall 213SW, the first and second edges of the first curved sidewall 409CSW-1 can be located outside the top edge 503TE to overlap with the flat top surface of the cover layer 213.

[0218] Reference Figure 31 In the cross-sectional perspective view, the redistribution overlap 409 may include a first extension segment 409E-1 extending from the bottom section of the redistribution overlap 409 to the first curved sidewall 409CSW-1. The bottom section may be the portion of the redistribution overlap 409 that is in direct contact with the second conductive layer 107-3.

[0219] Reference Figure 32 The redistribution overlap portion 409 may include a second extension segment 409E-3 extending from the bottom segment to the fourth sidewall 409SW-3. The second extension segment 409E-3 may extend to the outer region of the tapered sidewall 213SW to overlap with the flat top surface of the cover layer 213.

[0220] Reference Figures 29 to 32 The first extension segment 409E-1 and the second extension segment 409E-3 can cover the bottom edge 213BE and the bottom edge 503BE. Therefore, even if the redistribution overlap portion 409 shifts from its normal position due to process changes, the second conductive layer 107-3 can still be covered by the redistribution overlap portion 409. That is, the overlap margin between the redistribution overlap portion 409 and the second conductive layer 107-3 can be increased to significantly suppress or reduce faults that expose the second conductive layer 107-3 after the redistribution overlap portion 409 is formed.

[0221] Due to the design of the semiconductor device disclosed herein, the programmable unit 30 and the redistribution structure 40 can be integrated and can serve as programmable components of the semiconductor device. Furthermore, the presence of the spike portion 307 improves the programming reliability of the semiconductor device 1C.

[0222] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0223] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, matter formations, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future processes, machinery, manufacturing, matter formations, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, matter formations, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A semiconductor element, comprising: One substrate; A first conductive layer is located above the substrate; A bottom conductive layer is located above the first conductive layer and electrically coupled to the first conductive layer; A programmable insulating layer is located on the bottom conductive layer; A top conductive layer is located on the programmable insulating layer; A redistributed structure is located above the first conductive layer and electrically coupled to the first conductive layer; The bottom conductive layer, the programmable insulating layer, and the top conductive layer together constitute a programmable unit. One vertical level of the redistribution structure is higher than one vertical level of the programmable unit. The redistribution structure includes a redistribution conductive layer and a heat release layer. The redistribution conductive layer is located above and electrically coupled to the first conductive layer, and the heat release layer is located on the redistribution conductive layer. The semiconductor device further includes a second conductive layer disposed between the first conductive layer and the redistribution structure, wherein the redistribution structure is electrically coupled to the first conductive layer through the second conductive layer.

2. The semiconductor device of claim 1, wherein the redistribution conductive layer comprises a seed layer and an electroplated layer, the seed layer being located above and electrically coupled to the first conductive layer, and the electroplated layer being located on the seed layer.

3. The semiconductor device of claim 2, wherein the heat release layer comprises an organic material intermittently mixed with a plurality of carbon nanotubes.

4. The semiconductor device of claim 2, wherein the heat release layer comprises a fluoropolymer material intermittently mixed with a plurality of carbon nanotubes.

5. The semiconductor device of claim 3, wherein the aspect ratio of the carbon nanotubes is between 1:1 and 1:

100.

6. The semiconductor device of claim 5 further comprises a barrier layer located below the redistribution conductive layer, wherein the barrier layer comprises titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof.

7. The semiconductor device of claim 6, wherein the thickness of the barrier layer is between 10 angstroms and 15 angstroms.

8. The semiconductor device of claim 7 further includes an adjustment layer located between the barrier layer and the redistribution conductive layer, wherein the adjustment layer comprises graphene or graphite.

9. The semiconductor device of claim 8, wherein the heat release layer is configured to maintain a thermal resistance between 0.04 °C cm² / Watt and 0.25 °C cm² / Watt.

10. The semiconductor device of claim 9, wherein the redistribution conductive layer comprises tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof.

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