Bipolar junction transistor (BJT) structures and related methods

Abstract

Embodiments of the present disclosure provide bipolar junction transistor (BJT) structures and related methods. A BJT according to the present disclosure can include a base located above a semiconductor substrate. A collector is located above the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is located above the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is less than a horizontal interface between the collector and the base.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to integrated circuits (ICs). More specifically, the present disclosure relates to bipolar junction transistor (BJT) structures and related methods in which a horizontal interface between an emitter and a base is less than a horizontal interface between a collector and the base. BACKGROUND

[0002] In the microelectronics industry, and other industries involving the construction of microscopic structures, there is a constant drive to reduce the size of the structural features and / or to provide more circuitry for a given chip size. Miniaturization generally allows increased performance (more processing per clock cycle, and less heat generated) at lower power levels and lower costs. Current technology is at the atomic scale for certain micro devices (e.g., logic gates, transistors, resistors, capacitors, etc.). Circuit chips with millions of such devices are common.

[0003] One type of transistor architecture is the bipolar junction transistor (BJT). A BJT refers to a transistor formed from three adjacent semiconductor regions (referred to as the emitter, base, and collector, respectively) having alternating conductivity types (e.g., n-p-n or p-n-p). BJTs differ from other types of transistors in that they are "current-controlled devices," such that the current delivered to the base of the transistor controls the current between the emitter and the collector. BJTs can take on a variety of shapes, and can include vertically-stacked semiconductor layers (i.e., vertical BJTs) or horizontal planar arrays of semiconductor material (i.e., lateral BJTs). In the case of lateral BJTs, one persistent technical problem is a relatively low emitter / collector gain, as well as electrical isolation between the emitter and a portion of the base. In some cases, these problems can be avoided by replacing lateral BJTs with vertical BJTs. However, vertical BJTs are not practical in some design or technology applications. SUMMARY

[0004] One aspect of the present disclosure provides a bipolar junction transistor (BJT) structure, comprising: a base located over a semiconductor substrate; a collector located over the semiconductor substrate and laterally adjacent to a first horizontal end of the base; and an emitter located over the semiconductor substrate and laterally adjacent to a second horizontal end of the base opposite the first horizontal end, wherein a horizontal interface between the emitter and the base is less than a horizontal interface between the collector and the base.

[0005] Another aspect of the present disclosure provides a bipolar junction transistor (BJT) structure, comprising: an intrinsic base located on a semiconductor substrate, the intrinsic base having a length between a first pair of horizontal ends in a first direction and a width between a second pair of horizontal ends in a second direction perpendicular to the first direction; a pair of extrinsic bases located on the semiconductor substrate, each extrinsic base of the pair of extrinsic bases laterally abutting a respective one of the first pair of horizontal ends of the intrinsic base; a collector located on the semiconductor substrate and laterally abutting a selected one of the second pair of horizontal ends of the intrinsic base; an emitter located on the semiconductor substrate and laterally abutting another one of the second pair of horizontal ends of the intrinsic base, wherein a length of the emitter in the first direction is less than a length of the collector in the first direction, such that a horizontal interface between the emitter and the intrinsic base is less than a horizontal interface between the collector and the intrinsic base; a gate structure located on the intrinsic base; and a first voltage source coupled to the gate structure and configured to apply a bias to the intrinsic base.

[0006] Yet another aspect of the present disclosure provides a method, comprising: providing a bipolar junction transistor (BJT) structure, the BJT structure comprising: a base located on a semiconductor substrate; a collector located on the semiconductor substrate and laterally abutting a first horizontal end of the base; and an emitter located on the semiconductor substrate and laterally abutting a second horizontal end of the base opposite the first horizontal end, wherein a horizontal interface between the emitter and the base is less than a horizontal interface between the collector and the base; and a gate structure located on the base; applying a voltage to the gate structure; and communicating a current from the collector to the emitter while applying the voltage to the gate structure. BRIEF DESCRIPTION OF DRAWINGS

[0007] These and other features of the present disclosure will be more readily understood from the following detailed description of the aspects of the present disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the present disclosure, in which:

[0008] Figure 1 A cross-sectional view showing an initial structure including a semiconductor layer on a buried insulator layer is shown in accordance with embodiments of the present disclosure.

[0009] Figure 2 A cross-sectional view showing formation of a gate structure, a collector, and an emitter on the initial structure is shown in accordance with embodiments of the present disclosure.

[0010] Figure 3A cross-sectional view of forming an outer base from an initial structure is shown in accordance with embodiments of the present disclosure.

[0011] Figure 4 A cutaway perspective view of a portion of a BJT structure is shown in accordance with embodiments of the present disclosure.

[0012] Figure 5 A plan view of a bipolar junction transistor (BJT) structure is shown in accordance with embodiments of the present disclosure.

[0013] Figure 6 A cross-sectional view of a BJT structure is shown in accordance with embodiments of the present disclosure taken along line 3-3 in Figure 1

[0014] Figure 7 A cross-sectional view of a BJT structure is shown in accordance with embodiments of the present disclosure taken along line 4-4 in Figure 2

[0015] Figure 8 A cross-sectional view of a BJT structure is shown in accordance with embodiments of the present disclosure taken along line 5-5 in Figure 2

[0016] Figure 9 A cross-sectional view of a BJT structure is shown in accordance with embodiments of the present disclosure having an alternative doping configuration.

[0017] Figure 10 An illustrative flow diagram of a method in accordance with embodiments of the present disclosure is provided.

[0018] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the disclosure and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents similar elements between the drawings. DETAILED DESCRIPTION

[0019] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific exemplary embodiments in which the teachings can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the teachings, and it is to be understood that other embodiments can be utilized and that changes can be made without departing from the scope of the present teachings. The following description is, therefore, not to be taken in a limiting sense.

[0020] ​​​Embodiments of the present disclosure provide a bipolar junction transistor (BJT) having laterally oriented base, collector, and emitter materials for achieving enhanced isolation and stronger collector / emitter gain compared to other types of BJT structures. Such a structure can be referred to as a “lateral BJT.” Each of the base, collector, and emitter can be located over a semiconductor substrate, and optionally over an insulator layer of a fully depleted semiconductor-on-insulator (FDSOI) substrate. The collector can laterally abut the base along a predetermined length. The emitter can laterally abut the base opposite the collector, but with a smaller horizontal interface along the length than the horizontal interface between the collector and the base. In some cases, a gate structure can be formed over the base and coupled to a voltage source to apply a bias to the base. In such cases, the BJT can be “gate assisted,” such that applying a reverse bias to the base through the gate enhances current between the collector and the emitter. Methods according to the present disclosure include applying a reverse bias to the base through the gate while operating the BJT structure.

[0021] BJT structures, such as those in embodiments of the present disclosure, operate by using multiple “P-N junctions.” The term “P-N” refers to two adjacent materials having different types of electrical conductivity (i.e., P-type and N-type), which can be induced by dopants within the adjacent materials. When formed in a device, a PN junction can operate as a diode. A diode is a two-terminal element whose behavior differs from a conductive or insulating material between two electrical contacts. Specifically, a diode provides high conductivity from one contact to the other in one direction (i.e., the “forward” direction), and little or no conductivity in the opposite direction (i.e., the “reverse” direction). In the case of a PN junction, the orientation of the forward and reverse directions of the diode can depend on the type and magnitude of bias applied to the materials composition of one or both terminals, which affects the size of the potential barrier. In the case of a junction between two semiconductor materials, a potential barrier will form along the interface between the two semiconductor materials. IC structures and related methods according to the present disclosure include applying varying biases to doped semiconductor materials to create a BJT within selected portions of a device layer.

[0022] Reference Figure 1 FIG. 1 illustrates an initial structure 100 suitable for forming a BJT according to embodiments of the present disclosure. The initial structure 100 can be processed as described herein to produce one or more lateral BJT structures having different collector-base and emitter-base geometries, although it should be understood that in additional embodiments other techniques, process sequences, etc. can also be implemented to produce the same BJT structures or similar BJT structures. Figure 1A cross-sectional view of a structure 100 having a substrate 102 comprising, for example, one or more semiconductor materials is shown. The substrate 102 can comprise any presently known or later developed semiconductor material, which can include, but is not limited to, silicon, germanium, silicon carbide, and materials substantially consisting of one or more III-V compound semiconductors having a chemical formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 defined composition, where Xi, X2, X3, Yi, Y2, Y3, and Y4 represent relative proportions greater than or equal to zero, respectively, and Xi + X2 + X3 + Yi + Y2 + Y3 + Y4 = 1 (1 being the total relative molar amount). Other suitable substrates include II-VI compound semiconductors having a composition Zn A1 Cd A2 Se B1 Te B2 , where Ai, A2, Bi, and B2 are relative proportions greater than or equal to zero, respectively, and Ai + A2 + Bi + B2 = 1 (1 being the total molar amount). The bulk of the substrate 102 or a portion thereof can be strained.

[0023] A buried insulator layer 104, also referred to in the art as a "buried oxide" or "BOX" layer, can be formed on the substrate 102 to electrically isolate overlying active semiconductor material, examples of which are discussed elsewhere herein. The buried insulator layer 104 can comprise one or more oxide compounds and / or any other presently known or later developed electrically insulative substance. The buried insulator layer 104 can be as narrow as possible to provide better interaction with overlying semiconductor material, and can have a thickness of at most about twenty-five nanometers (nm) in various embodiments. The structure 100 can be considered a "fully depleted semiconductor-on-insulator" (FDSOI) structure in cases where transistors formed on the buried insulator layer 104 also have functionally similar thickness scales. Use of FDSOI technology provides various advantages, such as tunable transistor potentials by applying a bias to the semiconductor material above the substrate 102 and / or buried insulator layer 104.

[0024] The structure 100 can include an initial semiconductor layer 106 located on the buried insulator layer 104. The initial semiconductor layer 106 can be formed, for example, by deposition and / or etching with the aid of various masks (not shown) on the buried insulator layer 104. In formation, the initial semiconductor layer 106 can have a predetermined height above the buried insulator layer 104 and have a predetermined surface area. Some portions of the buried insulator layer 104 can be free of the initial semiconductor layer 106. In addition, various electrically conductive particles (“dopants”) can be introduced into the buried insulator layer 104 via a process known as “pre-doping” of the initial semiconductor layer 106 above the buried insulator layer 104.

[0025] The initial doping of the initial semiconductor layer 106 can be a relatively low concentration of P-type or N-type compared to the doping material formed subsequently. P-type dopants refer to elements introduced into the semiconductor material 1063 to create free holes by “accepting” an electron from a semiconductor atom and thus “releasing” a hole. An acceptor atom must have one less valence electron than the host semiconductor. P-type dopants suitable for the initial semiconductor material 106 can include, but are not limited to: boron (B), indium (In), and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Other alternatives include indium and gallium (Ga). Gallium (Ga) has a high diffusivity in silicon dioxide (SiO2), so the oxide cannot be used as a mask during Ga diffusion. N-type dopants are elements introduced into a semiconductor material to create free electrons, for example, by “donating” an electron to the semiconductor. N-type dopants must have one more valence electron than the semiconductor. Common N-type donors in silicon (Si) include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). In example implementations, the initial semiconductor layer 106 is lightly doped with P-type dopants.

[0026] Reference is now made to Figure 2 After the desired concentration of dopants is formed therein, a gate structure 108 can be formed over a portion of the initial semiconductor layer 106. Figure 2 A cross-sectional view in the X-Z plane is shown, while Figure 1A cross-sectional view in the X-Y plane is shown. The gate structure 108 can be a functional component of another active device (e.g., a laterally extending gate of one or more field effect transistors (FETs)), a "dummy gate" configured to be replaced with an active gate structure in subsequent processing, or in some cases, can be a placeholder material simply to prevent further doping of semiconductor material thereunder. Regardless of how the gate structure 108 is embodied, the area of the initial semiconductor layer 106 covered by the gate structure 108 can define a base 110 in the final BJT structure. Due to the presence of the gate structure 108 thereover, the base 110 of the initial semiconductor layer 106 can be protected from further doping, modification, etc. With the gate structure 108 in place, additional semiconductor material (e.g., silicon, silicon germanium (SiGe), and / or other semiconductor materials described herein) can be formed on the buried insulator layer 104 along with the initial semiconductor layer 106. Such material can be epitaxially grown over the buried insulator layer 104 to a desired height and can be approximately the same height as the initial semiconductor layer 106.

[0027] For example, additional dopants can be formed within semiconductor material alongside the initial semiconductor layer 106, e.g., by implantation or other doping techniques. The polarity of the doping of such material can be opposite that of the initial semiconductor layer 106. In the example where the initial semiconductor layer 106 is P-type lightly doped, the semiconductor material adjacent to the initial semiconductor layer 106 can be N-type heavily doped. The gate structure 108 protects the base 110 of the initial semiconductor layer 106 from being doped along with the adjacent material. One region of the semiconductor material adjacent to the base 110 defines a collector 112 of the final BJT structure, while another region of the semiconductor material adjacent to the base 110 defines an emitter 114 of the final BJT structure. Through doping, the base 110, collector 112, and emitter 114 can together form an NPN or PNP junction, thereby defining three terminals of a bipolar junction transistor (BJT) 115.

[0028] Reference is now made to Figure 3 which again shows a cross-sectional view in the plane Y-Z, continued processing can include covering the collector 112 and emitter 114 with a mask or insulator (not shown) and introducing additional dopants to the initial semiconductor layer 106 Figure 1 , 2The portions of the initial semiconductor layer 106 that are not covered by the gate structure 108 on the buried insulator layer 104 can receive additional P-type dopants (e.g., by implantation or other doping process) according to one example. These portions of semiconductor material will continue to exhibit their original doping polarity, but at a significantly higher concentration than the other semiconductor material covered by the gate structure 108. Thus, this further doping creates an inner base 116 under the gate structure 108 and one or more outer bases 118 adjacent to the inner base 116. The inner base 116 can be structurally continuous with the outer bases 118 despite the difference in doping concentration in the outer bases 118, as both regions were originally part of the initial semiconductor layer 106. Optionally, additional doped semiconductor material can be formed on the outer bases 118 (e.g., by epitaxial growth) to increase their height above the buried insulator layer 104. The inner base 116, however, retains its original dimensions due to the presence of the gate structure 108. The inner base 116 and the outer bases 118 each define a partial base 110 on the buried insulator layer 104. The buried insulator layer 104 thus vertically separates the base 110 from the substrate 102. At this stage, the gate structure 108 can be removed or otherwise converted to one or more functional gate materials, as described herein.

[0029] Turning now to Figure 4 and Figure 5 the continued processing of the materials discussed herein can result in a BJT structure (hereinafter simply “structure”) 120. Figure 4 A cutaway perspective view of the structure 120 is shown, while Figure 5 A single plane of the structure 120 in the X-Y plane is shown, where several materials are immediately on top of the buried insulator layer 104 or above the substrate 102. Figure 3 Portions of the structure 120 not shown in FIG. 12A can be considered mirror images of those shown, as the cutaway view is taken along a bisecting line through the structure 130. After the base 110 (including the inner base 116 and the outer bases 118), the collector 112, and the emitter 114 are formed, an insulator 121 can be formed above the substrate 102 (e.g., by deposition and planarization as discussed herein).

[0030] Insulator 121 prevents electrical short circuits and / or accidental biasing of nearby components and also physically separates the various doped materials of structure 120 from the various lateral far-end structures. Insulator 121 can be made of any insulating material such as SiO2 or a "low-k" dielectric, which may, for example, have a dielectric constant less than 3.9. In some cases, insulator 121 can be made of oxide materials. Insulator 121 can be formed by forming one or more insulating materials (e.g., by deposition of an insulating material and subsequent planarization). When formed by deposition, insulator 121 can be formed after patterning of other structures such as base 110, collector 112, and / or emitter 114.

[0031] The horizontal orientation of the base 110, collector 112, and emitter 114 results in the BJT 115 being configured as a "lateral BJT". Applying a current to the base 110 controls the ability of current to flow from the collector 112 to the emitter 114. As discussed herein, the base 110 may include an inner base 116 having a lighter doping concentration and spanning a width in the X-axis direction and a length in the Y-axis direction. An outer base 118 is adjacent to the longitudinal end of the inner base 116 and has a significantly higher doping concentration (e.g., as...). Figure 3 (The result of the individual doping operation is shown in the figure). The outer base 118 may have a greater height than the inner base 116, so the outer base 118 may have a top surface located above the top surface of the inner base 116 (i.e., oriented along the positive Z-axis).

[0032] The base 110 may have a first horizontal end W1 in the X-axis direction and a second horizontal end W2 opposite to the first horizontal end W1 in the X-axis direction. In some cases, the horizontal ends W1 and W2 specifically refer to the two horizontal ends of the inner base 116. The collector 112 may be laterally adjacent to the first horizontal end W1 of the base 110, while the emitter 114 may be laterally adjacent to the opposite horizontal end W2 of the base 110. As discussed elsewhere herein, the base 110 may have a first doping type (i.e., P-type or N-type doping), while the collector 112 and emitter 114 have opposite doping types, thereby forming a PNP or NPN junction in the X-axis direction. The collector 112 and emitter 114 may have doping types opposite to those of the base 110. If the base 110 is P-type doped, the collector 112 and emitter may be N-type doped, and vice versa.

[0033] Specifically, such as Figure 4 and Figure 5As shown, in various embodiments of structure 120, the collector 112 may have a different size than the emitter 114. For example, the emitter 114 may be smaller than the collector 112, so the horizontal interface between the emitter 114 and the base 110 may be smaller than the horizontal interface between the collector 112 and the base 110. In this case, the length of the emitter 114 parallel to the inner base 116 may be smaller than the length of the collector 112 in the same direction, thereby providing a smaller horizontal interface with the base 110 relative to the collector 112. For example, this configuration can be provided by forming the emitter 114 from a smaller area of ​​deposited or grown semiconductor material, and / or by removing a portion of the semiconductor material from the emitter 114 after both the collector 112 and the emitter 114 have been formed. Because the horizontal interface between the emitter 114 and the base 110 is smaller relative to the horizontal interface between the collector 112 and the base 110, some portions of the insulator 121 may be horizontally located between the emitter 114 and the base 110 along the Y-axis direction. Here, the insulator 121 horizontally separates the emitter 114 from the outer base 118, such as Figure 5 As shown. The position of the insulator 121 between the emitter 114 and the base 110 is... Figure 4 The dashed outline is used for emphasis.

[0034] Various conductive materials can electrically connect the various portions of structure 120 (e.g., base 110, collector 112, and emitter 114) to other components of the IC structure. Such materials may include contacts 122 (only) formed on structure 120 and / or partially formed within an overlying material (e.g., insulator 121). Figure 1 Contact 122 may be formed of, for example, one or more conductive metals and / or conductive silicide regions. Contact 122 may be present on the outer base 118, and collector 112 and emitter 114 may each have one or more contacts 122 for defining electrical terminals (base 110, collector 112, emitter 114) of the BJT 115 in structure 120. Contact 122 may additionally include, for example, a refractory metal liner (not shown) to horizontally separate the conductive material of contact 122 from the adjacent portion of insulator 121 and / or other horizontally adjacent material. Such a liner includes, for example, but not limited to, materials such as: tantalum nitride (TaN) and tantalum; tantalum nitride, tantalum, and cobalt; and magnesium (Mn) or combinations thereof.

[0035] Structure 120 may optionally include a gate structure 130 located above the base 110 of the BJT 115 (including the inner base 116 and possibly some portions of the outer base 118). Figure 1 Gate structure 130 can be compared with gate structure 108 described herein for directional growth and doping of semiconductor material on buried insulating layer 104.Figures 1-3 The gate structure 130 can be the same as, or it can be an alternative to, the previously described gate structure 108, forming an electroactive "alternative metal gate". Regardless of the specific embodiment, the gate structure 130 can be electrically coupled to the base 110 (e.g., by reverse biasing with a negative voltage), thereby influencing the current flowing from the collector 112 to the emitter 114 through the inner base 116 by increasing the ability of charge carriers to flow through the doped semiconductor material in the base 110. If included, the gate structure 130 does not directly control whether the current flow from the collector 112 to the emitter 114 is enabled or disabled, as this function is controlled by the current applied to the base 110. Instead, when negatively biased, when the current flowing to the base 110 has already enabled the current flow from the collector 112 to the emitter 114, the gate structure 130 allows current to flow from the collector 112 to the emitter 114.

[0036] Those skilled in the art will understand that the gate structure 130 may include one or more layers that may form a gate stack. According to one example, the gate structure 130 may include a gate conductor 132 formed of doped or undoped polysilicon (poly-Si). In other examples, the gate conductor 132 may include, for example, but not limited to, materials such as, but not limited to, aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and / or combinations thereof.

[0037] The gate structure 130 may include a gate dielectric layer 134 located above the base 110 (e.g., at least the outer base 116). The gate dielectric layer 134 may include a high-k dielectric, such as, but not limited to: metal oxides, such as tantalum oxide (Ta₂O₅), barium titanium oxide (BaTiO₃), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and aluminum oxide (Al₂O₃); or metal silicates, such as hafnium silicate (HfO₂). A1 Si A2 O A3 ) or hafnium oxynitride silicate (Hf A1 Si A2 O A3 N A4), where A1, A2, A3 and A4 represent relative proportions, which are greater than or equal to zero and A1+A2+A3+A4 (1 is the total relative molar amount). The gate dielectric layer 134 may include any conceivable insulating material, such as, but not limited to: silicon nitride (Si3N4); silicon oxide (SiO2); fluorinated SiO2 (FSG); hydrogenated carbon silicon oxide (SiCOH); porous SiCOH; borosilicate glass (BPSG); silsesquioxane; carbon (C) doped oxides (i.e., organosilicones) comprising atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H); thermosetting polyarylene ether; SiLK (a polyarylene ether available from Dow Chemical Corporation); spin-coated silicon-carbon-containing polymer materials available from JSR Corporation; hydrogenated carbon silicon oxide (SiCOH); porous SiCOH; porous methylsilsesquioxane (MSQ); porous hydrogen silsesquioxane (HSQ); octamethylcyclotetrasiloxane (OMCTS)[(CH3)2SiO]4 available from Air Liquide. 2.7, or other low dielectric constant (k < 3.9) materials, or combinations thereof. The gate dielectric layer 134 may also include high-k dielectric materials, such as, but not limited to, hafnium silicate (HfSiO), zirconium silicate (ZrSiOx), silicon oxynitride (SiON), or any combination thereof. For horizontal electrical isolation from other materials, the gate structure 130 may include various spacers 136 located within and / or on the sidewalls of the gate structure 130. Spacers 136 may include various nitride insulators and / or other insulating materials described herein with respect to buried insulating layer 104 and / or insulator 121.

[0038] Figures 6-8 Each provided along Figure 5 The cross-sectional view of structure 120 is taken from lines 6-6, 7-7 and 8-8. Figure 6 A longitudinal view of structure 120 in the YZ plane is provided. Figure 7 and Figure 8The width of structure 120 in the XZ plane along two cross sections is shown. Each view shows components for applying one or more voltages to portions of structure 120 discussed herein. In an embodiment where gate structure 130 is present above base 110, a first voltage source 140 may be coupled to gate structure 130. First voltage source 140 may have a positive terminal coupled to ground (GND) and a negative terminal set to a first voltage level B and coupled to gate conductor 132 of gate structure 130. First voltage source 140 applies a reverse bias to base 110 through gate dielectric layer 134 (e.g., at inner base 116), i.e., the voltage polarity of the first voltage level B is opposite to the voltage polarity in BJT 115. The bias applied in gate structure 130 may cause a voltage difference between gate 130 and portions of base 110 below it. For example, where BJT 115 operates by applying a positive voltage to base 110, gate structure 130 may have a negative voltage to induce reverse bias. In addition to other effects, this larger potential difference will also affect the voltage at the base 110 required to initiate the current flow from the collector 112 to the emitter 114.

[0039] Second voltage source 142 with second voltage level "V" Figure 3 , Figure 4 The second voltage level V can be electrically coupled between electrical ground GND and contact 122 to base 110 (e.g., coupled to the outer base 118 of base 110). The second voltage level V can be configured to apply at least a threshold current to base 110, thereby allowing current to flow from collector 112 ( Figure 4 , Figure 5 The current flows to the emitter 114. Because the second voltage source 142 applies a potential to the contact 122, the current is induced into the doped semiconductor material within the outer base 118 below it. Furthermore, due to its position relative to the inner base 116, the induced current within the outer base 118 is also induced within the inner base 116. The current induced within the inner base 116 may be smaller than the current within the outer base 118, for example, because the dopant concentration within the inner base 116 is lower compared to the outer base 118. When the second voltage source 142 selectively applies a potential to the base 110 through the contact 122, it controls the current flow from the collector 112 to the emitter 114.

[0040] Specifically, such as Figure 7 and Figure 8 As shown, the second voltage source 142 can also be coupled to the contact 122 of the collector 112 of structure 120. In this configuration, the collector 112 is set to the second voltage level V in parallel with the base 110 (e.g., its outer base 118). Along Figure 4As shown in the cross-sectional view, during the application of a second voltage level V to the base 110, the collector 112 can transfer an induced current from the second voltage source 142 to the emitter 114 through the base 110. The emitter 114 can then be coupled to ground GND and / or coupled to another interconnected electrical component via a contact 112 thereon. Therefore, the emitter 114 is not coupled to the second voltage source 142 in parallel with the base 110 and the collector 112, and can have a third voltage level G different from the second voltage level V. Because the emitter 114 is sized differently from the collector 112, and because the horizontal interface between the emitter 114 and the base 110 is different compared to the collector 112, the emitter 114 does not... Figure 8 The cross-sectional view of structure 120 shown is horizontally adjacent to base 110.

[0041] refer to Figure 9 This illustrates an alternative configuration of structure 120 with alternative doping. In some embodiments, collector 112 and emitter 114 may be doped to P-type, while inner base 116 may be doped to N-type to form a PNP junction, a configuration shown in other embodiments (e.g., Figures 4-8 (An example of an NPN junction) is the opposite. In such an implementation, the emitter 114 can be opposite to the outer base 118 ( Figure 6 It is coupled in parallel to the second voltage source 142, for example, as discussed elsewhere herein. In this case, the gate structure 132 can be coupled to the first voltage source 140 in the same manner as other configurations. Therefore, structure 120 is adaptable to alternative doping profiles and / or polarities to suit various devices and / or implementations.

[0042] Turn Figure 4 , Figure 5 and Figure 10Embodiments of this disclosure provide methods for operating a structure 120 (e.g., having a base 110, a collector 112, an emitter 114, and a gate structure 130). Embodiments of this disclosure assist the operation of BJT 115 terminals (i.e., base 110, collector 112, emitter 114) within structure 120 by using the gate structure 130, even if the gate structure 130 is not one of the BJT 115s or is not its active portion. To practice the methods according to this disclosure, structure 120 may include BJT 115s, wherein the base 110 is horizontally adjacent to the collector 112 at a first horizontal end W1 and horizontally adjacent to the emitter 114 at a second horizontal end W2. The horizontal interface between the base 110 and the emitter 114, represented by their respective sidewalls that are horizontally in contact with each other, may be smaller than the horizontal interface between the base 110 and the collector 112 (i.e., due to the different dimensions of the collector 112 and the emitter 114). The gate structure 130 (including, for example, gate conductor 132, gate dielectric layer 134, spacer 136, etc.) may be located above the base 110 so as to electrically bias that portion without being electrically coupled to some portion of the base 110 (e.g., inner base 116).

[0043] Process P1 may include applying a reverse bias to the base 110 through the gate structure 130. This can be achieved by using a first voltage source 140 ( Figures 3-5 The reverse bias application in process P1 can be implemented using another electrical element coupled to the gate conductor 132. The reverse bias can affect the charge mobility through the inner base 116 or other portions of the base 110 located below the gate structure 130 to facilitate current flow from the collector 112 to the emitter 114. Process P2 in embodiments of this disclosure (which can be initiated in parallel with process P1 or via an operator of structure 120) can include operating the BJT 115 terminals (i.e., base 110, collector 112, and emitter 114) while applying a reverse bias to the base 110 via the gate structure 130. Where applicable, operation of the BJT 115 in process P2 can include controlling the voltage bias to the base 110 (e.g., via a second voltage source 142). In any case, process P3 can include, for example, delivering current to the collector 112 via the second voltage source 142. The current transmitted can flow from the collector 112 to the emitter 114 through the base 110, as achieved by a voltage applied to the base 110 and a reverse voltage bias in the gate structure 130. Therefore, the method according to this disclosure includes a process of assisting the operation of the base 110, collector 112, and emitter 114 through the gate structure 130 thereon.

[0044] The embodiments of this disclosure provide various technical and commercial advantages, several examples of which are discussed herein. The embodiments of this disclosure offset the relatively small amount of gain and electrical isolation in lateral bipolar transistor structures by using a gate structure overlaid on the lateral bipolar transistor to control current modulation and current flow through the underlying base. The use of gate structure architectures typically used in FET devices allows for easy mapping of the disclosed embodiments and their integration into conventional process flows to form various structures on the device layer of the IC. Furthermore, even when the overlay gate structure is omitted, the use of collector and emitter structures of different sizes can force the bipolar transistor to exhibit different amounts of gain across its collector and emitter terminals.

[0045] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0047] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0048] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A bipolar junction transistor (BJT) structure, comprising: A base electrode located on a semiconductor substrate and comprising an inner base electrode and a pair of outer base electrodes adjacent to the inner base electrode, the inner base electrode having a first pair of horizontal ends in a first direction and a second pair of horizontal ends in a second direction perpendicular to the first direction, each of the outer base electrodes being adjacent to a corresponding horizontal end of the first pair of horizontal ends of the inner base electrode. A collector electrode, which is located on the semiconductor substrate and laterally adjacent to a selected horizontal end of the second pair of horizontal ends of the inner base electrode; An emitter, which is located on the semiconductor substrate and laterally adjacent to another horizontal end of the second pair of horizontal ends of the inner base, wherein the horizontal interface between the emitter and the inner base is smaller than the horizontal interface between the collector and the inner base; A gate structure located above the inner base and laterally positioned between the outer bases in the first direction, wherein the gate structure includes a gate dielectric layer above the inner base and a gate conductor located above the gate dielectric layer; An insulator laterally adjacent to the inner base, wherein the insulator horizontally separates the emitter from the outer base; A first voltage source is coupled to the gate structure, wherein the voltage level of the first voltage source causes the gate structure to apply a reverse bias to the inner base; as well as A second voltage source is coupled to one of the outer bases. One of the emitter and the collector is coupled to ground, and the other of the emitter and the collector is coupled to the second voltage source.

2. The BJT structure according to claim 1 further includes a buried insulating layer located above the semiconductor substrate and below the base, the collector and the emitter.

3. The BJT structure according to claim 2, wherein the base, the collector, and the emitter comprise portions of a fully depleted insulator-on-a-semiconductor (FDSOI) layer located on the buried insulator layer.

4. The BJT structure according to claim 1, wherein the dopant concentration in the inner base is less than the dopant concentration in the outer base.

5. A bipolar junction transistor (BJT) structure, comprising: An inner base electrode, located on a semiconductor substrate, having a length between a first pair of horizontal ends in a first direction and a width between a second pair of horizontal ends in a second direction perpendicular to the first direction; A pair of outer bases are located on the semiconductor substrate, and each of the outer bases is laterally adjacent to a corresponding horizontal end of the first pair of horizontal ends of the inner base. A collector electrode, which is located on the semiconductor substrate and laterally adjacent to a selected horizontal end of the second pair of horizontal ends of the inner base electrode; An emitter, which is located on the semiconductor substrate and laterally adjacent to another horizontal end of the second pair of horizontal ends of the inner base, wherein the length of the emitter in the first direction is less than the length of the collector in the first direction, such that the horizontal interface between the emitter and the inner base is less than the horizontal interface between the collector and the inner base. A gate structure located above the inner base and laterally positioned between the outer bases in the first direction, wherein the gate structure includes a gate dielectric layer above the inner base and a gate conductor located above the gate dielectric layer; A first voltage source is coupled to the gate structure and configured to apply a reverse bias to the inner base; An insulator that is laterally adjacent to the other horizontal end of the second pair of horizontal ends of the inner base, wherein the insulator horizontally separates the emitter from the outer base; as well as A second voltage source is coupled to one of the outer bases. One of the emitter and the collector is coupled to ground, and the other of the emitter and the collector is coupled to the second voltage source.

6. The BJT structure according to claim 5 further includes a buried insulating layer located above the semiconductor substrate and below the inner base, the pair of outer bases, the collector, and the emitter.

7. The BJT structure according to claim 6, wherein the inner base, the pair of outer bases, the collector, and the emitter comprise portions of a fully depleted insulator-on-semiconductor (FDSOI) layer located on the buried insulator layer.

8. The BJT structure according to claim 5, wherein the insulator is laterally adjacent to the emitter.

9. The BJT structure according to claim 8, wherein the insulator comprises a pair of insulator regions, each of the pair of insulator regions being laterally located between the emitter and a corresponding outer base of the pair of outer bases.

10. A method for operating a bipolar junction transistor (BJT), comprising: A voltage is applied to the gate structure of the BJT, the BJT comprising: A base electrode located on a semiconductor substrate and comprising an inner base electrode and a pair of outer base electrodes adjacent to the inner base electrode, the inner base electrode having a first pair of horizontal ends in a first direction and a second pair of horizontal ends in a second direction perpendicular to the first direction, each of the outer base electrodes being adjacent to a corresponding horizontal end of the first pair of horizontal ends of the inner base electrode. A collector electrode, located on the semiconductor substrate and laterally adjacent to a selected horizontal end of the second pair of horizontal ends of the inner base electrode; and An emitter, which is located on the semiconductor substrate and laterally adjacent to another horizontal end of the second pair of horizontal ends of the inner base, wherein the horizontal interface between the emitter and the inner base is smaller than the horizontal interface between the collector and the inner base; A gate structure located above the inner base and laterally positioned between the outer bases in the first direction, wherein the gate structure includes a gate dielectric layer above the inner base and a gate conductor located above the gate dielectric layer; and An insulator laterally adjacent to the inner base, wherein the insulator horizontally separates the emitter from the outer base. The gate structure of the BJT is located above the base and electrically coupled to the base; While applying the voltage to the gate structure, current is transferred from the collector to the emitter; Controlling the polarity of the voltage to apply a reverse bias to the inner base through the gate structure; and One of the emitter and collector of the BJT is electrically coupled to a voltage source, and the other of the emitter and collector of the BJT is electrically coupled to ground.

11. The method of claim 10, wherein the gate dielectric layer between the base and the gate structure prevents the applied voltage from inducing current in the base of the BJT.

12. The method of claim 10, further comprising transmitting the current through at least one external base coupled to the base of the BJT.

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