A display device and its manufacturing method

Abstract

The present application provides a display device and a preparation method thereof, which relates to the field of display technology. The display device can greatly improve the binding accuracy of a chip packaging unit and a display panel, thereby greatly improving the number of output channels of the chip packaging unit, thereby meeting the requirements of high-resolution display products. A chip packaging structure is formed, the chip packaging structure includes at least one chip packaging unit; the chip packaging unit includes at least: a flexible substrate, a rigid substrate arranged on one side of the flexible substrate, and a pin layer arranged on the side of the flexible substrate away from the rigid substrate, the pin layer includes at least a plurality of first pins, and the orthographic projections of the plurality of first pins on the flexible substrate are located within the orthographic projections of the rigid substrate on the flexible substrate; a display panel is formed, the display panel includes a non-display area, the non-display area includes a rigid substrate and a binding portion arranged on the rigid substrate; the first pins of the chip packaging structure are bound and connected to the binding portion of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and a method for manufacturing the same. Background Art

[0002] With the development of high-resolution 3D display products, multi-channel COF (Chip On Film) drivers are the future trend. COF is a chip packaging technology, which is a chip soft film assembly technology that fixes the driver chip (IC) on a flexible circuit board. In 3D display products, COF is connected to the display panel; however, due to the manufacturing process, the binding accuracy of COF and the display panel is limited, and the number of drive channels that can be output is limited, which is difficult to meet the requirements of high-resolution 3D display products. Summary of the invention

[0003] The embodiments of the present application provide a display device and a method for manufacturing the same, which can significantly improve the binding accuracy of a chip packaging unit and a display panel, thereby significantly increasing the number of output channels of the chip packaging unit, thereby meeting the requirements of high-resolution display products.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In one aspect, a method for preparing a display device is provided, the method comprising:

[0006] A chip packaging structure is formed, wherein the chip packaging structure includes at least one chip packaging unit; the chip packaging unit at least includes: a flexible substrate, a rigid substrate arranged on one side of the flexible substrate, and a pin layer arranged on a side of the flexible substrate away from the rigid substrate, the pin layer at least includes a plurality of first pins, and the orthographic projections of the plurality of first pins on the flexible substrate are located within the orthographic projections of the rigid substrate on the flexible substrate;

[0007] forming a display panel, wherein the display panel comprises a non-display area, the non-display area comprises a rigid substrate and a binding portion disposed on the rigid substrate;

[0008] The first pin of the chip packaging structure is bound and connected to the binding portion of the display panel.

[0009] Optionally, after binding and connecting the first pin of the chip packaging structure to the binding portion of the display panel, the method further includes:

[0010] The entire rigid substrate of the chip packaging unit is removed.

[0011] Optionally, the rigid base and the rigid substrate have the same thermal expansion coefficient.

[0012] On the other hand, a display device is provided, which is formed by using one of the manufacturing methods described above, and includes: a chip packaging structure and a display panel; the chip packaging structure includes at least one chip packaging unit; the chip packaging unit includes at least: a flexible substrate, a rigid substrate arranged on one side of the flexible substrate, and a pin layer arranged on a side of the flexible substrate away from the rigid substrate, the pin layer includes at least a plurality of first pins, and the orthographic projections of the plurality of first pins on the flexible substrate are located within the orthographic projections of the rigid substrate on the flexible substrate; the display panel includes a non-display area, the non-display area includes a rigid substrate and a binding portion arranged on the rigid substrate; the first pins of the chip packaging structure are bound and connected to the binding portion of the display panel;

[0013] Alternatively, the display device is formed using the preparation method described above, and includes: a chip packaging structure and a display panel; the chip packaging structure includes at least one chip packaging unit; the chip packaging unit includes: a flexible substrate, and a pin layer arranged on one side of the flexible substrate, the pin layer includes at least a plurality of first pins; the display panel includes a non-display area, the non-display area includes a rigid substrate and a binding portion arranged on the rigid substrate; the first pin of the chip packaging structure is bound and connected to the binding portion of the display panel.

[0014] Optionally, a distance between the first pin and the flexible substrate along a direction perpendicular to the flexible substrate is greater than a distance between an adjacent portion of the first pin and the flexible substrate along a direction perpendicular to the flexible substrate.

[0015] Optionally, a difference between a distance between the first pin and the flexible substrate along a direction perpendicular to the flexible substrate and a distance between an adjacent portion of the first pin and the flexible substrate along a direction perpendicular to the flexible substrate is in a range of 2-8 microns.

[0016] Optionally, the chip packaging unit further comprises at least one lead unit, wherein the lead unit is arranged between the pin layer and the flexible substrate; in the whole formed by all the lead units, the distance between the portion not covered by the first pin and the flexible substrate along the direction perpendicular to the flexible substrate is smaller than the distance between the portion covered by the first pin and the flexible substrate along the direction perpendicular to the flexible substrate; the thickness of the flexible substrate along the direction perpendicular to the flexible substrate is uniform;

[0017] The lead unit includes: a first lead layer and a first organic layer, the first organic layer covers the first lead layer; the first lead layer includes at least a plurality of first routing wires and / or a plurality of first routing pins; the first routing wires and / or the first routing pins are electrically connected to the corresponding first pins.

[0018] Optionally, among all the lead units, in the first organic layer of the lead unit in contact with the first pin, a distance between a portion not covered by the first pin and the flexible substrate along a direction perpendicular to the flexible substrate is smaller than a distance between a portion covered by the first pin and the flexible substrate along a direction perpendicular to the flexible substrate;

[0019] The thickness of the remaining lead units along a direction perpendicular to the flexible substrate is uniform.

[0020] Optionally, the chip packaging unit further comprises a water-oxygen insulation layer, wherein the water-oxygen insulation layer covers the flexible substrate, and the pin layer is arranged on a side of the water-oxygen insulation layer away from the flexible substrate;

[0021] In the flexible substrate, a thickness of a portion not covered by the first pin is smaller than a thickness of a portion covered by the first pin.

[0022] Optionally, the first pin includes at least one conductive layer, and the material of the conductive layer includes metal or metal alloy.

[0023] Optionally, in the case that the first pin includes a layer of the conductive layer, the first pin further includes an anti-oxidation layer, and the anti-oxidation layer covers the conductive layer.

[0024] Optionally, in the case where the first pin includes multiple conductive layers, the first pin includes a first conductive layer, a second conductive layer and a third conductive layer stacked on the flexible substrate;

[0025] The thickness of the first conductive layer along a direction perpendicular to the flexible substrate and the thickness of the third conductive layer along a direction perpendicular to the flexible substrate are respectively smaller than the thickness of the second conductive layer along a direction perpendicular to the flexible substrate.

[0026] Optionally, the first conductive layer and the third conductive layer are made of the same material, and the first conductive layer and the second conductive layer are made of different materials.

[0027] Optionally, the chip packaging unit further includes at least one lead unit, and the lead unit is arranged between the pin layer and the flexible substrate; the lead unit includes: a first lead layer and a first organic layer, and the first organic layer covers the first lead layer;

[0028] The first lead layer includes a plurality of first routing lines, and the layer structure included in the first routing lines is the same as the layer structure included in the first pins;

[0029] And / or, the first lead layer includes a plurality of first routing pins, and the layer structure included in the first routing pins is the same as the layer structure included in the first pins.

[0030] Optionally, the chip packaging unit further includes at least one lead unit, and the lead unit is arranged between the pin layer and the flexible substrate; the lead unit includes: a first lead layer and a first organic layer, and the first organic layer covers the first lead layer;

[0031] The first lead layer includes a plurality of first routing lines, the first routing lines include multiple conductive layers stacked in layers, and the first pin includes a conductive layer;

[0032] And / or, the first lead layer includes a plurality of first routing pins, the first routing pins include a plurality of conductive layers stacked together, and the first pins include a conductive layer.

[0033] Optionally, a plurality of the first pins are arranged in an array.

[0034] Optionally, the pin layer further includes: a plurality of second pins, the plurality of second pins are arranged on one side of the flexible substrate, and the display device further includes a driving board, the plurality of second pins are bound and connected to the driving board.

[0035] Optionally, the second pin and the first pin are arranged on the same layer.

[0036] Optionally, the chip packaging unit further includes a chip, and the first pin and the second pin are electrically connected to the chip respectively.

[0037] Optionally, the display panel further includes a display area connected to the non-display area;

[0038] The length of one side of the chip packaging structure bound to the display panel along a preset direction, the length of the binding portion of the display panel along the preset direction, and the length of the display area of ​​the display panel along the preset direction are the same.

[0039] The embodiment of the present application provides a display device and a method for preparing the same. In the process of binding the first pin of the chip packaging structure of the display device to the binding part of the display panel, the orthographic projection of the multiple first pins on the flexible substrate is located within the orthographic projection of the rigid substrate on the flexible substrate. At the same time, the binding part of the display panel is arranged on the rigid substrate, and the thermal expansion coefficients of the rigid substrate and the rigid substrate are the same or similar. In the binding process, the compensation amount introduced by thermal expansion can be minimized, the binding deviation and the binding spacing can be reduced, and high-precision binding can be achieved. The display device can greatly improve the binding accuracy of the chip packaging unit and the display panel, thereby greatly improving the number of output channels of the chip packaging unit, thereby meeting the requirements of high-resolution display products (e.g., 3D display products).

[0040] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A schematic diagram of the structure of a chip packaging unit provided in an embodiment of the present application;

[0043] Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0044] Figure 3 for Figure 1 and Figure 2 Schematic diagram of the structure after binding;

[0045] Figure 4 For the general Figure 3 Schematic diagram of the structure after peeling off the medium rigid substrate;

[0046] Figure 5 , Figure 6a , Figure 6b and Figure 7 Schematic diagram of the structure of four chip packaging units after bending provided in the embodiments of the present application;

[0047] Figure 8 A schematic diagram of the structure of another chip packaging unit provided in an embodiment of the present application;

[0048] Fig. 9 A schematic structural diagram of a chip packaging unit with a single-layer wiring provided in an embodiment of the present application;

[0049] Fig.10 for Fig. 9 Cross-sectional view along CC1 direction;

[0050] Fig.11 for Fig. 9 Cross-sectional view along the C2C3 direction;

[0051] Fig.12 A schematic diagram of the structure of a first lead layer provided in an embodiment of the present application;

[0052] Fig.13 A schematic diagram of the structure of a pin layer provided in an embodiment of the present application;

[0053] Fig.14 is a schematic diagram of the structure of a chip packaging unit including two layers of wiring;

[0054] Fig.15 for Fig.14 Cross-sectional view along EE1 direction;

[0055] Fig.16 for Fig.14 Cross-sectional view along the E2E3 direction;

[0056] Fig.17 is a schematic structural diagram of a chip packaging unit including two lead units;

[0057] Fig.18 A schematic structural diagram of another chip packaging unit provided in an embodiment of the present application;

[0058] Fig.19 and Fig. 20 Structural schematic diagrams of two chip packaging structures including two chips provided in embodiments of the present application;

[0059] Figure 21-24 Schematic diagram of the arrangement structure of four types of multiple first pins provided in the embodiments of the present application;

[0060] Fig.25 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0061] Figure 26-27 A schematic diagram of the structure of two display panels and chip packaging structures provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0063] In the embodiments of the present application, words such as "first", "second", and "third" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0064] In the embodiments of the present application, "multiple" means two or more, "multiple" means two or more, and "at least one" means one or more, unless otherwise clearly defined.

[0065] In the embodiments of the present application, the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0066] The present invention provides a method for manufacturing a display device, the method comprising:

[0067] S01, forming a chip packaging structure, wherein the chip packaging structure includes at least one Figure 1 The chip packaging unit 1 shown in the figure comprises at least: a flexible substrate 11, a rigid substrate 10 arranged on one side of the flexible substrate 11, and a pin layer 12 arranged on a side of the flexible substrate 11 away from the rigid substrate 10, wherein the pin layer comprises at least a plurality of first pins ( Figure 1 (not shown), the orthographic projections of the plurality of first pins on the flexible substrate are located within the orthographic projection of the rigid substrate on the flexible substrate.

[0068] The material of the flexible substrate is not limited. For example, the material of the flexible substrate may include flexible materials such as polyimide (PI). The material of the rigid substrate is not limited. For example, the material of the rigid substrate may include rigid materials such as glass.

[0069] The specific method for forming the chip packaging structure can be determined according to the specific structure. For example, a rigid substrate, a flexible substrate and a pin layer can be formed in sequence.

[0070] It should be noted that the rigid substrate of the chip packaging unit can be Figure 1 As shown, it is arranged relative to the entire surface of the flexible substrate; or, it can also be arranged only in the area corresponding to the first pin; or, it can also be arranged in the area corresponding to the first pin, as well as in other binding areas (for example: chip binding area and / or driver board binding area).

[0071] S02, forming Figure 2 The display panel shown, wherein the display panel 2 includes a non-display area A1, and the non-display area A1 includes a rigid substrate and a binding portion 21 arranged on the rigid substrate.

[0072] There is no limitation on the type of display panel here, and it can be a TN (Twisted Nematic) type, VA (Vertical Alignment) type, IPS (In-Plane Switching) type, ADS (Advanced Super Dimension Switch) type or other liquid crystal display panel, or it can be an OLED (Organic Light-Emitting Diode) display panel.

[0073] The material of the rigid substrate is not limited, and for example, the material of the rigid substrate may include rigid materials such as glass. The material of the rigid substrate may be the same as the material of the rigid base of the chip packaging unit, and in this case, the thermal expansion coefficients of the two materials are the same.

[0074] The display panel may further include a display area (Active Area, AA), where the display area is connected to a non-display area, wherein the display area refers to an area used to realize display, and the non-display area is generally used to set a driving circuit and the like.

[0075] S03, binding and connecting the first pin of the chip packaging structure with the binding portion of the display panel to obtain Figure 3 The structure shown.

[0076] In the related art, the chip packaging structure includes a PI flexible substrate, and the display panel includes a glass substrate, and the thermal expansion coefficients of PI and glass are different. During the binding process, it is necessary to adopt a temperature compensation method, that is, the upper and lower substrates are heated at different temperatures to achieve upper and lower alignment. Although part of the compensation can be achieved, in the actual operation process, there are low alignment accuracy and large yield loss, and the binding accuracy is low. Based on this, in the chip packaging structure provided by the present application, the orthographic projection of multiple first pins on the flexible substrate is located within the orthographic projection of the rigid substrate on the flexible substrate; at the same time, the binding part of the display panel is arranged on the rigid substrate, and the thermal expansion coefficients of the rigid substrate and the rigid substrate are the same or similar. In the binding process of step S03, the compensation amount introduced by thermal expansion can be minimized, thereby achieving high-precision binding.

[0077] Optionally, in order to save space as much as possible, reduce product size, and facilitate bending, after S03, binding and connecting the first pin of the chip packaging structure with the binding portion of the display panel, the method further includes:

[0078] S04, removing all rigid substrates of the chip packaging unit, obtaining Figure 4 The structure shown.

[0079] For example, the stripping may be performed by laser lift-off (LLO), thermal dissociation, or mechanical dissociation.

[0080] It should be noted that after step S03, the rigid substrate can also be retained; or it can be thinned by grinding or other methods and then brought into the terminal; the specific selection can be made according to actual requirements. In order to further reduce the frame, after step S04, the chip packaging structure is bent to form a Figure 5-7 Three structures are shown. Figure 5 In the embodiment, the rigid substrate of the chip packaging unit included in the terminal product is not retained; Figure 6a In the embodiment, the rigid substrate of the chip packaging unit included in the terminal product is retained in the area corresponding to the first pin and the chip binding area; Figure 6b In the embodiment, the rigid substrate of the chip packaging unit included in the terminal product is retained in the area corresponding to the first pin; Figure 7 In the embodiment, the rigid base of the chip packaging unit included in the terminal product is retained in the area corresponding to the first pin, the chip binding area and the driving board binding area.

[0081] Optionally, the rigid base and the rigid substrate have the same thermal expansion coefficient. For example, the materials of the rigid base and the rigid substrate may both include glass. Of course, the thermal expansion coefficients of the rigid base and the rigid substrate may also be similar. For example, the material of the rigid substrate may include glass, and the material of the rigid base may include PET (Polyethylene Terephthalate).

[0082] The present application also provides a display device, which is formed by the manufacturing method of steps S01-S03, and includes: a chip packaging structure and a display panel; the chip packaging structure includes at least one chip packaging unit; Figure 7 As shown, the chip packaging unit at least includes: a flexible substrate 11, a rigid substrate 10 arranged on one side of the flexible substrate 11, and a pin layer 12 arranged on the side of the flexible substrate 11 away from the rigid substrate, the pin layer at least includes a plurality of first pins, and the orthographic projections of the plurality of first pins on the flexible substrate are located within the orthographic projections of the rigid substrate on the flexible substrate; the display panel includes a non-display area, the non-display area includes a rigid substrate 20 and a binding portion 21 arranged on the rigid substrate 20; the first pins of the chip packaging structure are bound and connected to the binding portion of the display panel.

[0083] It should be noted that the chip packaging unit may include: Figure 8 The panel binding area B1, chip binding area B2, driver board binding area B3 and other non-binding areas ( Figure 8 The panel binding area is used for binding with the display panel, the chip binding area is used for binding with the chip, and the driver board binding area is used for binding with the driver board. The first pin 13 can be set in the panel binding area B1. In the chip packaging unit of the above-mentioned display device, the rigid substrate can be set only in the panel binding area; or, in order to ensure the warping degree, the rigid substrate can be set in the panel binding area and the driver board binding area; or, the rigid substrate can be set in the panel binding area, the chip binding area and the driver board binding area; or, the rigid substrate can be set in all areas of the chip packaging unit, which is not limited here.

[0084] Alternatively, the display device provided in the embodiment of the present application can also be formed by the preparation method of the above steps S01-S04, and the display device includes: a chip packaging structure and a display panel; the chip packaging structure includes at least one chip packaging unit; Figure 4 and Figure 5As shown, the chip packaging unit includes: a flexible substrate 11, and a pin layer 12 arranged on one side of the flexible substrate 11, the pin layer includes at least a plurality of first pins; the display panel includes a non-display area, the non-display area includes a rigid substrate 20 and a binding portion 21 arranged on the rigid substrate 20; the first pin of the chip packaging structure is bound and connected to the binding portion of the display panel.

[0085] The thickness of the flexible substrate is not limited. For example, the thickness range is 10-40 micrometers. It can include a single layer or a multi-layer structure, which is not limited here.

[0086] In the process of binding the first pins of the chip packaging structure of the above two display devices with the binding part of the display panel, the orthographic projections of the multiple first pins on the flexible substrate are located within the orthographic projections of the rigid substrate on the flexible substrate. At the same time, the binding part of the display panel is arranged on the rigid substrate, and the thermal expansion coefficients of the rigid substrate and the rigid substrate are the same or similar. In the binding process, the compensation amount introduced by thermal expansion can be minimized, the binding deviation and the binding spacing can be reduced, and high-precision binding can be achieved. The display device can greatly improve the binding accuracy of the chip packaging unit and the display panel, thereby greatly improving the number of output channels of the chip packaging unit, and thus meeting the requirements of high-resolution display products (e.g., 3D display products).

[0087] The first pin and the binding portion may be bound by anisotropic conductive adhesive (ACF, Anisotropic Conductive Films). In order to provide sufficient overflow space for the adhesive and ensure the binding quality, in one or more embodiments, reference is made to Fig.10 and Fig.11 As shown, a distance H1 between the first pin 13 and the flexible substrate 11 along a direction perpendicular to the flexible substrate 11 is greater than a distance H2 between an adjacent portion of the first pin and the flexible substrate 11 along a direction perpendicular to the flexible substrate 11 .

[0088] Optionally, in order to ensure sufficient space for glue overflow and reduce the product size at the same time, the difference between the distance between the first pin and the flexible substrate in a direction perpendicular to the flexible substrate and the distance between an adjacent part of the first pin and the flexible substrate in a direction perpendicular to the flexible substrate is in the range of 2-8 microns. For example, the difference can be 2 microns, 4 microns, 6 microns or 8 microns, etc.

[0089] The chip packaging unit can be used Fig.10 and Fig.11 The single-layer routing structure shown, or Fig.15 and Fig.16 The multi-layer routing structure shown is not limited here.

[0090] A chip packaging unit including multi-layer wiring is provided below.

[0091] Optionally, the chip packaging unit further includes at least one lead unit, referring to Fig.15 and Fig.16 As shown, the lead unit 3 is arranged between the pin layer and the flexible substrate 11; in the whole formed by all the lead units, the distance H4 between the part not covered by the first pin and the flexible substrate along the direction perpendicular to the flexible substrate is smaller than the distance H3 between the part covered by the first pin and the flexible substrate along the direction perpendicular to the flexible substrate; the thickness H of the flexible substrate along the direction perpendicular to the flexible substrate is uniform.

[0092] refer to Fig.12 , Figure 14-16 As shown, the lead unit 3 includes: a first lead layer 18 and a first organic layer 19, the first organic layer 19 covers the first lead layer 18; the first lead layer 18 includes at least a plurality of first routing wires 182 and / or a plurality of first routing pins 181; the first routing wires 182 and / or the first routing pins 181 are electrically connected to the corresponding first pins 13, and for example, the first routing pins 181 can be connected through Fig.14 The illustrated transfer hole 180 is electrically connected to the corresponding first pin 13 .

[0093] The above-mentioned first lead layer includes at least a plurality of first routing lines and / or a plurality of first routing pins, including three situations: the first situation, the first lead layer includes at least a plurality of first routing lines, in which case the first routing lines are electrically connected to the corresponding first pins, and the first routing lines and the first pins may overlap or not overlap along a direction perpendicular to the flexible substrate. The second situation, the first lead layer includes at least a plurality of first routing pins, in which case the first routing pins are electrically connected to the corresponding first pins, and in which case the first routing pins and the first pins may overlap or not overlap along a direction perpendicular to the flexible substrate. The third situation, the first lead layer includes at least: Fig.12 The first wiring 182 and the first wiring pins 181 are shown in FIG. 1 . At this time, the first wiring, the first wiring pin and the corresponding first pin are electrically connected. The first wiring and the first wiring pin can be arranged in the same layer. The first wiring pin and the first wiring can overlap or not overlap with the first pin in a direction perpendicular to the flexible substrate. In order to reduce the generation of parasitic capacitance, reference Fig.14 As shown, the first trace 182 and the first pin 13 do not overlap in a direction perpendicular to the flexible substrate; in order to save space and reduce the spacing, refer to Fig.14 As shown, the first routing pin 181 overlaps with the first pin 13 in a direction perpendicular to the flexible substrate. Further, the orthographic projection of the first routing pin on the flexible substrate is located within the orthographic projection of the first pin on the flexible substrate. Here, the same-layer arrangement refers to the use of a one-time patterning process. The one-time patterning process refers to a process of forming the required layer structure through one exposure. The one-time patterning process includes processes such as masking, exposure, development, etching and stripping.

[0094] The specific layer structure of the first routing line and the first routing pin is not limited here. For example, the first routing line and the first routing pin may include a conductive layer, such as a copper conductive layer; or may also include multiple conductive layers, such as a three-layer stacked structure of a titanium conductive layer, an aluminum conductive layer and a titanium conductive layer, or a three-layer stacked structure of a molybdenum conductive layer, an aluminum conductive layer and a molybdenum conductive layer, and the like.

[0095] Here, the specific layer structure of the first routing line and the first routing pin may be the same as the specific layer structure of the first pin, or may be different, which is not limited here.

[0096] The first organic layer may include a single layer structure or a multi-layer structure, which is not limited here. Its thickness may be 5-10 microns. In the case where the first organic layer includes a multi-layer structure, the materials of each organic layer may be the same or different.

[0097] In this structure, by setting the pin layer and the first lead layer, the first pin and the first wiring function can be respectively realized, so that more pins can be further set, and the number of output channels of the chip packaging structure can be further increased.

[0098] Optional, all lead units, reference Fig.17 As shown, in the first organic layer 19 of the lead unit 3 in contact with the first pin 13, the distance H6 between the portion not covered by the first pin and the flexible substrate in the direction perpendicular to the flexible substrate is smaller than the distance H5 between the portion covered by the first pin and the flexible substrate in the direction perpendicular to the flexible substrate; the thickness H7 of the remaining lead units in the direction perpendicular to the flexible substrate is uniform. This structure is simple and easy to implement, and only the first organic layer of the lead unit in contact with the first pin needs to be patterned to ensure sufficient glue overflow space. Fig.17 The illustration is made by taking two lead units as an example.

[0099] In one or more embodiments, since the flexible substrate is made of organic materials and is easily corroded by water and oxygen, in order to prevent water and oxygen corrosion, the chip packaging unit further includes Fig.10 The water-oxygen insulating layer 16 shown, wherein the water-oxygen insulating layer 16 covers the flexible substrate 11, and the pin layer is arranged on the side of the water-oxygen insulating layer away from the flexible substrate; Fig.10 As shown, the thickness h2 of the portion of the flexible substrate 11 not covered by the first pin 13 is less than the thickness h1 of the portion covered by the first pin. The thickness of the water-oxygen isolation layer is not limited, and for example, the thickness ranges from 100 to 500 nanometers, and the material thereof may include silicon dioxide or silicon nitride.

[0100] In one or more embodiments, the first pin includes at least one conductive layer, and the material of the conductive layer includes metal or metal alloy. For example, the material of the conductive layer may include metals or alloys such as Mo, Al, Ti, and Cu. Taking copper as an example, the first pin can be formed by thick copper plate etching or thick copper electroplating process, and the thickness of copper is about 8 microns. Due to the isotropic nature of wet etching, the dimensional deviation (CD Bias) is difficult to be made smaller, so the pin spacing formed is greater than 16 microns.

[0101] Optionally, in the case where the first pin includes a conductive layer, if the first pin is made of an easily oxidizable material, such as copper, in order to prevent copper oxidation, the first pin also includes an anti-oxidation layer 13, and the anti-oxidation layer covers the conductive layer. The anti-oxidation layer can be made by chemical plating Sn, Au and other processes, with a thickness range of 0.5um to 2um; or, ITO (Indium Tin Oxide) can be covered on the surface of the first pin to prevent oxidation. In addition, the anti-oxidation layer is also beneficial to increase the height of the area where the first pin is located, ensuring sufficient glue overflow space when it is subsequently bound to the panel.

[0102] In order to protect the non-binding area, optionally, a solder resist layer (eg, green oil) may be provided in the non-binding area of ​​the chip packaging unit, with a thickness ranging from 5 to 20 microns.

[0103] Optionally, in the case where the first pin includes a plurality of conductive layers, the first pin includes a first conductive layer, a second conductive layer and a third conductive layer stacked on a flexible substrate; wherein the thickness of the first conductive layer along a direction perpendicular to the flexible substrate and the thickness of the third conductive layer along a direction perpendicular to the flexible substrate are respectively smaller than the thickness of the second conductive layer along the direction perpendicular to the flexible substrate.

[0104] The materials of the first conductive layer and the third conductive layer can be the same or different. The second conductive layer can be made of metal materials such as aluminum, and the first conductive layer and the third conductive layer can be made of metal materials such as molybdenum or titanium. In this way, photolithography or electroplating processes can be used to form finer wiring, and the wiring pitch can be reduced to less than 16 microns, or even to a few microns (for example, 3.6 microns or 5 microns, etc.); if copper is used, the minimum wiring pitch is 16-18 microns. The multi-layer stacked structure can greatly reduce the wiring space compared to the single-layer copper structure, so that the chip packaging unit can provide more output pins to meet the needs of high-resolution display products and 3D display products. It should be noted that if Fig. 9 As shown, the trace spacing refers to the trace ( Fig. 9 The sum of the line width W1 of the trace 17) shown in the figure and the spacing D1 between adjacent traces. The pin spacing refers to the pin ( Fig. 9The sum of the width W of the first pin 13 shown and the distance D between adjacent pins.

[0105] To simplify the process, the first conductive layer and the third conductive layer are made of the same material, and the first conductive layer and the second conductive layer are made of different materials. For example, the second conductive layer may include aluminum, and the first conductive layer and the third conductive layer may include molybdenum or titanium.

[0106] In some embodiments, the chip packaging unit further includes at least one lead unit, which is disposed between the pin layer and the flexible substrate; the lead unit includes: a first lead layer and a first organic layer, and the first organic layer covers the first lead layer.

[0107] The first lead layer includes a plurality of first routing wires, and the layer structure included in the first routing wires is the same as the layer structure included in the first pins; and / or the first lead layer includes a plurality of first routing pins, and the layer structure included in the first routing pins is the same as the layer structure included in the first pins.

[0108] The chip packaging unit includes three situations: the first one, the first lead layer includes a plurality of first routing wires. In this case, the layer structure included in the first routing wires is the same as the layer structure included in the first pin. By way of example, the first routing wires may also include a single-layer or multi-layer structure. For details, please refer to the aforementioned description of the layer structure of the first pin, which will not be repeated here. The second one, the first lead layer includes a plurality of first routing pins. The layer structure included in the first routing pins is the same as the layer structure included in the first pin. By way of example, the first routing wires may also include a single-layer or multi-layer structure. For details, please refer to the aforementioned description of the layer structure of the first pin, which will not be repeated here. The third one, the first lead layer includes a plurality of first routing wires and a plurality of first routing pins. The first routing wires and the first routing pins may include a single-layer or multi-layer structure. For details, please refer to the aforementioned description of the layer structure of the first pin, which will not be repeated here.

[0109] In some embodiments, the chip packaging unit further includes at least one lead unit, which is disposed between the pin layer and the flexible substrate; the lead unit includes: a first lead layer and a first organic layer, and the first organic layer covers the first lead layer.

[0110] The first lead layer includes multiple first routing lines, the first routing lines include multiple conductive layers stacked together, and the first pins include one conductive layer; and / or, the first lead layer includes multiple first routing pins, the first routing pins include multiple conductive layers stacked together, and the first pins include one conductive layer.

[0111] The chip packaging unit includes three situations: the first situation, the first lead layer includes a plurality of first routing lines, the first routing lines include a plurality of conductive layers arranged in a stacked manner, the first pin includes a conductive layer, and by way of example, the first routing lines include a titanium conductive layer, an aluminum conductive layer, and a titanium conductive layer arranged in a stacked manner, and the first pin includes a copper conductive layer. The second situation, the first lead layer includes a plurality of first routing pins, the first routing pins include a plurality of conductive layers arranged in a stacked manner, the first pin includes a conductive layer, and by way of example, the first routing pins include a titanium conductive layer, an aluminum conductive layer, and a titanium conductive layer arranged in a stacked manner, and the first pin includes a copper conductive layer. The third situation, the first lead layer includes a plurality of first routing lines and a plurality of first routing pins, the first routing lines and the first routing pins include a plurality of conductive layers arranged in a stacked manner, and the first pin includes a conductive layer; by way of example, the first routing lines and the first routing pins include a titanium conductive layer, an aluminum conductive layer, and a titanium conductive layer arranged in a stacked manner, and the first pin includes a copper conductive layer.

[0112] Due to the limitations of current silicon wafer production and cutting, the maximum lateral size of a single IC (chip) is generally only about 32 mm, making it difficult to lead out more signal lines. In the present application, the display device includes at least one chip packaging unit, and the number of chip packaging units can be selected according to the size of the product. In the case where the display device includes multiple chip packaging units, the arrangement of the chips included in each chip packaging unit is not limited. For example, each chip 14 can be as follows Fig.19 Alternatively, each chip 14 may be arranged horizontally along the OA direction as shown; Fig. 20 As shown, it is arranged longitudinally along the OB direction; or, partly arranged transversely and partly arranged longitudinally; there is no limitation here.

[0113] In addition, the chip size is limited, and the arrangement of multiple pins in the chip packaging unit will also affect the number of output channels. Optionally, the multiple first pins are arranged in an array. For example, the multiple first pins can be arranged in multiple rows, such as 2 rows, 3 rows, 4 rows ( Figure 21-24 The arrangement direction of the plurality of first pins in each row and the arrangement direction of the plurality of rows are not limited. For example, the plurality of rows may be as follows: Fig.21 As shown in vertical order, or as Fig. 22 In each row, each first pin can be as shown in FIG. Fig.21 and Fig. 22 As shown in the vertical row, or as Fig.23 and Fig.24 The total length of the plurality of first pins can be 60 mm, 68 mm, 70 mm or 127 mm or more, which can be adjusted according to the length of the panel.

[0114] In one or more embodiments, the pin layer further includes: a plurality of Figure 8 and Fig.25 The second pins 15 shown in the figure are arranged on one side of the flexible substrate. Fig.25 As shown, the display device further includes a driving board 4 , and a plurality of second pins 15 are bound and connected to the driving board 4 .

[0115] Here, the driving board can be a PCB (Printed Circuit Board) circuit board, or it can also be an FPC (Flexible Printed Circuit) circuit board. Considering the need to further reduce the frame, the latter can be selected.

[0116] Optionally, in order to simplify the process and reduce the cost, the second pin and the first pin are arranged in the same layer. The second pin and the first pin include the same layer structure. For example, the second pin may include a single layer or a multi-layer structure. For details, please refer to the description of the layer structure of the first pin, which will not be repeated here.

[0117] Optionally, the chip packaging unit also includes Figure 8 In the chip (IC) shown, the first pin 13 and the second pin 15 are electrically connected to the chip 14 respectively. Since the number of the second pins bound and connected to the driving board is less than the number of the first pins bound and connected to the display panel, the extra second pins can also be used to bind to the display panel, thereby further increasing the output channel and saving space. In order to protect the chip, a packaging layer, such as a resin layer, can also be provided.

[0118] In one or more embodiments, the display panel also includes a display area connected to the non-display area; the length of one side of the chip packaging structure bound to the display panel along a preset direction, the length of the binding portion of the display panel along the preset direction, and the length of the display area of ​​the display panel along the preset direction are the same.

[0119] In the related art, the size of the PI-based COF is limited. When the display panel is bound to the COF, the display panel needs to be provided with the following configuration in the non-display area in order to match the size of the COF: Fig.26 The fanout area A2 shown in the figure gathers the leads in a certain area and then connects them to the binding part. In order to ensure equal resistance wiring, the leads in the lead area are arranged in a way such as a "F" shape, which occupies a large space and leads to a large frame. However, this application uses a glass substrate to form a chip packaging structure, and the size is not limited. Fig. 27 As shown, one side of the chip packaging structure bound to the display panel is along a preset direction ( Fig. 27 OA direction) shown in the figure) and the length L2 of the binding portion of the display panel along the preset direction ( Fig. 27 OA direction) and the display area A0 of the display panel along the preset direction ( Fig. 27The lengths L of the three are the same, so that the lead wires 100 of the display panel can be arranged in a direction perpendicular to the preset direction ( Fig. 27 The OB direction shown in the figure is directly led out and electrically connected to the binding part, and equal resistance wiring setting is no longer required, thereby minimizing the border to the greatest extent and facilitating the formation of a display product with an ultra-narrow border.

[0120] The term "one embodiment", "embodiment" or "one or more embodiments" herein means that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. In addition, please note that the examples of the term "in one embodiment" here do not necessarily all refer to the same embodiment.

[0121] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a display device, characterized in that: include: A chip packaging structure is formed, wherein the chip packaging structure includes at least one chip packaging unit; the chip packaging unit at least includes: a flexible substrate, a rigid substrate arranged on one side of the flexible substrate, and a pin layer arranged on a side of the flexible substrate away from the rigid substrate, the pin layer at least includes a plurality of first pins, and the orthographic projections of the plurality of first pins on the flexible substrate are located within the orthographic projections of the rigid substrate on the flexible substrate; forming a display panel, wherein the display panel comprises a non-display area, the non-display area comprises a rigid substrate and a binding portion disposed on the rigid substrate; The first pin of the chip packaging structure is bound and connected to the binding portion of the display panel; wherein the rigid base is located on a side of the flexible base away from the rigid substrate, the pin layer and the rigid base are located on opposite sides of the flexible base, the pin layer is located on a side of the flexible base close to the display panel, and the pin layer is in direct contact with the binding portion; Wherein, the chip packaging unit also includes at least one lead unit, the lead unit is located between the pin layer and the flexible substrate, the lead unit includes a first lead layer, the first lead layer includes at least a plurality of first routing lines and / or a plurality of first routing pins, wherein the first routing lines and the first routing pins are electrically connected to the corresponding first pins, the first routing lines and the first pins do not overlap along a direction perpendicular to the flexible substrate, and the first routing pins overlap with the first pins along a direction perpendicular to the flexible substrate.

2. The preparation method according to claim 1, characterized in that: After binding and connecting the first pin of the chip packaging structure to the binding portion of the display panel, the method further includes: The entire rigid substrate of the chip packaging unit is removed.

3. The preparation method according to claim 1 or 2, characterized in that: The rigid base and the rigid substrate have the same coefficient of thermal expansion.

4. A display device, characterized in that: The display device is formed by the preparation method of claim 1, comprising: a chip packaging structure and a display panel; the chip packaging structure comprises at least one chip packaging unit; the chip packaging unit comprises at least: a flexible substrate, a rigid substrate arranged on one side of the flexible substrate, and a pin layer arranged on a side of the flexible substrate away from the rigid substrate, the pin layer comprises at least a plurality of first pins, and the orthographic projections of the plurality of first pins on the flexible substrate are located within the orthographic projections of the rigid substrate on the flexible substrate; the display panel comprises a non-display area, the non-display area comprises a rigid substrate and a binding portion arranged on the rigid substrate; the first pins of the chip packaging structure are bound and connected to the binding portion of the display panel; Alternatively, the display device is formed by the preparation method according to claim 2, comprising: a chip packaging structure and a display panel; the chip packaging structure comprises at least one chip packaging unit; the chip packaging unit comprises: a flexible substrate, and a pin layer arranged on one side of the flexible substrate, the pin layer comprises at least a plurality of first pins; the display panel comprises a non-display area, the non-display area comprises a rigid substrate and a binding portion arranged on the rigid substrate; the first pin of the chip packaging structure is bound and connected to the binding portion of the display panel; wherein the rigid substrate is located on a side of the flexible substrate away from the rigid substrate, the pin layer and the rigid substrate are located on opposite sides of the flexible substrate, the pin layer is located on a side of the flexible substrate close to the display panel, and the pin layer is in direct contact with the binding portion; Wherein, the chip packaging unit also includes at least one lead unit, the lead unit is located between the pin layer and the flexible substrate, the lead unit includes a first lead layer, the first lead layer includes at least a plurality of first routing lines and / or a plurality of first routing pins, wherein the first routing lines and the first routing pins are electrically connected to the corresponding first pins, the first routing lines and the first pins do not overlap along a direction perpendicular to the flexible substrate, and the first routing pins overlap with the first pins along a direction perpendicular to the flexible substrate.

5. The display device according to claim 4, characterized in that: A distance between the first pin and the flexible substrate along a direction perpendicular to the flexible substrate is greater than a distance between an adjacent portion of the first pin and the flexible substrate along a direction perpendicular to the flexible substrate.

6. The display device according to claim 5, characterized in that: The difference between the distance between the first pin and the flexible substrate in a direction perpendicular to the flexible substrate and the distance between an adjacent portion of the first pin and the flexible substrate in a direction perpendicular to the flexible substrate is in a range of 2-8 micrometers.

7. The display device according to claim 5, characterized in that: The lead unit is arranged between the pin layer and the flexible substrate; in the whole formed by all the lead units, the distance between the portion not covered by the first pin and the flexible substrate along the direction perpendicular to the flexible substrate is smaller than the distance between the portion covered by the first pin and the flexible substrate along the direction perpendicular to the flexible substrate; The thickness of the flexible substrate along a direction perpendicular to the flexible substrate is uniform; The lead unit further includes a first organic layer, and the first organic layer covers the first lead layer.

8. The display device according to claim 7, characterized in that: Among all the lead units, in the first organic layer of the lead unit in contact with the first lead, a distance between a portion not covered by the first lead and the flexible substrate along a direction perpendicular to the flexible substrate is smaller than a distance between a portion covered by the first lead and the flexible substrate along a direction perpendicular to the flexible substrate; The thickness of the remaining lead units along a direction perpendicular to the flexible substrate is uniform.

9. The display device according to claim 5, characterized in that: The chip packaging unit further comprises a water-oxygen insulation layer, wherein the water-oxygen insulation layer covers the flexible substrate, and the pin layer is arranged on a side of the water-oxygen insulation layer away from the flexible substrate; In the flexible substrate, a thickness of a portion not covered by the first pin is smaller than a thickness of a portion covered by the first pin.

10. The display device according to any one of claims 4 to 9, characterized in that: The first pin includes at least one conductive layer, and the material of the conductive layer includes metal or metal alloy.

11. The display device according to claim 10, characterized in that: In the case that the first pin includes a layer of the conductive layer, the first pin further includes an anti-oxidation layer, and the anti-oxidation layer covers the conductive layer.

12. The display device according to claim 10, characterized in that: In the case where the first pin includes a plurality of conductive layers, the first pin includes a first conductive layer, a second conductive layer and a third conductive layer stacked on the flexible substrate; The thickness of the first conductive layer along a direction perpendicular to the flexible substrate and the thickness of the third conductive layer along a direction perpendicular to the flexible substrate are respectively smaller than the thickness of the second conductive layer along a direction perpendicular to the flexible substrate.

13. The display device according to claim 12, characterized in that: The first conductive layer and the third conductive layer are made of the same material, and the first conductive layer and the second conductive layer are made of different materials.

14. The display device according to claim 10, characterized in that: The lead unit comprises: a first lead layer and a first organic layer, wherein the first organic layer covers the first lead layer; The first lead layer includes a plurality of first routing lines, and the layer structure included in the first routing lines is the same as the layer structure included in the first pins; And / or, the first lead layer includes a plurality of first routing pins, and the layer structure included in the first routing pins is the same as the layer structure included in the first pins.

15. The display device according to claim 10, characterized in that: The lead unit comprises: a first lead layer and a first organic layer, wherein the first organic layer covers the first lead layer; The first lead layer includes a plurality of first routing lines, the first routing lines include multiple conductive layers stacked in layers, and the first pin includes a conductive layer; And / or, the first lead layer includes a plurality of first routing pins, the first routing pins include a plurality of conductive layers stacked together, and the first pins include a conductive layer.

16. The display device according to claim 4, characterized in that: The plurality of first pins are arranged in an array.

17. The display device according to claim 4, characterized in that: The pin layer further includes: a plurality of second pins, which are arranged on one side of the flexible substrate. The display device further includes a driving board, which is bound and connected to the driving board.

18. The display device according to claim 17, characterized in that: The second pin and the first pin are arranged on the same layer.

19. The display device according to claim 18, characterized in that The chip packaging unit further includes a chip, and the first pin and the second pin are electrically connected to the chip respectively.

20. The display device according to claim 4, characterized in that The display panel further includes a display area connected to the non-display area; The length of one side of the chip packaging structure bound to the display panel along a preset direction, the length of the binding portion of the display panel along the preset direction, and the length of the display area of ​​the display panel along the preset direction are the same.

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