semiconductor integrated circuit devices

Abstract

A structure is provided for sufficiently suppressing the occurrence of a latch-up phenomenon in a semiconductor integrated circuit device. In an output circuit, an output transistor (P1) is separated from an ESD protection diode (D1) connected to an external output terminal, and a protection resistor (R1) is arranged between the output transistor (P1) and the ESD protection diode (D1). The protection resistor (R1) is formed in a plurality of resistor regions (21), and taps for supplying a power supply voltage to a substrate or a well are formed between the resistor regions (21). Noise applied to the external output terminal is attenuated by the protection resistor (R1) before reaching the output transistor (P1) and absorbed by the tap.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit device having a core region and an I / O region arranged on a chip, and more particularly to a layout structure of an I / O cell arranged in the I / O region. Background Art

[0002] In a semiconductor integrated circuit, input and output cells (I / O cells) are arranged around a core region. Signals are input and output and power is supplied to and from the outside of the semiconductor integrated circuit device through the I / O cells.

[0003] With the recent advancement of miniaturization, the noise immunity of semiconductor integrated circuit devices has declined. In particular, in I / O cells, the latch-up phenomenon caused by noise applied from pads has become a serious problem.

[0004] Patent Document 1 discloses a semiconductor integrated circuit device in which a diode is provided for an external connection terminal as an ESD (ElectroStatic Discharge) protection circuit, and a resistance element is arranged as a protection resistor between an output transistor and the external connection terminal.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-96897 Summary of the Invention

[0006] -Technical problem to be solved by the invention-

[0007] In the structure disclosed in Patent Document 1, the output transistor is protected from ESD damage by a diode and a resistor as ESD protection elements. However, the structure disclosed in Patent Document 1 cannot fully suppress the occurrence of latch-up caused by noise propagating through the well and substrate.

[0008] An object of the present disclosure is to provide a structure capable of sufficiently suppressing the occurrence of a latch-up phenomenon in a semiconductor integrated circuit device.

[0009] -Technical solutions to technical problems-

[0010] In the first aspect disclosed, in a semiconductor integrated circuit device including an output circuit, the output circuit includes: an external output terminal; a first output transistor that outputs an output signal to the external output terminal; a first ESD (ElectroStatic Discharge) protection diode connected to the external output terminal; and a first protection resistor connected between the first output transistor and the first ESD protection diode. When viewed from above, the first output transistor and the first ESD protection diode are arranged separately, and the first protection resistor is arranged between the first output transistor and the first ESD protection diode. The first protection resistor is formed in multiple resistance areas, and taps are formed between the resistance areas to supply power supply voltage to the substrate or well.

[0011] According to this aspect, the first output transistor is arranged separately from the first ESD protection diode connected to the external output terminal, and a first protection resistor is arranged between the first output transistor and the first ESD protection diode. In this way, the noise applied to the external output terminal is attenuated by the first protection resistor before reaching the first output transistor. In addition, the first protection resistor is formed in multiple resistance areas, and taps are formed between the resistance areas to supply the power supply voltage to the substrate or well. In this way, the noise applied to the external output terminal is absorbed by the tap. Therefore, the propagation of noise that causes latch-up can be suppressed.

[0012] -Effects of the Invention-

[0013] According to the present disclosure, the occurrence of a latch-up phenomenon can be sufficiently suppressed in a semiconductor integrated circuit device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a plan view schematically showing the overall structure of a semiconductor integrated circuit device according to an embodiment;

[0015] Figure 2 is a circuit configuration diagram of an output circuit according to the first embodiment;

[0016] Figure 3 This is an example of the planar layout structure of the output circuit involved in the first embodiment;

[0017] Figure 4 This is an example of the layout structure of an ESD protection diode;

[0018] Figure 5 This is an example of the layout structure of an ESD protection diode;

[0019] Figure 6 This is an example of the layout structure of a protection resistor;

[0020] Figure 7 This is an example of the layout structure of a protection resistor;

[0021] Figure 8 This is an example of the layout structure of the output transistor;

[0022] Figure 9 This is an example of the layout structure of the output transistor;

[0023] Figure 10 This is a diagram for explaining how to suppress the occurrence of latch-up.

[0024] Figure 11 This is another example of the planar layout structure of the output circuit according to the first embodiment;

[0025] Figure 12 is a circuit configuration diagram of an output circuit according to a second embodiment;

[0026] Figure 13 This is an example of a planar layout structure of an output circuit according to the second embodiment;

[0027] Figure 14 (a) and (b) are other examples of the planar layout structure of the output circuit according to the second embodiment. DETAILED DESCRIPTION

[0028] The following describes an embodiment with reference to the accompanying drawings. It should be noted that in the following description, "VDDIO" and "VSS" refer to power supply voltages or the power supply itself. Furthermore, transistors are formed on a P-type substrate and an N-type well. It should be noted that transistors can be formed on either a P-type well or an N-type substrate.

[0029] (First embodiment)

[0030] Figure 1 It is a plan view schematically showing the overall structure of a semiconductor integrated circuit device according to an embodiment. Figure 1 The semiconductor integrated circuit device 1 shown includes a core area 2 in which an internal core circuit is formed, and an I / O area 3 provided around the core area 2 and in which an interface circuit (I / O circuit) is formed. In the I / O area 3, an I / O cell array 10A is formed in a ring shape surrounding the periphery of the semiconductor integrated circuit device 1. In the I / O cell array 10A, a plurality of I / O cells 10 constituting the interface circuit are arranged. Figure 1 In the semiconductor integrated circuit device 1, a plurality of external connection pads are arranged. Figure 1 Illustration omitted.

[0031] Figure 2This is a circuit diagram of the output circuit 11 included in the I / O unit 10. It should be noted that in the actual output circuit, Figure 2 Elements other than the circuit elements shown in the Figure 2 The record is omitted.

[0032] Figure 2 The output circuit 11 shown includes an external output terminal OUT, output transistors P1 and N1, ESD (ElectroStatic Discharge) protection diodes D1 and D2, and protection resistors R1 and R2. The output transistor P1 is a P-conductivity type transistor, and the output transistor N1 is an N-conductivity type transistor.

[0033] Output transistors P1 and N1 output signals to an external output terminal OUT based on signals received at their gates. The source of output transistor P1 is connected to VDDIO, and the drain of output transistor P1 is connected to the external output terminal OUT via a protective resistor R1. The source of output transistor N1 is connected to VSS, and the drain of output transistor N1 is connected to the external output terminal OUT via a protective resistor R2. Protection resistors R1 and R2 are, for example, wiring resistors, which are formed using wiring formed on a diffusion layer, a gate wiring layer, a metal wiring layer, or a combination thereof.

[0034] ESD protection diode D1 is installed between VDDIO and the external output terminal OUT, and ESD protection diode D2 is installed between VSS and the external output terminal OUT. If high-voltage noise is input to the external output terminal OUT, current flows through ESD protection diodes D1 and D2 to VDDIO and VSS, respectively, protecting output transistors P1 and N1.

[0035] Figure 3 This is a simplified diagram showing an example of the planar layout structure of the output circuit 11 involved in this embodiment. The X direction (horizontal direction in the figure) is the arrangement direction of the I / O cells 10, and the Y direction (vertical direction in the figure) is the direction from the core area 2 toward the chip end. The upper side in the figure is the core area 2 side, and the lower side in the figure is the chip end side. Figure 3 Each district is marked with Figure 2 The same symbols as the corresponding circuit elements in the circuit diagram.

[0036] ESD protection diodes D1 and D2 are arranged in the center in the Y direction. Output transistor P1 is arranged above and separated from ESD protection diode D1 in the drawing. Output transistor N1 is arranged below and separated from ESD protection diode D2 in the drawing.

[0037] The protection resistor R1 is arranged between the output transistor P1 and the ESD protection diode D1. The protection resistor R1 is formed in a plurality of regions (resistance regions) 21. Figure 3 In the example shown, the protection resistor R1 is rectangular and extends in the Y direction, and is divided into four resistor regions 21 arranged in the X direction. A tap region 23 is arranged to sandwich each resistor region 21, and a tap for supplying VSS to the P-type substrate is formed in the tap region 23.

[0038] The protection resistor R2 is arranged between the output transistor N1 and the ESD protection diode D2. The protection resistor R2 is formed in a plurality of regions (resistance regions) 22. Figure 3 In the example shown, the protection resistor R2 is rectangular and extends in the Y direction, and is divided into four resistor regions 22 arranged in the X direction. A tap region 24 is arranged to sandwich each resistor region 22, and a tap is formed in the tap region 24 to supply VDDIO to the N-type well.

[0039] Note that pads (not shown) are provided on the upper layers of the ESD protection diodes D1 and D2 , and these pads are connected to the outside of the semiconductor integrated circuit device.

[0040] The following describes the details of the layout structure of each circuit element.

[0041] (Layout of ESD protection diodes)

[0042] Figure 4 An example of the layout structure of the ESD protection diode D2 is shown, but the wiring layer and the like are omitted from illustration.

[0043] like Figure 4 As shown, ESD protection diode D2 is formed in the central P-type substrate region. ESD protection diode D2 includes an anode portion 31 formed by a P-type fin 32 and cathode portions 33a, 33b formed by N-type fins 34a, 34b. Fins 32, 34a, 34b extend in the X direction. Anode portion 31 is connected to VSS, while cathode portions 33a, 33b are connected to the external output terminal OUT. A diode is formed between P-type fin 32 and N-type fins 34a, 34b.

[0044] Furthermore, a guard ring 81 is formed around the ESD protection diode D2. The guard ring 81 includes an N-conductivity-type fin 82 formed in the N-well. The fin 82 extends in the X direction and is connected to VDDIO.

[0045] A dummy gate 41 is formed on the fin 32 of the anode portion 31 and the fins 34a and 34b of the cathode portions 33a and 33b. A dummy gate 42 is formed on the fin 82 of the guard ring 81. Dummy gates 41 and 42 extend in the Y direction. The provision of dummy gates 41 and 42 improves the uniformity of the gate pattern of the semiconductor integrated circuit device, thereby improving the reliability and yield of the semiconductor integrated circuit device.

[0046] It should be noted that it is not necessary to provide the dummy gates 41 and 42. Furthermore, it is not necessary to form the guard ring 81.

[0047] Figure 5 An example of the layout structure of the ESD protection diode D1 is shown, but the wiring layer and the like are omitted from the illustration.

[0048] like Figure 5 As shown, ESD protection diode D1 is formed in the central N-well. ESD protection diode D1 includes a cathode portion 36 formed by an N-conductivity-type fin 37 and anode portions 38a, 38b formed by P-conductivity-type fins 39a, 39b. Fins 37, 39a, 39b extend in the X direction. Cathode portion 36 is connected to VDDIO, and anode portions 38a, 38b are connected to the external output terminal OUT. A diode is formed between N-conductivity-type fin 37 and P-conductivity-type fins 39a, 39b.

[0049] Furthermore, a guard ring 83 is formed around the ESD protection diode D1. The guard ring 83 includes a P-type conductive fin 84 formed in a P-substrate region. The fin 84 extends in the X direction and is connected to VSS.

[0050] A dummy gate 43 is formed on the fin 37 of the cathode portion 36 and the fins 39a and 39b of the anode portions 38a and 38b. A dummy gate 44 is formed on the fin 84 of the guard ring 83. Dummy gates 43 and 44 extend in the Y direction. The provision of dummy gates 43 and 44 improves the uniformity of the gate pattern of the semiconductor integrated circuit device, thereby improving the reliability and yield of the semiconductor integrated circuit device.

[0051] It should be noted that it is not necessary to provide the dummy gates 43 and 44. Furthermore, it is not necessary to form the guard ring 83.

[0052] (Layout of protection resistor)

[0053] Figure 6 An example of the layout structure of the protection resistor R2 is shown, but the wiring layer and the like are omitted from the illustration.

[0054] like Figure 6 As shown, Figure 3As shown, the protection resistor R2 is divided into four resistor regions 22 arranged in the X direction. A gate wiring 51 is formed in each resistor region 22. By connecting the gate wirings 51 with wiring (not shown), one or more resistors are formed. The gate wirings 51 are formed on an N-type well.

[0055] The tap regions 24 are arranged to sandwich the resistor regions 22. In each tap region 24, an N-conductivity fin 52 is formed on the N-well, forming a tap. Each fin 52 extends in the X direction and is connected to VDDIO. A dummy gate 45 is formed on each fin 52, extending in the Y direction.

[0056] It should be noted that although the gate wiring 51 constituting the protection resistor is formed on the N-type well, it can also be formed on a P-type substrate. In addition, the tap of the tap area 24 can also be a P-conductivity fin formed on a P-type substrate and connected to VSS.

[0057] Figure 7 An example of the layout structure of the protection resistor R1 is shown, but the wiring layer and the like are omitted from the illustration.

[0058] like Figure 7 As shown, Figure 3 As shown, the protective resistor R1 is divided into four resistor regions 21 arranged in the X direction. A gate wiring 53 is formed in each resistor region 21. By connecting the gate wiring 53 with wiring (not shown), one or more resistors are formed. The gate wiring 53 is formed on an N-type well.

[0059] The tap regions 23 are arranged so as to sandwich the resistor regions 21. In each tap region 23, a P-type conductive fin 54 is formed on a P-type substrate, forming a tap. Each fin 54 extends in the X direction and is connected to VSS. A dummy gate 46 is formed on each fin 54, extending in the Y direction.

[0060] It should be noted that although the gate wiring 53 constituting the protection resistor is formed on the N-type well, it can also be formed on a P-type substrate. In addition, the tap of the tap area 23 can also be an N-conductivity fin formed on the N-type well and connected to VDDIO.

[0061] It should be noted that in this example, the protection resistor is formed by the gate wiring, but is not limited thereto and may be formed by fins, metal wiring, etc. Alternatively, the resistor may be formed by a combination of gate wiring, fins, metal wiring, etc.

[0062] In addition, the dummy gates 45 and 46 may not be provided.

[0063] In addition, although the tap has a diffusion region of a fin structure here, it is not limited thereto.

[0064] (Layout of output transistors)

[0065] Figure 8 An example of the layout structure of the output transistor N1 is shown, but the wiring layer and the like are omitted from the illustration.

[0066] like Figure 8 As shown, in the region of the output transistor N1 located in the center, multiple N-conductivity-type fins 61 are formed, each extending in the X direction and arranged in the Y direction, and multiple gate wirings 62 are formed, each extending in the Y direction and arranged in the X direction. When viewed from above, the overlapping fins 61 and gate wirings 62 form a transistor. The transistors are connected in parallel via wiring (not shown). The drain of each transistor is connected to the external output terminal OUT via a protective resistor R2.

[0067] Furthermore, a guard ring 85 is formed around the output transistor N1. The guard ring 85 includes a P-type conductive fin 86 formed on a P-substrate. The fin 86 extends in the X direction. The fin 86 is connected to VSS. A dummy gate 47 is formed on the fin 86.

[0068] It should be noted that it is not necessary to provide the dummy gate 47. Furthermore, it is not necessary to form the guard ring 85.

[0069] Figure 9 An example of the layout structure of the output transistor P1 is shown, but the wiring layer and the like are omitted from illustration.

[0070] like Figure 9 As shown, in the region of the output transistor P1 located in the center, multiple P-conductivity-type fins 66 are formed, each extending in the X direction and arranged in the Y direction, and multiple gate wirings 67 are formed, each extending in the Y direction and arranged in the X direction. When viewed from above, the overlapping fins 66 and gate wirings 67 form a transistor. The transistors are connected in parallel via wiring (not shown). The drain of each transistor is connected to the external output terminal OUT via a protective resistor R1.

[0071] Furthermore, a guard ring 87 is formed around the output transistor P1. The guard ring 87 includes an N-conductivity-type fin 88 formed in the N-well. The fin 88 extends in the X direction. The fin 88 is connected to VDDIO. A dummy gate 48 is formed on the fin 88.

[0072] It should be noted that the dummy gate 48 may not be provided. Furthermore, the guard ring 87 may not be formed.

[0073] According to this embodiment, output transistor P1 is separated from ESD protection diode D1 connected to external output terminal OUT, and protection resistor R1 is disposed between output transistor P1 and ESD protection diode D1. Output transistor N1 is separated from ESD protection diode D2 connected to external output terminal OUT, and protection resistor R2 is disposed between output transistor N1 and ESD protection diode D2. This allows noise applied to external output terminal OUT to be attenuated by protection resistors R1 and R2 before reaching output transistors P1 and N1. Furthermore, protection resistor R1 is formed across multiple resistor regions 21, and taps for supplying VSS to the P-type substrate are formed in tap regions 23 between resistor regions 21. Protection resistor R2 is formed across multiple resistor regions 22, and taps for supplying VDDIO to the N-type well are formed in tap regions 24 between resistor regions 22. This allows noise applied to external output terminal OUT to be absorbed by the taps. Consequently, the propagation of noise, which can cause latch-up, can be suppressed. Furthermore, since the tap regions 23 and 24 are dispersed into a plurality of regions, the noise absorbing effect can be obtained more uniformly.

[0074] use Figure 10 , which explains how to suppress the occurrence of latch-up. Figure 10 This is a schematic cross-sectional view of the semiconductor integrated circuit device according to this embodiment. Arranged in order from the right in the figure are an ESD protection diode D2, a protection resistor R2, a well tap (protection resistor R2 is omitted from the illustration), an output transistor N1, and other transistors.

[0075] Here, it is assumed that noise is applied to the external output terminal OUT ( Figure 10 If this noise is not sufficiently reduced and propagates to the output transistor N1 or other transistors, the propagated noise causes current to flow into the base of the parasitic bipolar transistor. This causes a latch-up phenomenon caused by the parasitic transistor, generating a large current between VDDIO and VSS ( Figure 10 B).

[0076] On the other hand, according to the structure involved in this embodiment, the distance between the ESD protection diode D2 and the output transistor N1 is increased by the protection resistor R2 interposed between the diode D2 and the other transistors, thereby attenuating noise. In addition, the tap provided in the region of the protection resistor R2 reduces the noise ( Figure 10 A) was Figure 10 The path absorption of D can suppress the base node of the parasitic bipolar transistor ( Figure 10 This can suppress noise propagating to the output transistor N1 and other transistor regions, and can prevent the occurrence of latch-up.

[0077] (Variation)

[0078] Figure 11 1 is a schematic diagram showing another example of the planar layout structure of the output circuit 11. Figure 11 In the example shown, the protective resistor R1 is rectangular and extends in the X direction. It is divided into four resistor regions 21A arranged in the Y direction. Tap regions 23A are arranged to sandwich the resistor regions 21A. Taps for supplying VSS to the P-type substrate are formed in the tap regions 23A.

[0079] The protection resistor R2 has a rectangular shape extending in the X direction and is divided into four resistor regions 22A arranged in the Y direction. A tap region 24A is arranged to sandwich the resistor regions 22A. A tap for supplying VDDIO to the N-type well is formed in the tap region 24A.

[0080] This modified example also achieves the same functions and effects as the aforementioned embodiment. Specifically, noise applied to the external output terminal OUT is attenuated by the protective resistors R1 and R2 before reaching the output transistors P1 and N1. Furthermore, the noise applied to the external output terminal OUT is absorbed by the taps formed in the tap regions 23A and 24A. This suppresses the propagation of noise that can cause latch-up. Furthermore, since the tap regions 23A and 24A are dispersed across multiple locations, the noise absorption effect can be achieved more uniformly.

[0081] It should be noted that in Figure 3 In the figure, the protection resistors R1 and R2 are separated in the X direction. Figure 11 In the embodiment, the protection resistors R1 and R2 are divided in the Y direction, but different division directions may be used. For example, the protection resistor R1 may be divided in the X direction and the protection resistor R2 may be divided in the Y direction.

[0082] (Second embodiment)

[0083] Figure 12 2 is a circuit configuration diagram of the output circuit 12 according to this embodiment. Figure 12 The circuit structure and Figure 2 The circuit structure is basically the same, but the insertion position of the protection resistor is different. Figure 12 The output circuit 12 is provided with a protection resistor R3 instead Figure 2 The protection resistors R1 and R2. Figure 12 In the embodiment, the drains of the output transistors P1 and N1 are connected to each other, and the protection resistor R3 is provided between the external output terminal OUT and the drains of the output transistors P1 and N1.

[0084] Figure 13This is a simplified diagram showing an example of the planar layout structure of the output circuit 12 involved in this embodiment. The X direction (horizontal direction in the figure) is the arrangement direction of the I / O cells 10, and the Y direction (vertical direction in the figure) is the direction from the core area 2 toward the chip end. The upper side in the figure is the core area 2 side, and the lower side in the figure is the chip end side. Figure 13 Each district is marked with Figure 12 The same symbols are used for the corresponding circuit elements in the circuit diagram. On the upper layer of the ESD protection diodes D1 and D2, there are pads (not shown), which are connected to the outside of the semiconductor integrated circuit device.

[0085] ESD protection diodes D1 and D2 are arranged adjacent to each other in the Y direction. Output transistors P1 and N1 are arranged adjacent to each other in the Y direction. ESD protection diodes D1 and D2 are arranged at the lower portion of the drawing in the Y direction. Output transistors P1 and N1 are arranged above ESD protection diodes D1 and D2 in the drawing and are separated from ESD protection diodes D1 and D2.

[0086] The protection resistor R3 is arranged between the output transistors P1 and N1 and the ESD protection diodes D1 and D2. The protection resistor R3 is formed in a plurality of regions (resistance regions) 121. Figure 13 In the example shown in FIG, the protection resistor R3 is rectangular and extends in the Y direction, and is divided into four resistor regions 121 arranged in the X direction. Between the resistor regions 121, a tap region 122 is formed with a tap for supplying VSS to the P-type substrate, and a tap region 123 is formed with a tap for supplying VDDIO to the N-type well. Figure 13 In the example shown in FIG, the tap regions 122 and the tap regions 123 are alternately arranged in the Y direction. That is, a tap for supplying VSS to the P-type substrate and a tap for supplying VDDIO to the N-type well are formed in a single region between the resistor regions 121.

[0087] According to this embodiment, output transistors P1 and N1 are separated from ESD protection diodes D1 and D2 connected to the external output terminal OUT, and a protection resistor R3 is disposed between the output transistors P1 and N1 and the ESD protection diodes D1 and D2. This allows noise applied to the external output terminal OUT to be attenuated by the protection resistor R3 before reaching the output transistors P1 and N1. Furthermore, the protection resistor R3 is formed across multiple resistor regions 121. Taps for supplying VSS to the P-type substrate are formed in the tap regions 122 between the resistor regions 121, and taps for supplying VDDIO to the N-type well are formed in the tap regions 123 between the resistor regions 121. This allows noise applied to the external output terminal OUT to be absorbed by the taps. Consequently, the propagation of noise that can cause latch-up can be suppressed. Furthermore, since the tap regions 122 and 123 are dispersed across multiple regions, the noise absorption effect can be achieved more uniformly.

[0088] It should be noted that the tap region 122 having a tap for supplying VSS to the P-type substrate is used to absorb noise from the ESD protection diode D1 , and the tap region 123 having a tap for supplying VDDIO to the N-type well is used to absorb noise from the ESD protection diode D2 .

[0089] It should be noted that the positions of the ESD protection diodes D1 and D2 can be interchanged. In addition, the positions of the output transistors P1 and N1 can be interchanged.

[0090] (Variation)

[0091] Figure 14 (a) and (b) are schematic diagrams showing another example of the planar layout structure of the output circuit 12. Figure 14 In the example (a), tap regions 122A and tap regions 123A are alternately arranged in the X direction between the resistor regions 121. A tap for supplying VSS to the P-type substrate is formed in the tap region 122A, and a tap for supplying VDDIO to the N-type well is formed in the tap region 123A.

[0092] exist Figure 14 In the example (b), the protection resistor R3 is rectangular and extends in the X direction, and is divided into four resistor regions 121A arranged in the Y direction. Between the resistor regions 121A, a tap region 122B is formed with a tap for supplying VSS to the P-type substrate, and a tap region 123B is formed with a tap for supplying VDDIO to the N-type well. Figure 14 In the example of (b), the tap areas 122B and the tap areas 123B are alternately arranged in the X direction.

[0093] It should be noted that in Figure 14In the example of (b), the tap areas 122B and the tap areas 123B may also be arranged alternately in the Y direction.

[0094] This modified example also achieves the same functions and effects as the aforementioned embodiment. Specifically, noise applied to the external output terminal OUT is attenuated by the protective resistor R3 before reaching the output transistors P1 and N1. Furthermore, the noise applied to the external output terminal OUT is absorbed by the taps formed in the tap regions 122A and 123A or the tap regions 122B and 123B. This suppresses the propagation of noise that can cause latch-up. Furthermore, since the tap regions 122A and 123A or the tap regions 122B and 123B are dispersed across multiple locations, the noise absorption effect can be achieved more uniformly.

[0095] It should be noted that, in the above embodiment, the protection resistors R1 , R2 , and R3 are divided into four resistance areas, but the number of resistance areas is not limited to four.

[0096] It should be noted that in the output circuit of the above embodiment, both the P-type and N-type output transistors are single-stage transistors, but the present invention is not limited thereto. For example, a structure comprising multiple transistors connected in series, such as two or three stages, is also possible. Furthermore, the output circuit of the above embodiment may also be an input-output circuit including an input circuit.

[0097] -Industrial Applicability-

[0098] In the present disclosure, the occurrence of a latch-up phenomenon can be sufficiently suppressed in a semiconductor integrated circuit device, thereby contributing to, for example, improvement in the performance of a semiconductor chip.

[0099] -Explanation of symbols-

[0100] 1 Semiconductor integrated circuit devices

[0101] 11, 12 output circuit

[0102] 21, 21A, 22, 22A resistance zone

[0103] 52, 54 fins

[0104] 121, 121A resistance area

[0105] OUT External output terminal

[0106] P1, N1 output transistors

[0107] D1, D2 ESD protection diodes

[0108] R1, R2, R3 protection resistors

Claims

1. A semiconductor integrated circuit device comprising an output circuit, characterized in that: The output circuit includes: External output terminal; a first output transistor for outputting an output signal to the external output terminal; a first ESD (ElectroStatic Discharge) protection diode connected to the external output terminal; and a first protection resistor connected between the first output transistor and the first ESD protection diode, In a top view, the first output transistor and the first ESD protection diode are arranged separately, and the first protection resistor is arranged between the first output transistor and the first ESD protection diode. The first protection resistor is formed in a plurality of resistor regions, and a tap for supplying a power supply voltage to a substrate or a well is formed between the resistor regions.

2. The semiconductor integrated circuit device according to claim 1, wherein: The first output transistor and the first ESD protection diode are arranged separately in a first direction, The plurality of resistance regions are spaced apart and arranged in a second direction perpendicular to the first direction.

3. The semiconductor integrated circuit device according to claim 1, wherein: The first output transistor and the first ESD protection diode are arranged separately in a first direction, The plurality of resistance regions are spaced apart from each other in the first direction.

4. The semiconductor integrated circuit device according to claim 1, wherein: The tap has a diffusion region in a fin structure.

5. The semiconductor integrated circuit device according to claim 1, wherein: A tap for supplying a first power supply voltage to a substrate or a well and a tap for supplying a second power supply voltage different from the first power supply voltage to the substrate or the well are formed in a single region between the resistance regions.

6. The semiconductor integrated circuit device according to claim 1, wherein: The output circuit includes: a second output transistor for outputting an output signal to the external output terminal; a second ESD protection diode connected to the external output terminal; and a second protection resistor connected between the second output transistor and the second ESD protection diode, In a top view, the second output transistor and the second ESD protection diode are arranged separately, and the second protection resistor is arranged between the second output transistor and the second ESD protection diode. The second protection resistor is formed in a plurality of second resistor regions, and a tap for supplying a power supply voltage to a substrate or a well is formed in a region between the second resistor regions.

7. The semiconductor integrated circuit device according to claim 1, wherein: The output circuit includes: a second output transistor that outputs an output signal to the external output terminal; and a second ESD protection diode connected to the external output terminal, In a top view, the second output transistor is arranged adjacent to the first output transistor, and the second ESD protection diode is arranged adjacent to the first ESD protection diode. The first protection resistor is arranged between the first and second output transistors and the first and second ESD protection diodes.

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