A superjunction semiconductor field effect transistor with a virtual substrate

Abstract

The present invention relates to the technical field of field effect transistors, and discloses a superjunction semiconductor field effect transistor with a virtual substrate, which includes a P-type substrate. There is a P-type buffer layer in the upper left of the P-type substrate, and an N-type buffer layer in the upper right of it. There is a drain N-type heavily doped region in the upper right of the N-type buffer layer. There is an isolation oxide layer directly above the P-type substrate, and a superjunction layer above the isolation oxide layer. There is a P well on the left side of the superjunction layer, and a source N-type heavily doped region on the left side of the P well. A source electrode, a gate electrode and a drain electrode are provided above the superjunction layer. The right side of the superjunction layer is a drain N-type heavily doped region, which is used to form an ohmic contact between the drain electrode and the N-type buffer layer, the superjunction P columns and the superjunction N columns. The present invention uses a virtual substrate, which effectively makes the surface electric field distributions of the substrate and the superjunction tend to be consistent, eliminates the substrate-assisted depletion effect, greatly reduces the specific on-resistance of the device, and greatly improves the breakdown voltage. At the same time, it can effectively prevent the leakage current between the substrate and the superjunction, and greatly improves the maximum output power.

Description

Technical Field

[0001] The present invention relates to the technical field of field effect transistors, and particularly to a superjunction laterally double-diffused metal oxide semiconductor field effect transistor with a virtual substrate. Background Art

[0002] The laterally double-diffused metal oxide semiconductor field effect transistor (LDMOS) has become one of the main devices for power processing and conversion due to its excellent advantages such as high input impedance, easy driving, and high frequency. Compared with traditional LDMOS, the superjunction LDMOS (SJLDMOS) has great performance advantages. However, applying the superjunction theory to lateral devices has the problem of substrate-assisted depletion effect. When the superjunction P-columns have not been fully depleted, the superjunction N-columns have been completely depleted by the superjunction P-columns and the substrate. To solve the substrate-assisted depletion effect, researchers have proposed many optimized structures from the perspective of changing the substrate, such as optimized technologies like sapphire, diamond, or SOI technology. Another main optimization technology is to compensate for the substrate-assisted depletion effect by adding a buffer layer in the drift region and between the drift region and the substrate. For example, CN104716190B discloses a new SJ-LDMOS device, which fabricates a semi-superjunction on an N-type substrate epitaxial layer and introduces a P-type buried layer in the semi-superjunction region. Compared with the traditional superjunction, this invention compensates for the charge imbalance between the N-type column region and the P-type column region in the superjunction through the combined action of the N-region and the P-type buried layer, overcomes the substrate-assisted effect, and improves the breakdown voltage. However, the presence of the substrate still hinders the superjunction structure from achieving the theoretical optimal performance in lateral devices because this solution sacrifices a part of the channel region, also reduces the concentration of the superjunction due to compensation, and the concentration increase of the P-type doping layer in this solution is limited. If the concentration is too large, a large space charge region will be formed, making it difficult for the device to have the characteristics of an ideal superjunction. Summary of the Invention

[0003] Aiming at the above deficiencies existing in the prior art, the purpose of the present invention is to provide a superjunction semiconductor field effect transistor with a virtual substrate that eliminates the substrate-assisted depletion effect and has a better breakdown voltage and specific on-resistance relationship.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] A superjunction semiconductor field effect transistor with a virtual substrate, comprising a P-type substrate. There is a P-type buffer layer in the upper left of the P-type substrate, and an N-type buffer layer in the upper right. There is a drain N-type heavily doped region in the upper right of the N-type buffer layer. There is an isolation oxide layer directly above the P-type substrate. There is a superjunction layer above the isolation oxide layer. The superjunction layer includes superjunction P columns and superjunction N columns. There is a P well on the left side of the superjunction layer, and a source N-type heavily doped region on the left side of the P well. There are a source electrode, a gate electrode and a drain electrode above the superjunction layer. The P-type buffer layer is connected to the source electrode, and the drain N-type heavily doped region is connected to the drain electrode. There is a drain N-type heavily doped region on the right side of the superjunction layer, which is used to form an ohmic contact between the drain electrode and the N-type buffer layer, the superjunction P columns and the superjunction N columns.

[0006] Preferably, the depth of the superjunction layer including the superjunction P columns and the superjunction N columns is 3 μm, and the lengths of the superjunction N columns and the superjunction P columns in the superjunction layer are 15 - 25 μm.

[0007] Preferably, the widths of the superjunction P columns and the superjunction N columns are both 0.5 μm.

[0008] Preferably, the doping concentration of the superjunction N columns is 3×10 16 cm -3 , and the doping concentration of the superjunction P columns is 3×10 16 cm -3 .

[0009] Preferably, the length of the N-type buffer layer is 12 μm, the depth is 6 μm, and the doping concentration is 3×10 15 cm -3 .

[0010] Preferably, the length of the P-type buffer layer is 6 μm, the depth is 3 μm, and the doping concentration is 8×10 16 cm -3 .

[0011] Preferably, the thickness of the isolation oxide layer is 0.1 - 0.5 μm.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] (1) Thoroughly eliminate the substrate-assisted depletion effect: The structure proposed in the present invention first separates the superjunction layer from the substrate through an isolation oxide layer to alleviate the substrate-assisted depletion effect. However, the electric field caused by the capacitance of the insulating layer still affects the electric field distribution layer of the superjunction. Therefore, a P-type buffer layer is added on the substrate and connected to the source, and a heavily doped N-type drain region is added to the N-type buffer layer region and connected to the drain. The device proposed in the present invention connects the substrate to the source and drain electrodes, and changes the surface potential of the substrate from zero to the high voltage of the drain, making it have the same voltage as the superjunction layer. A new electric field peak is formed on the substrate surface, making it closer to the rectangular electric field distribution of the superjunction layer. The influence of the substrate on the superjunction layer is greatly weakened, and finally the substrate-assisted depletion effect is completely eliminated.

[0014] (2) Significantly improve the breakdown voltage: The N-type buffer layer can reduce the depletion of the substrate on the superjunction N columns, reduce the electric field absorption of the superjunction P columns on the heavily doped N-type drain region, thereby alleviating the substrate-assisted depletion effect and improving the device performance; a new electric field peak is added on the device surface to improve the surface electric field distribution and increase the breakdown voltage of the device.

[0015] (3) Significantly reduce the specific on-resistance: Since the substrate-assisted depletion effect is eliminated, the device can operate approximately under the mechanism of an ideal superjunction. Therefore, under the condition of increasing the breakdown voltage, the concentrations of the superjunction N columns and superjunction P columns can be greatly increased compared with traditional devices, thus increasing the current density of the superjunction N columns and superjunction P columns and significantly reducing the specific on-resistance of the device.

[0016] (4) Effectively prevent the leakage current between the substrate and the superjunction N columns and superjunction P columns: Compared with other optimization methods, due to the electric field modulation of the device by the P-type buffer layer, N-type buffer layer and heavily doped N-type region, the equipotential lines between the superjunction layer and the P-type substrate are perpendicular to each other, and supplemented by the oxide layer between the two, making the carriers unable to move between these two layers, so the leakage current between the superjunction layer and the substrate can be prevented, making the device closer to the working characteristics of an ideal superjunction. Description of the Drawings

[0017] Other features, objects and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0018] Figure 1 Schematic diagram of a superjunction semiconductor field effect transistor with a virtual substrate according to the present invention;

[0019] In the figure: 1 - P-type substrate, 2 - P-type buffer layer, 3 - isolation oxide layer, 4 - heavily doped N-type source region, 5 - P well, 6 - source electrode, 7 - gate electrode, 8 - drain electrode, 9 - superjunction P column, 10 - superjunction N column, 11 - heavily doped N-type drain region, 12 - N-type buffer layer. Detailed Embodiments

[0020] The present invention will be described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made. These all belong to the protection scope of the present invention.

[0021] A superjunction semiconductor field effect transistor with a virtual substrate, comprising a P-type substrate 1. The upper left of the P-type substrate 1 is a P-type buffer layer 2, and the upper right is an N-type buffer layer 12. The upper right of the N-type buffer layer 12 is a drain N-type heavily doped region 11. Directly above the P-type substrate 1 is an isolation oxide layer 3. Above the isolation oxide layer 3 is a superjunction layer, which includes alternately arranged superjunction P-columns 9 and superjunction N-columns 10. To the left of the superjunction P-columns 9 and superjunction N-columns 10 is a P-well 5, and to the left of the P-well 5 is a source N-type heavily doped region 4. Above the superjunction P-columns 9 and superjunction N-columns 10 are a source electrode 6, a gate electrode 7, and a drain electrode 8. The P-type buffer layer 2 is connected to the source electrode 6, the drain N-type heavily doped region 11 is connected to the drain electrode 8. To the right of the superjunction P-columns 9 and superjunction N-columns 10 is the drain N-type heavily doped region 11, which is used to form an ohmic contact between the drain electrode 8 and the N-type buffer layer 12 and the superjunction P-columns 9 and superjunction N-columns 10.

[0022] The depth of the superjunction layer including the superjunction P-columns 9 and superjunction N-columns 10 is 3 μm. The lengths of the superjunction N-columns and superjunction P-columns in the superjunction layer are 15 - 25 μm. The widths of both the superjunction P-columns 9 and superjunction N-columns 10 are 0.5 μm. The doping concentration of the superjunction N-columns is 3×10 16 cm -3 , and the doping concentration of the superjunction P-columns is 3×10 16 cm -3 .

[0023] The length of the N-type buffer layer 12 is 12 μm, the depth is 6 μm, and the doping concentration is 3×10 15 cm -3 ; the length of the P-type buffer layer 2 is 6 μm, the depth is 3 μm, and the doping concentration is 8×10 16 cm -3 .

[0024] The thickness of the isolation oxide layer 3 is 0.1 - 0.5 μm.

[0025] Simulation experiments found that under the condition that the superjunction length is 20 μm, compared with the traditional SJLDMOS, the specific on-resistance of the SJLDMOS proposed by the present invention is reduced by 60.09% (11.59 mΩ·cm 2), the breakdown voltage increases by 28.9% (467V). It can be seen that the SJLDMOS of the present invention has more obvious advantages in the high-voltage field.

[0026] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various deformations or modifications within the scope of the claims, which does not affect the essence of the present invention.

Claims

1. A superjunction semiconductor field effect transistor with a virtual substrate, characterized in that, It includes a P-type substrate. There is a P-type buffer layer in the upper left of the P-type substrate, an N-type buffer layer in the upper right, a drain N-type heavily doped region in the upper right of the N-type buffer layer, an isolation oxide layer directly above the P-type substrate, a superjunction layer above the isolation oxide layer. The superjunction layer includes superjunction P pillars and superjunction N pillars. There is a P well on the left side of the superjunction layer, a source N-type heavily doped region on the left of the P well. There are a source electrode, a gate electrode and a drain electrode above the superjunction layer. The P-type buffer layer is connected to the source electrode, the drain N-type heavily doped region is connected to the drain electrode. There is a drain N-type heavily doped region on the right side of the superjunction layer, which is used to form an ohmic contact between the drain electrode and the N-type buffer layer, superjunction P pillars and superjunction N pillars.

2. The superjunction semiconductor field effect transistor with a virtual substrate according to claim 1, characterized in that, The depth of the superjunction layer including superjunction P pillars and superjunction N pillars is 3 μm, and the lengths of the superjunction N pillars and superjunction P pillars in the superjunction layer are 15 - 25 μm.

3. The superjunction semiconductor field effect transistor with a virtual substrate according to claim 1, characterized in that, The widths of the superjunction P pillars and superjunction N pillars are both 0.5 μm.

4. The superjunction semiconductor field effect transistor with a virtual substrate according to claim 1, characterized in that, The doping concentration of the superjunction N column is 3×10 16 cm -3 , and the doping concentration of the superjunction P column is 3×10 16 cm -3 .

5. The superjunction semiconductor field effect transistor with a virtual substrate according to claim 1, characterized in that, The length of the N-type buffer layer is 12 μm, the depth is 6 μm, and the doping concentration is 3×10 15 cm -3 .

6. The superjunction semiconductor field effect transistor with a virtual substrate according to claim 1, characterized in that, The length of the P-type buffer layer is 6 μm, the depth is 3 μm, and the doping concentration is 8×10 16 cm -3 .

7. The superjunction semiconductor field effect transistor with a virtual substrate according to claim 1, characterized in that, The thickness of the isolation oxide layer is 0.1 - 0.5 μm.

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