Capacitor manufacturing method

Abstract

The present specification relates to a capacitor manufacturing method comprising the steps of: a) forming a stack comprising, in order from an upper surface of a substrate, a first conductive layer made of aluminum or an aluminum-based alloy, a first electrode, a first dielectric layer, and a second electrode; b) etching an upper portion of the stack by chemical plasma etching, said chemical plasma etching being interrupted before the upper surface of the first conductive layer; and c) etching a lower portion of the stack by physical plasma etching, said physical plasma etching being interrupted in the upper surface of the first conductive layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the manufacturing of integrated circuits, and more specifically, to the manufacturing of integrated circuits comprising capacitors, such as passive integrated circuits. BACKGROUND

[0002] Various methods of manufacturing integrated circuits comprising capacitors are provided. These methods have various drawbacks. It would be desirable to have a method of manufacturing integrated circuits comprising capacitors that overcomes all or part of the drawbacks of known methods. SUMMARY

[0003] One embodiment provides a method of manufacturing a capacitor, comprising the successive steps of:

[0004] a. forming a stack comprising successively, from the upper surface of a substrate, a first conductive layer made of aluminum or an aluminum-based alloy, a first electrode, a first dielectric layer and a second electrode;

[0005] b. etching the upper part of the stack by chemical plasma etching, said chemical plasma etching being interrupted before the upper surface of the first conductive layer; and

[0006] c. etching the lower part of the stack by physical plasma etching, said physical plasma etching being interrupted on the upper surface of the first conductive layer.

[0007] According to one embodiment, in step b), the chemical plasma etching comprises a first step of chemical plasma etching by means of a chlorine-based plasma, followed by a second step of chemical plasma etching by means of a fluorine-based plasma.

[0008] According to one embodiment, the second chemical plasma etching step and the physical plasma etching step are implemented in the same etching chamber, a purging step of said etching chamber being implemented between the two steps.

[0009] According to one embodiment, in step b), the chemical plasma etching comprises a single step of chemical plasma etching by means of a chlorine-based plasma.

[0010] According to one embodiment, in step b), the chemical plasma etching comprises a single step of chemical plasma etching by means of a fluorine-based plasma.

[0011] According to one embodiment, the stack further comprises a second conductive layer coating the second electrode.

[0012] According to one embodiment, in step c), the physical plasma etching is implemented by means of an argon plasma.

[0013] According to one embodiment, the second conductive layer is made of aluminum or an alloy comprising aluminum.

[0014] According to an embodiment, the first electrode is made of tantalum nitride.

[0015] According to an embodiment, said lower part of the stack comprises at least a portion of the thickness of the first electrode. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above features and advantages and other will be described in detail below with respect to specific embodiments given by way of illustration and not limitation, with reference to the following drawings, wherein:

[0017] Figure 1 is a simplified cross-sectional view of an example of a capacitor according to an embodiment;

[0018] Figure 2 is a cross-sectional view showing a step of a method of manufacturing a capacitor according to an embodiment; Figure 1

[0019] Figure 3 is a cross-sectional view showing another step of a method of manufacturing a capacitor according to an embodiment; Figure 1

[0020] Figure 4 is a cross-sectional view showing another step of a method of manufacturing a capacitor according to an embodiment; Figure 1

[0021] Figure 5 is a cross-sectional view showing another step of a method of manufacturing a capacitor according to an embodiment; Figure 1

[0022] Figure 6 is a cross-sectional view showing a step of a method of manufacturing a capacitor according to a first embodiment; Figure 1

[0023] Figure 7 is a cross-sectional view showing another step of a method of manufacturing a capacitor according to a first embodiment; Figure 1

[0024] Figure 8 is a cross-sectional view showing another step of a method of manufacturing a capacitor according to a first embodiment; Figure 1

[0025] Figure 9 is a cross-sectional view showing another step of a method of manufacturing a capacitor according to a first embodiment; Figure 1

[0026] Figure 10 is a cross-sectional view showing a step of a method of manufacturing a capacitor according to a second embodiment; and Figure 1

[0027] Figure 11 ​​​​​​​​​This illustrates the second embodiment. Figure 1 A cross-sectional view of another step in the manufacturing process of the capacitor. Detailed Implementation

[0028] In different figures, the same features are designated by the same reference. In particular, common structural and / or functional features in various embodiments may have the same reference and may be provided with the same structure, dimensions, and material properties.

[0029] For clarity, only steps and elements useful for understanding the embodiments described herein are described in detail. In particular, the etching steps that expose metal layers to make electrical contacts on the lower electrode of the capacitor in an integrated circuit are primarily considered herein. Other steps in the methods of manufacturing capacitor circuits and integrated circuits are within the capabilities of those skilled in the art and will not be described in detail.

[0030] Unless otherwise stated, when referring to two elements connected together, it means there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected, or they can be coupled through one or more other elements.

[0031] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative position qualifiers such as the terms “above,” “below,” “above,” “below,” etc., or orientation qualifiers such as “horizontal,” “vertical,” etc., the orientation shown in the figure shall be used.

[0032] Unless otherwise stated, “about,” “approximately,” “basically,” and “in sequence” indicate up to 10%, preferably up to 5%.

[0033] Figure 1 This is a cross-sectional view of an example capacitor 11 according to an embodiment.

[0034] The capacitor 11 includes, starting from the upper surface 12 of the substrate or support member 21, the following components in sequence:

[0035] Conductive layer 13, also known as redistribution layer (RDL);

[0036] First electrode 15, also known as lower electrode;

[0037] Layer 17 is made of dielectric material; and

[0038] The second electrode 19 is also known as the upper electrode.

[0039] In the example shown, the redistribution layer 13, which may be a conductive layer or a conductive layer, is in contact with the upper surface of the substrate 21 through its lower surface, the lower electrode 15 is in contact with the upper surface of the layer 13 through its lower surface, the dielectric layer 17 is in contact with the upper surface of the lower electrode 15 through its lower surface, and the upper electrode 19 is in contact with the upper surface of the dielectric layer 17 through its lower surface.

[0040] According to one aspect of the embodiment, the conductive layer 13 is made of aluminum or an alloy including aluminum, such as an alloy of aluminum and copper (AlCu) or an alloy of aluminum, copper and silicon (AlSiCu). For example, the thickness of layer 13 is in the range of 0.5 μm to 3 μm, preferably equal to about 1.5 μm.

[0041] Electrodes 15 and 19 can be made of the same material or different materials. Electrodes 15 and 19 are made of, for example, tantalum nitride. As a variation, electrodes 15 and / or 19 can be made of polycrystalline silicon or platinum. As an example, the thickness of electrode 15 is in the range of 20 nm to 200 nm, preferably on the order of about 80 nm. As an example, the thickness of electrode 19 is in the range of 20 nm to 200 nm, preferably on the order of about 80 nm.

[0042] The dielectric layer 17 is made of, for example, silicon nitride (Si3N4) or tantalum oxynitride (TaON). ​​As an example, the thickness of the dielectric layer 17 is in the range of 20 nm to 600 nm, preferably equal to about 110 nm or about 440 nm.

[0043] exist Figure 1 In the example, capacitor 11 also includes:

[0044] Conductive layer 23 is located on the upper surface of electrode 19 and is in contact with the upper surface of electrode 19; and

[0045] Metal pads 25 are located on the upper surface of conductive layer 23 and are in contact with the upper surface of conductive layer 23.

[0046] As a variation, the upper conductive layer 23 can be omitted, so that the metal pad 25 is arranged on and in contact with the upper electrode 19 of the capacitor.

[0047] The support 21 is made of glass or silicon, preferably with high resistance. The support 21 and layer 13 are separated from each other, for example by a dielectric layer not shown, such as an oxide layer, such as undoped silicon glass (USG) or any other silicon oxide.

[0048] The conductive layer 23 is made of aluminum, for example, and has a thickness, for example, in the range of 200 nm to 1 μm, preferably equal to about 400 nm. Layer 23 is particularly capable of increasing the lateral conductivity of the upper electrode 19 it covers.

[0049] The metal pad 25 is made of copper, for example.

[0050] In the example shown, electrodes 15 and 19, as well as layers 23 and 17, are recessed relative to conductive layer 13. In other words, a portion of conductive layer 13 is not covered by electrodes 15 and 19, as well as layers 23 and 17. This allows for electrical contact with the lower electrode 15 of the capacitor via conductive layer 13 during a manufacturing step not described in detail, for example, by means of a wire soldered to the upper surface of the exposed portion of layer 13.

[0051] like Figure 1 As shown, layers 15, 17, 19, and 23 form sidewall 14, where the sides of layers 15, 17, 19, and 23 are substantially coplanar with each other. Figure 1 As shown, layers 13 and 21 include ends (not shown) that terminate when extending to the right at the ends. The ends (not shown) of layers 13 and 21 are spaced apart from the right side of sidewall 14, and sidewall 14 is spaced apart from the left side of the ends (not shown) of layers 13 and 21. Sidewall 14 is on the upper surface of conductive layer 13 and protrudes from conductive layer 13 and substrate 21.

[0052] Figure 2 , Figure 3 , Figure 4 and Figure 5 It is shown Figure 1 A cross-sectional view of the sequential steps of an example manufacturing method for capacitor 11.

[0053] Figure 2 An initial stack is shown, which sequentially includes a support 21, a lower conductive layer 13, a lower electrode 15, a dielectric layer 17, an upper electrode 19, an upper conductive layer 23, and a protective layer 29 covering the upper surface of the upper conductive layer 23, for example made of resin.

[0054] At this stage, the layers of the stack are aligned. In particular, electrodes 15 and 19, as well as layers 17, 23, and 29, each extend over the entire upper surface of the lower conductive layer 13.

[0055] Figure 3 The structure obtained at the end of the step of partially removing the protective layer 29 and the upper conductive layer 23 which is opposite to the lower conductive layer 13 is shown.

[0056] The local removal of the protective layer 29 can be performed by photolithography.

[0057] Then, layer 23 can be etched by a first chemical plasma etching, for example, by using layer 29 as an etching mask, opposite to the openings formed in layer 29, using a chlorine-based plasma. In this example, during the first chemical etching, layer 23 is etched over its entire thickness.

[0058] In the example shown, the first chemical etching is interrupted on the upper surface of electrode 19.

[0059] Figure 4 The structure obtained at the end of the step of partially removing layers 19, 17 and 15 is shown, which is opposite to the portion of the lower conductive layer 13 that is to be exposed.

[0060] Layers 19, 17, and 15 can be etched using a second chemical plasma etching process, for example, by using layer 29 as an etching mask, opposite to the openings formed in layers 29 and 23, and utilizing a fluorine-based plasma. In this example, during the second chemical etching, layers 19, 17, and 15 are etched over their entire thickness.

[0061] In the example shown, the second chemical etching is interrupted on the upper surface of the conductive layer 13.

[0062] The second fluorine chemical etching step does indeed have the advantage of selectively etching layers 19, 17 and 15 on the aluminum-containing layer 13.

[0063] A drawback of this method is that during the second chemical plasma etching step, the fluorine-based plasma comes into contact with the upper surface of the aluminum-containing conductive layer 13. Then, fluorine atoms combine with aluminum atoms on the surface of layer 13, forming an aluminum fluoride (AlF) atomic layer 35 on the surface of layer 13. Figure 4 As schematically shown, layer 35 is non-uniform and discontinuously covers the exposed portion of conductive layer 13.

[0064] Figure 5 The structure obtained at the end of a subsequent wet chemical etching step is shown, for example by one or more acids, such as by a solution known by the trade name "Pvapox", which comprises a mixture of hydrofluoric acid (HF), ammonium fluoride (NH4F), acetic acid (CH3COOH), and benzotriazole (C6H5N3).

[0065] This wet chemical etching can be used, for example, to locally remove previously deposited material opposite the upper surface of the conductive layer 13. Figure 4 The passivation layer on the upper surface of the structure (not shown in the figure).

[0066] For example, prior to wet chemical etching, there is a step of depositing an oxide layer, such as a USG layer, over the entire structure (not detailed in the accompanying drawings). The wet chemical etching step is particularly effective at removing oxide layers located on... Figure 4 The top of the portion of layer 13 exposed during the plasma etching step and a portion of the oxide layer in contact with the upper surface of that portion.

[0067] exist Figure 5The etching solution used in the process tends to consume exposed portions of the conductive layer 13 on the surface. However, this surface etching is blocked by aluminum fluoride residue 35, which resists the solution used and, more generally, acid erosion.

[0068] This results in an uneven micromasking phenomenon on the upper surface of the conductive layer 13.

[0069] These non-uniformities reduce the quality of the electrical contacts subsequently achieved on the upper surface of layer 13. In particular, these non-uniformities do not allow for a good electrical connection between the conductor and layer 13 by soldering.

[0070] Figure 6 , Figure 7 , Figure 8 and Figure 9 This illustrates the first embodiment. Figure 1 A cross-sectional view of the sequential steps of an example manufacturing method for capacitor 11.

[0071] Figure 6 It shows the relationship with Figure 2 The stack shown is the same as the initial stack.

[0072] Figure 7 The structure obtained at the end of the step of partially removing the protective layer 29 and the upper conductive layer 23 opposite to the portion of the lower conductive layer 13 that is to be discussed is shown.

[0073] These steps, for example, are combined with the above. Figure 3 The steps described are the same or similar.

[0074] Specifically, the local removal of the protective layer 29 can be performed by photolithography. Then, layer 23 can be etched relative to the openings formed in layer 29 by a first chemical plasma etching, such as by a chlorine-based plasma.

[0075] In the example shown, the first chemical etching is interrupted on the upper surface of electrode 19.

[0076] Figure 8 The structure obtained at the end of the step of partially removing layers 19 and 17 opposite to the desired exposed portion of the lower conductive layer 13 is shown.

[0077] Layers 19 and 17 can be etched by a second chemical plasma etching, for example by means of a fluorine-based plasma, similar to the bonding described above. Figure 4 As described.

[0078] In this example, during the second chemical etching, layers 19 and 17 are etched over their entire thickness.

[0079] Combined with the above Figure 4Unlike the description, in this example, the second chemical plasma etching is interrupted before reaching the upper surface of the lower conductive layer 13.

[0080] In the example shown, the second chemical plasma etching is interrupted on the upper surface of the lower electrode 15.

[0081] The second chemical plasma etching is similar to the combination described above. Figure 4 As described. As an example, the second chemical plasma etching is carried out by means of fluorine-based plasma.

[0082] The second chemical etching step is stopped or stopped before it reaches layer 13, and the fluorine-based plasma does not come into contact with layer 13, which allows the formation of the aluminum-fluorine layer 35 to be avoided. Figure 4 ).

[0083] Figure 9 The structure obtained at the end of a partial removal step of the lower electrode layer 15, which is opposite to the portion of the lower conductive layer 13 that is to be exposed, is shown.

[0084] In this example, layer 15 is removed by physical plasma etching using a plasma of a gas that has no affinity for aluminum, such as a neutral gas plasma, for example, argon or nitrogen plasma, preferably argon plasma. In this example, the physical etching is induced by neutral gas ions, such as argon ions, accelerated by a bias voltage.

[0085] The physical etching rate of electrode 15 is, for example, approximately 50 nm / min, which is 10 times that during fluorine chemical plasma etching and 15 times that during chlorine chemical plasma etching.

[0086] In this example, physical plasma etching is interrupted when the upper surface of conductive layer 13 is exposed, that is, when electrode 15 is etched over its entire thickness.

[0087] and Figure 6 to Figure 9 The advantage of this method is that it is revealed onto the conductive layer 13 through neutral physical plasma etching. This allows for the avoidance of aluminum fluoride formation on the exposed surface of the conductive layer 13. Therefore, it is possible to avoid the formation of aluminum fluoride on the upper surface of the conductive layer 13. Figure 5 The aforementioned non-uniformity allows for the formation of more reliable and higher-performance electrical connections on the upper surface of layer 13.

[0088] As a variant not shown, the first chemical plasma etching ( Figure 7 It can be implemented through all or part of the thickness of the upper electrode 19 and interrupted in the electrode 19 or on the upper surface of the dielectric layer 17.

[0089] In another variant not shown, the first chemical plasma etching can be performed through all or part of the thickness of the dielectric layer 17 and interrupted in the dielectric layer 17 or on the upper surface of the electrode 15.

[0090] In another variant, not shown, a second chemical plasma etching step ( Figure 8 The process is interrupted before reaching the upper surface of electrode 15, for example, on the upper surface of dielectric layer 17 or within dielectric layer 17.

[0091] In another variation, not shown, a portion of the thickness of electrode 15 is removed during the second chemical plasma etching step. In other words, the second chemical plasma etching step is interrupted in the lower electrode layer 15.

[0092] As an example, the first chemical plasma etching step is performed in the first etching tool, and the second chemical plasma etching step and the physical plasma etching step are performed in a second etching tool that is different from the first tool.

[0093] In this case, the etching chamber of the second tool can be cleaned between the second chemical plasma etching step and the physical plasma etching step to prevent fluorine atoms from remaining in the etching chamber during the physical plasma etching step. For example, the duration of the cleanup varies from 10 to 20 seconds.

[0094] It should be noted that by omitting the upper aluminum-based conductive layer 23, the first step of chemical plasma etching using chlorine-based plasma can be omitted. In other words, two etching steps can be provided, namely, the second step of chemical plasma etching using fluorine-based plasma. Figure 8 ), and the physical plasma etching step using neutral gas plasma, such as argon plasma ( Figure 9 ).

[0095] Figure 10 and Figure 11 This illustrates the second embodiment. Figure 1 A cross-sectional view of the sequential steps of an example manufacturing method for capacitor 11.

[0096] In this second embodiment, the second step of chemical plasma etching using fluorine-based plasma is omitted. In other words, only two etching steps are provided: a first step of chemical plasma etching using chlorine-based plasma and a step of physical plasma etching using neutral gas plasma, such as argon plasma.

[0097] As an example, it is from similar to Figure 6 It starts with the initial stack.

[0098] Figure 10The structure is shown at the end of the step of partially removing protective layers 29 and layers 23, 19 and 17 opposite to the desired exposed portion of the lower conductive layer 13.

[0099] The local removal of the protective layer 29 can be performed by photolithography.

[0100] Then, layers 23, 19 and 17 can be etched using layer 29 as an etching mask, opposite to the openings formed in layer 29, by a first chemical plasma etching, for example, by means of a chlorine-based plasma.

[0101] The first chemical plasma etching is interrupted before reaching the upper surface of the lower conductive layer 13.

[0102] In the example shown, the first chemical plasma etching is interrupted on the upper surface of the lower electrode 15.

[0103] Figure 11 The structure obtained at the end of a partial removal step of the lower electrode layer 15, which is opposite to the portion of the lower conductive layer 13 that is to be exposed, is shown.

[0104] In this example, layer 15 is removed by physical plasma etching, similar to the bonding described above. Figure 9 As described.

[0105] In this example, the side surface of layer 15 is substantially coplanar with the corresponding side surfaces of layers 17, 19, 23, and 29, forming sidewalls 16 of these corresponding side surfaces of layers 17, 19, 23, and 29 and the side surface of layer 15. In this disclosure... Figure 9 and Figure 11 Sidewall 16 can be seen in the middle.

[0106] As a variant not shown, the first chemical plasma etching ( Figure 10 The process can be interrupted before reaching the upper surface of electrode 15, for example, on the upper surface of dielectric layer 17 or in dielectric layer 17.

[0107] In another variant, not shown, a portion of the thickness of electrode 15 is removed during the first chemical plasma etching step.

[0108] like Figure 4 , Figure 5 , Figure 9 and Figure 11 As shown, the protective layer 29 can be removed from the upper surface of the conductive layer 23, and a metal pad 25 can be formed on the conductive pad. When the conductive layer 23 is omitted, the metal pad 25 can be formed on the upper electrode 19.

[0109] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will arise. In particular, the described embodiments are not limited to examples of numerical values ​​or examples of materials mentioned in this disclosure.

[0110] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0111] A method for manufacturing a capacitor can be summarized as comprising the following sequential steps: A) forming a stack comprising: a first conductive layer (13), a first electrode (15), a first dielectric layer (17), and a second electrode (19) made of aluminum or an aluminum-based alloy sequentially from the upper surface of a substrate (21); b) etching the upper portion of the stack by chemical plasma etching, the chemical plasma etching being interrupted before the upper surface of the first conductive layer (13); and c) etching the lower portion of the stack by physical plasma etching, the physical plasma etching being interrupted before the upper surface of the first conductive layer (13).

[0112] In step b), the chemical plasma etching may include a first step of chemical plasma etching using chlorine-based plasma, followed by a second step of chemical plasma etching using fluorine-based plasma.

[0113] The second chemical plasma etching step and the physical plasma etching step can be performed in the same etching chamber, with a purification step of the etching chamber performed between the two steps.

[0114] In step b), the chemical plasma etching may include a single step of chemical plasma etching using chlorine-based plasma.

[0115] In step b), the chemical plasma etching may include a single step of chemical plasma etching using fluorine-based plasma.

[0116] The stack may also include a second conductive layer (23) coated with the second electrode.

[0117] In step c), physical plasma etching can be performed using argon plasma.

[0118] The second conductive layer (23) may be made of aluminum or an alloy including aluminum.

[0119] The first electrode (15) can be made of tantalum nitride.

[0120] The lower part of the stack may include at least a portion of the thickness of the first electrode (15).

[0121] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned and / or listed in the application data sheets are incorporated herein by reference in their entirety. If necessary, aspects of the embodiments may be modified to incorporate concepts from various patents, applications, and publications to provide further embodiments.

[0122] These and other changes can be made to the embodiments based on the above detailed description. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method comprising: forming a capacitor, comprising: forming a stack, comprising: forming a first conductive layer on a first surface of a substrate, the first conductive layer comprising aluminum or an aluminum-based alloy; forming a first electrode on a second surface of the first conductive layer; forming a first dielectric layer on the first electrode; and forming a second electrode on the first dielectric layer; etching an upper portion of the stack by a chemical plasma etch, the chemical plasma etch being stopped before reaching the second surface of the first conductive layer; and etching a lower portion of the stack by a physical plasma etch, the physical plasma etch being stopped at the second surface of the first conductive layer.

2. The method of claim 1, wherein the chemical plasma etch comprises a chlorine-based chemical plasma etch step followed by a fluorine-based chemical plasma etch step.

3. The method of claim 2, wherein the fluorine-based chemical plasma etch step and the physical plasma etch step are performed in an etch chamber.

4. The method of claim 3, further comprising a purging step in which the etch chamber is purged after the fluorine-based chemical plasma etch step and before the physical plasma etch step.

5. The method of claim 1, wherein the chemical plasma etch comprises a chlorine-based chemical plasma etch step.

6. The method of claim 1, wherein the chemical plasma etch comprises a fluorine-based chemical plasma etch step.

7. The method of claim 1, wherein the stack further comprises a second conductive layer, the second conductive layer being on and extending along the second electrode.

8. The method of claim 1, wherein the physical plasma etch is an argon-based physical plasma etch.

9. The method of claim 7, wherein the second conductive layer is made of aluminum or an alloy comprising aluminum.

10. The method of claim 1, wherein the first electrode is made of tantalum nitride.

11. The method of claim 1, wherein the lower portion of the stack comprises at least a portion of a thickness of the first electrode.

12. A method comprising: forming a stacked structure, comprising: forming a first conductive layer on a first surface of a substrate; forming a first electrode on the first conductive layer; forming a dielectric layer on the first electrode; forming a second electrode on the dielectric layer; and forming a protective layer covering the second electrode, the dielectric layer, the first electrode, and the first conductive layer; forming a sidewall, comprising: forming respective sidewalls of the first electrode, the dielectric layer, the second electrode, and the protective layer by removing respective portions of the first electrode, the dielectric layer, the second electrode, and the protective layer, respectively; wherein removing the respective portions of the first electrode, the dielectric layer, and the second electrode comprises an etching step; wherein the etching step comprises: etching the second electrode and the dielectric layer with a fluorine-based chemical plasma etch followed by etching the first electrode with a physical plasma etch; wherein the physical plasma etch is interrupted in an upper surface of the first electrically conductive layer, and wherein the physical plasma etch is performed by means of a plasma of a neutral gas having no affinity for aluminum.

13. The method of claim 12, wherein removing respective portions of the protective layer comprises a photolithography step.

14. The method of claim 12, wherein the fluorine-based chemical plasma etch is terminated before reaching the first electrically conductive layer.

15. The method of claim 12, wherein: forming the stack structure further comprises forming a second electrically conductive layer on the second electrode; forming the protective layer further comprises forming the protective layer on the second electrically conductive layer; and forming the sidewall further comprises forming a respective side surface of the second electrically conductive layer by removing a respective portion of the second electrically conductive layer.

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