A timed hardware reset device for unattended embedded systems

Abstract

The invention discloses a timing hardware reset device for an unattended embedded system. The device comprises a power switch S1 and a relay RLY1, wherein the output end of the power switch S1 is connected to the common end of the contact of the relay RLY1, the first output end of the contact of the relay RLY1 is respectively connected to one end of its first coil C1 and a setting control circuit, the setting control circuit is connected to the other end of the first coil C1 of the relay RLY1, the second output end of the relay RLY1 is respectively connected to one end of its second coil C2 and a power supply line, the other end of the second coil C2 of the relay RLY1 is connected to the reset control circuit, the reset control circuit is connected to a controller, and the controller is connected to a clock chip. The invention controls the operation of a single-pole double-throw double-coil magnetic latching relay by the reset control circuit and the setting control circuit, thereby completing the power-on reset and automatic reset operations, and the operation is reliable.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, and in particular to a timing hardware reset device for an unattended embedded system. Background Art

[0002] In the field of electronic technology, with the continuous improvement of automation, embedded system devices with microcontrollers such as single-chip microcomputers, embedded systems, DSPs, and FPGAs as the core are increasingly widely used. While microcontrollers bring functional upgrades to hardware devices, they also bring reliability risks such as crashes. In order to minimize the risk of crashes, circuits such as "watchdogs" are generally added to the peripheral circuits of microcontrollers. When the microcontroller crashes, a reset signal can be output to perform a passive reset on the microcontroller. This type of reset is performed without powering off the system, and it is impossible to completely clean up the system garbage. As the continuous working time increases, the system garbage accumulates more and more, resulting in jams or even system crashes. In the end, manual intervention must be used to solve the problem through hardware reset, so that the unattended function cannot be truly reflected. At the same time, the synchronization between chips is also difficult to guarantee, especially for multi-core systems, which will also cause reliability risks such as jams or even system crashes. In order to effectively improve the reset effect, the hardware reset method of actively short-term power off and then power on after a certain delay is an effective technical development direction to solve the problem of incomplete reset. Summary of the invention

[0003] The purpose of the present invention is to provide a timing hardware reset device for an unattended embedded system in view of the deficiencies in the prior art.

[0004] To achieve the above-mentioned purpose, the present invention provides a timing hardware reset device for an unattended embedded system, comprising a power switch S1 and a relay RLY1, wherein the relay RLY1 is a single-pole double-throw double-coil magnetic latching relay, the output end of the power switch S1 is connected to the common end of the contacts of the relay RLY1, the first output end of the contacts of the relay RLY1 is respectively connected to one end of its first coil C1 and a setting control circuit, the setting control circuit is connected to the other end of the first coil C1 of the relay RLY1, the second output end of the relay RLY1 is respectively connected to one end of its second coil C2 and a power supply line, the other end of the second coil C2 of the relay RLY1 is connected to the reset control circuit, the reset control circuit is connected to a controller, and the controller is connected to a clock chip.

[0005] Furthermore, the setting control circuit includes a resistor R2 and a resistor R1, one end of which is connected to the first output end of the contact of the relay RLY1, the other end of the resistor R2 is respectively connected to one end of the resistor R4 and the positive end of the capacitor E1, the other end of the resistor R4 is respectively connected to one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is connected to the base of the transistor T2, the transistor T2 is an NPN type, the negative end of the capacitor E1, the other end of the resistor R6 and the emitter of the transistor T2 are all grounded, the other end of the resistor R1 is respectively connected to the collector of the transistor T2 and one end of the resistor R3, the other end of the resistor R3 is connected to the base of the transistor T1, the transistor T1 is a PNP type, its emitter is connected to the other end of the first coil C1, and the collector of the transistor T1 is grounded.

[0006] Furthermore, the reset control circuit includes a resistor R8 having one end connected to the controller, the other end of the resistor R8 being connected to one end of a resistor R7 and a resistor R9 respectively, the other end of the resistor R7 being connected to the base of the transistor T3, the collector of the transistor T3 being connected to the other end of the second coil C2, and its emitter and the other end of the resistor R9 being grounded.

[0007] Furthermore, the first coil C1 and the second coil C2 are connected in anti-parallel with a diode D1 and a diode D2 respectively.

[0008] Furthermore, the controller is a single chip microcomputer.

[0009] Furthermore, the model of the clock chip is DS1302.

[0010] Beneficial effect: The present invention controls the operation of a single-pole double-throw double-coil magnetic latching relay through a set control circuit and a reset control circuit, and realizes the function of automatic reset under the premise of satisfying the power-on reset function. During the power-on reset, no matter what connection position the contacts of the relay are in, the hardware of the embedded system can be powered normally under the action of the set control circuit. During the normal operation of the system, the reset control circuit is controlled by the processor and the clock chip, and the reset control circuit and the set control circuit cooperate to complete the automatic reset operation, and the operation is reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural diagram of a timed hardware reset device for an unattended embedded system. DETAILED DESCRIPTION

[0012] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The embodiments are implemented based on the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0013] like Figure 1 As shown, an embodiment of the present invention provides a timed hardware reset device for an unattended embedded system, including a power switch S1, and an output end of the power switch S1 is connected to a relay RLY1. Specifically, the relay RLY1 is a single-pole double-throw double-coil magnetic latching relay, which has two coils and single-pole double-throw switch contacts, the two coils are respectively a first coil C1 and a second coil C2, and the single-pole double-throw switch contacts include a common end (pin 1) of the contact, a first output end (pin 3) of the contact, and a second output end (pin 2) of the contact. The output end of the power switch S1 is connected to the common end of the contact of the relay RLY1, the first output end of the contact of the relay RLY1 is connected to one end of its first coil C1 and the setting control circuit respectively, the setting control circuit is connected to the other end of the first coil C1 of the relay RLY1, the second output end of the relay RLY1 is connected to one end of its second coil C2 and the power supply line respectively, the power supply line is used to supply power to the hardware of the embedded system, the other end of the second coil C2 of the relay RLY1 is connected to the reset control circuit, the reset control circuit is connected to the controller 1, the controller 1 preferably uses a single-chip microcomputer, such as a single-chip microcomputer of the MSP430F series. The controller 1 is connected to a clock chip 2, and the model of the clock chip 2 is preferably DS1302. It should be noted that the power supply required for the operation of the controller 1 and the clock chip 2 is provided separately.

[0014] The setting control circuit of the embodiment of the present invention includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a transistor T1, a transistor T2, and a capacitor E1. Among them, the resistor R2 and the resistor R1 are both connected to the first output end of the contact of the relay RLY1, the other end of the resistor R2 is respectively connected to one end of the resistor R4 and the positive end of the capacitor E1, the other end of the resistor R4 is respectively connected to one end of the resistor R5 and the resistor R6, the other end of the resistor R5 is connected to the base of the transistor T2, the transistor T2 is an NPN type, the negative end of the capacitor E1, the other end of the resistor R6 and the emitter of the transistor T2 are all grounded. The other end of the resistor R1 is respectively connected to the collector of the transistor T2 and one end of the resistor R3, the other end of the resistor R3 is connected to the base of the transistor T1, the transistor T1 is a PNP type, the emitter of the transistor T1 is connected to the other end of the first coil C1 of the relay RLY1, and the collector of the transistor T1 is grounded.

[0015] The reset control circuit of the embodiment of the present invention includes a resistor R7, a resistor R8, a resistor R9 and a transistor T3, etc., wherein one end of the resistor R8 is connected to the controller 1, the other end of the resistor R8 is connected to one end of the resistor R7 and the resistor R9 respectively, the other end of the resistor R7 is connected to the base of the transistor T3, the collector of the transistor T3 is connected to the other end of the second coil C2 of the relay RLY1, and the emitter of the transistor T3 and the other end of the resistor R9 are both grounded.

[0016] A diode D1 is further connected in anti-parallel to both ends of the first coil C1 of the relay RLY1 , ​​and a diode D2 is further connected in anti-parallel to both ends of the second coil C2 of the relay RLY1 .

[0017] Working principle: The present invention supports power-on reset and timed reset functions. During power-on reset, the power switch S1 is controlled to be disconnected and then closed. If the contact of the relay RLY1 is connected to the common terminal and the first output terminal at this time, the power supply voltage V1 charges the capacitor E1 through the resistor R2. When the voltage U E1 When the voltage between resistors R4 and R6 is greater than the base conduction voltage of NPN transistor T2 (generally in the range of 0.6-0.8V), T2 is turned on, so that the collector and the emitter are short-circuited due to the saturation effect, so U2 is short-circuited to "GND". At this time, transistor T1 is turned on, and a voltage difference with an amplitude of V1 is formed between the two ends of the first coil C1 (pin 1-2 and pin 1-1). Therefore, the first coil C1 generates a current flowing from pin 1-2 to pin 1-1, and an electromagnetic force is generated under the action of the current, so that the contact of relay RLY1 is connected to the second output terminal as the common end, so that the power supply voltage V1 is supplied to the hardware of the embedded system through the power supply line, and the voltage of the second output terminal of relay RLY1 becomes 0. The residual current on the first coil C1 is released through diode D1. If the power switch S1 is closed, the contact of the relay RLY1 is connected to the common end and the second output terminal, and power is directly supplied to the hardware of the embedded system.

[0018] The reset time can be set by the controller 1. It is recommended to select the 24-hour system at a time when the system tasks are relatively unbusy, such as 00:00:00 (zero o'clock, zero minutes and zero seconds), so that the timed reset can be performed once a day. During the working process, the time data of the patrol clock chip 2 is detected. When the timed reset time is detected, the controller 1 outputs a high-level pulse trigger signal to trigger the conduction of the transistor T3, so that the other end of the second coil C2 is grounded, and a voltage difference with an amplitude of V2 is formed between the two ends of the second coil C2 (pin 2-1 and pin 2-2). Therefore, the second coil C2 generates a current flowing from pin 2-1 to pin 2-2, and an electromagnetic force is generated under the action of the current, so that the contact of the relay RLY1 switches to the common end and connects to the first output terminal. The duration of the high-level pulse trigger signal output by the controller 1 can be set as needed. After the contact of the relay RLY1 switches, the high-level signal can be stopped. After the set reset time interval is reached, the contact of the relay RLY1 automatically switches to the common end and connects to the second output terminal, thereby realizing continued power supply after reset.

[0019] The above is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, other parts not specifically described belong to the prior art or common knowledge. Several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A timed hardware reset device for an unattended embedded system, characterized in that: It includes a power switch S1 and a relay RLY1, wherein the relay RLY1 is a single-pole double-throw double-coil magnetic latching relay, the output end of the power switch S1 is connected to the common end of the contact of the relay RLY1, the first output end of the contact of the relay RLY1 is respectively connected to one end of its first coil C1 and a setting control circuit, the setting control circuit is connected to the other end of the first coil C1 of the relay RLY1, the second output end of the relay RLY1 is respectively connected to one end of its second coil C2 and a power supply line, the other end of the second coil C2 of the relay RLY1 is connected to a reset control circuit, the reset control circuit is connected to a controller, and the controller is connected to a clock chip; The setting control circuit includes a resistor R2 and a resistor R1, one end of which is connected to the first output end of the contact of the relay RLY1, the other end of the resistor R2 is respectively connected to one end of the resistor R4 and the positive end of the capacitor E1, the other end of the resistor R4 is respectively connected to one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is connected to the base of the transistor T2, the transistor T2 is an NPN type, the negative end of the capacitor E1, the other end of the resistor R6 and the emitter of the transistor T2 are all grounded, the other end of the resistor R1 is respectively connected to the collector of the transistor T2 and one end of the resistor R3, the other end of the resistor R3 is connected to the base of the transistor T1, the transistor T1 is a PNP type, the emitter of which is connected to the other end of the first coil C1, and the collector of the transistor T1 is grounded; The reset control circuit includes a resistor R8 having one end connected to the controller, the other end of the resistor R8 being connected to one end of a resistor R7 and a resistor R9 respectively, the other end of the resistor R7 being connected to the base of the transistor T3, the collector of the transistor T3 being connected to the other end of the second coil C2, and the emitter thereof and the other end of the resistor R9 being grounded.

2. The timing hardware reset device for an unattended embedded system according to claim 1, characterized in that: The first coil C1 and the second coil C2 are connected in anti-parallel with a diode D1 and a diode D2 respectively.

3. The timing hardware reset device for an unattended embedded system according to claim 1, characterized in that: The controller is a single chip microcomputer.

4. The timing hardware reset device for an unattended embedded system according to claim 1, characterized in that: The model of the clock chip is DS1302.

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