Memory testing methods, testing devices, computer storage media and electronic devices

Abstract

This application discloses a memory detection method, detection device, computer storage medium, and electronic device. The method includes: writing first data to a memory cell connected to a first target word line; writing second data to a memory cell connected to a second target word line between the first target word line and the second target word line; performing a first voltage adjustment on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line; after completing the first voltage adjustment, turning the second target word line on and off a first preset number of times; performing a second voltage adjustment on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line; after completing the second voltage adjustment, turning the second target word line on and off a second preset number of times; and performing a read operation on the memory cell connected to the first target word line.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor device testing, and in particular to a memory testing method, testing device, computer storage medium, and electronic device. Background Technology

[0002] DRAM (Dynamic Random Access Memory), where DRAM Array is a dynamic random access memory array structure.

[0003] Currently, during the testing of DRAM arrays, the coverage of back-end testing is affected by the volatility of data retention time in the memory cells of the DRAM array, i.e., the continuous loss and reduction of charge in the memory cells of the DRAM array.

[0004] Therefore, how to solve the above problems has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a memory detection method, detection device, computer storage medium, and electronic device that can solve the above-mentioned problems.

[0006] A first aspect of this application provides a memory detection method, including:

[0007] Write the first data to the memory cell connected to the first target word line;

[0008] Write the second data into the storage unit between the first target word lines and the second target word line;

[0009] The storage cell connected to the first target word line is subjected to a first voltage adjustment to increase the voltage difference between the first target word line and the second target word line;

[0010] After the first voltage adjustment is completed, the second target word line is turned on and off a first preset number of times;

[0011] A second voltage adjustment is performed on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line;

[0012] After the second voltage adjustment is completed, the second target word line is turned on and off a second preset number of times;

[0013] A read operation is performed on the storage unit connected to the first target word line.

[0014] In some embodiments, after the first voltage adjustment of the memory cell connected to the first target word line, the method further includes:

[0015] The memory cells connected to the first target word line and the second target word line are refreshed.

[0016] In some embodiments, the value of the first data written to the first target word line is configured to be 0, and the value of the second data written to the second target word line is configured to be 1; wherein, before writing the first data to the storage unit connected to the first target word line, the method further includes:

[0017] The capacitance of the memory cell connected to the first target word line is increased from the default value to the first target capacitance value, wherein the voltage difference between the target capacitance value and the default value is 0 to 350 mV.

[0018] In some embodiments, after completing the second voltage adjustment and performing a second preset number of on / off cycles on the second target word line, the method further includes:

[0019] The capacitance of the memory cell connected to the first target word line is restored to the default value;

[0020] The memory cells connected to the first target word line and the second target word line are refreshed.

[0021] In some embodiments, it also includes;

[0022] When the first voltage adjustment is performed on the memory cell connected to the first target word line, the bit line reference voltage corresponding to the memory cell connected to the second target word line is adjusted to increase the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line.

[0023] In some embodiments, the value of the first data written to the first target word line is configured to be 0, and the value of the second data written to the second target word line is configured to be 1;

[0024] The first voltage regulation configuration is to reduce the voltage of the lower plate of the storage cell capacitor, and the second voltage regulation configuration is to reduce the voltage of the lower plate of the storage cell capacitor.

[0025] In some embodiments, adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line includes:

[0026] The bit line reference voltage corresponding to the memory cell connected to the second target word line is stepped down.

[0027] In some embodiments, the sum of the voltage drop value of the first voltage regulation and the voltage drop value of the second voltage regulation is less than or equal to 500mV;

[0028] The voltage drop value of the first voltage regulation is less than or equal to 150mV, and the voltage drop value of the second voltage regulation is less than or equal to 350mV.

[0029] In some embodiments, before the second target word line is turned on and off a first preset number of times, the method further includes:

[0030] Increase the capacitance of the memory cell connected to the first target word line to the second target capacitance value.

[0031] In some embodiments, the voltage difference between the second target capacitance value and the default value of the capacitance of the storage cell is 500 to 750 mV.

[0032] In some embodiments, the value of the first data written to the first target word line is configured to be 1, and the value of the second data written to the second target word line is configured to be 0;

[0033] The first voltage regulation configuration is to increase the voltage of the lower plate of the storage cell capacitor, and the second voltage regulation configuration is to increase the voltage of the lower plate of the storage cell capacitor.

[0034] In some embodiments, adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line includes:

[0035] The bit line reference voltage corresponding to the memory cell connected to the second target word line is boosted.

[0036] In some embodiments, the sum of the boost value of the first voltage regulation and the boost value of the second voltage regulation is less than or equal to 500mV;

[0037] The boost value of the first voltage regulation is less than or equal to 150mV, and the boost value of the second voltage regulation is less than or equal to 350mV.

[0038] A second aspect of this application provides a memory detection device, comprising:

[0039] The first write module is used to write first data to a storage unit connected to the first target word line;

[0040] The second writing module is used to write second data into the storage unit between the first target word lines and connected to the second target word line;

[0041] The first adjustment module is used to perform a first voltage adjustment on the memory cell connected to the first target word line, thereby increasing the voltage difference between the first target word line and the second target word line.

[0042] The first control module is used to turn the second target word line on and off a first preset number of times after the first adjustment module completes the first voltage adjustment.

[0043] The second adjustment module is used to perform a second voltage adjustment on the memory cell connected to the first target word line, thereby increasing the voltage difference between the first target word line and the second target word line.

[0044] The second control module is used to turn the second target word line on and off a second preset number of times after the second adjustment module completes the second voltage adjustment.

[0045] The read module is used to perform read operations on the storage unit connected to the first target word line.

[0046] In some embodiments, it also includes:

[0047] The first refresh module is used to refresh the storage unit connected to the first target word line and the second target word line.

[0048] In some embodiments, the first writing module configures the value of the first data written to the first target word line to be 0, and the second writing module configures the value of the second data written to the second target word line to be 1; wherein, the memory detection device further includes:

[0049] A recovery module is used to restore the capacitance of the memory cell connected to the first target word line to its default value;

[0050] The second refresh module is used to refresh the storage units connected to the first target word line and the second target word line.

[0051] In some embodiments, it also includes;

[0052] The third adjustment module is used to adjust the bit line reference voltage corresponding to the memory cell connected to the second target word line when the first adjustment module performs the first voltage adjustment on the memory cell connected to the first target word line. This adjustment module is used to increase the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line.

[0053] A third aspect of this application provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the detection method described above.

[0054] A fourth aspect of this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the detection method described above.

[0055] The above-mentioned technical solution of this application has at least the following beneficial technical effects:

[0056] In this embodiment, firstly, by performing a first voltage adjustment on the memory cell connected to the first target word line, the voltage difference between the memory cell connected to the first target word line and the memory cell connected to the second target word line is increased, so that memory cells with potential risks can be tested earlier; secondly, by turning the second target word line on and off a predetermined number of times, and performing a first and second voltage adjustment on the memory cell connected to the first target word line, side effects are reduced and the test results are made more accurate. Attached Figure Description

[0057] Figure 1 This is a flowchart of a memory detection method provided according to an embodiment of this application;

[0058] Figure 2 This is a schematic diagram of each step of the memory detection method provided according to an embodiment of this application;

[0059] Figure 3 This is a schematic diagram of the steps of a memory detection method provided according to another embodiment of this application. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0061] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0063] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0064] Currently, during the testing of DRAM arrays, the coverage of back-end testing is affected by the volatility of data retention time in the memory cells of the DRAM array, i.e., the continuous loss and reduction of charge in the memory cells of the DRAM array.

[0065] Therefore, how to solve the above problems has become a technical problem that urgently needs to be solved by those skilled in the art.

[0066] The memory includes multiple memory cells, multiple discrete bit lines, and multiple discrete word lines. Each bit line connects to several memory cells, and each word line connects to several memory cells. Each memory cell is connected to a corresponding bit line and a word line. The memory also has multiple complementary bit lines, each complementary bit line having an opposite voltage phase to the corresponding bit line. The memory also includes multiple sense amplifiers, each sense amplifier being electrically coupled to a bit line and a complementary bit line. The sense amplifier includes a power supply line providing a low-potential voltage and a power supply line providing a high-potential voltage.

[0067] Based on the above issues, refer to Figure 1 The first aspect of this application provides a memory detection method, including: S101, writing first data to a memory cell connected to a first target word line;

[0068] S103: Write second data into the storage unit between the first target word lines and connected to the second target word line;

[0069] S105. Perform a first voltage adjustment on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line.

[0070] S107. After completing the first voltage adjustment, turn the second target word line on and off for the first preset number of times.

[0071] S109. Perform a second voltage adjustment on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line;

[0072] S111. After completing the second voltage adjustment, turn the second target word line on and off a second preset number of times.

[0073] S113, Perform a read operation on the memory cell connected to the first target word line.

[0074] In this embodiment, firstly, by performing a first voltage adjustment on the memory cell connected to the first target word line, the voltage difference between the memory cell connected to the first target word line and the memory cell connected to the second target word line is increased, so that memory cells with potential risks can be tested earlier; secondly, by turning the second target word line on and off a preset number of times, and performing a first and second voltage adjustment on the memory cell connected to the first target word line, the risk of memory cells that originally met the requirements failing due to excessive voltage reduction or increase at one time is avoided, thereby reducing side effects on the memory cells and ensuring more accurate test results.

[0075] In some embodiments, after the first voltage adjustment of the memory cell connected to the first target word line, the method further includes:

[0076] The memory cells connected to the first target word line and the second target word line are refreshed.

[0077] In some embodiments, the value of the first data written to the memory cell connected to the first target word line is configured to be 0, and the value of the second data written to the memory cell connected to the second target word line is configured to be 1; wherein, before writing the first data to the memory cell connected to the first target word line, the method further includes:

[0078] The capacitance of the memory cell connected to the first target word line is increased from the default value to the first target capacitance value, and the voltage difference between the first target capacitance value and the default value is 0 to 350 mV.

[0079] In some embodiments, after completing the second voltage adjustment and performing a second preset number of on / off cycles on the second target word line, the method further includes:

[0080] Restore the capacitance of the memory cell connected to the first target word line to its default value;

[0081] The memory cells connected to the first target word line and the second target word line are refreshed.

[0082] In this embodiment, the capacitance of the memory cell connected to the first target word line is restored to its default value to increase the capacitance of the memory cell connected to the second target word line.

[0083] In some embodiments, the method further includes: when performing a first voltage adjustment on the memory cell connected to the first target word line, adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line to increase the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line.

[0084] In this embodiment, by adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line, the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line can be increased, enabling the memory cell connected to the second target word line to recharge faster during refresh, thus ensuring more accurate test results.

[0085] In some embodiments, the value of the first data written to the memory cell connected to the first target word line is configured to be 0, and the value of the second data written to the memory cell connected to the second target word line is configured to be 1;

[0086] The first voltage regulation configuration is to reduce the voltage of the lower plate of the storage cell capacitor, and the second voltage regulation configuration is to reduce the voltage of the lower plate of the storage cell capacitor.

[0087] In this embodiment of the application, for the memory cell that writes 0, by reducing its lower plate voltage (VPLT), the voltage difference between it and the memory cell that writes 1 is increased, which can accelerate the leakage current of the memory cell and increase the voltage of the memory cell that writes 0.

[0088] In some embodiments, adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line includes:

[0089] The bit line reference voltage corresponding to the memory cell connected to the second target word line is stepped down.

[0090] In some embodiments, the sum of the voltage drop values ​​of the first and second voltage regulation is less than or equal to 500 mV. Specifically, the voltage drop value of the first voltage regulation is less than or equal to 150 mV, and the voltage drop value of the second voltage regulation is less than or equal to 350 mV.

[0091] In some embodiments, before turning the second target word line on and off a first preset number of times, the method further includes:

[0092] Increase the capacitance of the memory cell connected to the first target word line to the second target capacitance value.

[0093] In some embodiments, the voltage difference between the second target capacitance value and the default capacitance value of the memory cell connected to the first target word line is 500 to 750 mV.

[0094] In some embodiments, the value of the first data written to the memory cell connected to the first target word line is configured as 1, and the value of the second data written to the memory cell connected to the second target word line is configured as 0;

[0095] The first voltage regulation configuration is to increase the voltage of the lower plate of the memory cell capacitor, and the second voltage regulation configuration is to increase the voltage of the lower plate of the memory cell capacitor.

[0096] In this embodiment of the application, for the write 1 memory cell, by increasing the lower plate voltage (VPLT), the voltage difference between it and the write 0 memory cell can be increased, which can accelerate the leakage current of the memory cell and reduce the voltage of the write 1 memory cell.

[0097] In some embodiments, adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line includes:

[0098] The bit line reference voltage corresponding to the memory cell connected to the second target word line is boosted.

[0099] In some embodiments, the sum of the boost values ​​of the first and second voltage regulation is less than or equal to 500 mV. Specifically, the boost value of the first voltage regulation is less than or equal to 150 mV, and the boost value of the second voltage regulation is less than or equal to 350 mV.

[0100] In one embodiment provided in this application, reference is made to Figure 2 The memory includes a plurality of word lines, among which are first target word lines and second target word lines. It is understood that in this embodiment, three second target word lines are arranged between two adjacent first target word lines. It should be noted that the detection method provided in this application embodiment includes, but is not limited to, the above-described arrangement, that is, a certain number of second target word lines can be arranged between two adjacent first target word lines as needed. Based on the word line arrangement determined above, the word lines to be tested can be numbered, with the numbering satisfying the condition X = X + 4. Based on this condition, the first target word lines are numbered using 0 / 4 / 8 / C… respectively, and the second target word lines are numbered using 1 / 5 / 9 / D…, 2 / 6 / A / E… or 3 / 7 / B / F… respectively.

[0101] One embodiment of the detection method includes:

[0102] S201. Write the first data to the storage unit connected to the first target word line;

[0103] In this embodiment, the first data is written to the memory cells connected by word lines numbered 0 / 4 / 8 / C… using the page write method, wherein the value of the first data is 0;

[0104] S203: Write the second data into the storage unit between the first target word lines and connected to the second target word line;

[0105] In this embodiment, the second data is written to the memory cells connected by word lines numbered 1 / 5 / 9 / D…, 2 / 6 / A / E…, 3 / 7 / B / F… using the page write method, wherein the value of the second data is 1.

[0106] S205. Perform a first voltage adjustment on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line; wherein, the voltage of the lower plate of the memory cell capacitor is reduced, and the voltage reduction adjustment value is 150mV (i.e., VPLT-150mV in the figure, where VPLT is the voltage of the lower plate of the memory cell capacitor connected to the first target word line).

[0107] In this embodiment, by adjusting the voltage of the lower plate of the capacitor of the memory cell connected to the first target word line, the voltage difference between the memory cell connected to the first target word line and the memory cell connected to the second target word line is increased, so that memory cells with potential risks can be tested earlier.

[0108] S207. After completing the first voltage adjustment, turn the second target word line on and off for the first preset number of times.

[0109] In this embodiment, the second target word line is turned on and off a preset number of times, that is, high / low level gate voltages are repeatedly applied, so that the interference between word lines can be made more prominent, and the memory cells with potential risks can be tested earlier.

[0110] S209. Perform a second voltage adjustment on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line; wherein, the lower plate of the capacitor of the memory cell connected to the first target word line is subjected to a voltage reduction treatment, and the voltage reduction adjustment value is 350mV (i.e., VPLT-350mV in the figure, where VPLT is the voltage of the lower plate of the capacitor of the memory cell connected to the first target word line).

[0111] In this embodiment, the voltage of the lower plate of the capacitor connected to the first target word line is further reduced to increase the voltage difference between the memory cell connected to the first target word line and the memory cell connected to the second target word line, allowing potentially risky memory cells to be detected earlier. In this embodiment, combined with the first voltage reduction process, the total voltage reduction is 500mV. Reducing the voltage by 500mV all at once might fail memory cells that were not initially faulty, introducing additional testing risks. Gradually reducing the voltage is more lenient and ensures more accurate test results.

[0112] S211. After completing the second voltage adjustment, turn the second target word line on and off a second preset number of times.

[0113] In this embodiment, the second target word line is turned on and off a preset number of times, that is, high / low level gate voltages are repeatedly applied, so that the interference between word lines can be made more prominent, and the memory cells with potential risks can be tested earlier.

[0114] S213, Perform a read operation on the memory cell connected to the first target word line.

[0115] The write value on the memory cell connected to the first target word line is read using the SA (sensing amplifier). It is then determined whether the 0 stored in the memory cell connected to the first target word line can be read correctly. If a 1 is read, it indicates that the memory cell connected to the first target word line has been interfered with and has failed.

[0116] In some embodiments, after performing the first voltage adjustment on the memory cell connected to the first target word line in step S205, the method further includes:

[0117] S206. Refresh the memory cells connected to the first target word line and the second target word line.

[0118] Among them, it can be refreshed at 8K. 8K is a preset method of refreshing N storage units at a time. That is, with a total of 8000N storage units, all storage units are refreshed in 8000 refreshes. The purpose of refreshing is to refresh all storage units once.

[0119] In some embodiments, after completing the second voltage adjustment in step S211 and performing a second preset number of on / off cycles on the second target word line, the method further includes:

[0120] S2111. Restore the capacitance of the memory cell connected to the first target word line to the default value (i.e., VARYDefault in the figure);

[0121] S2112, refresh the memory cell connected to the first target word line and the second target word line.

[0122] Similarly, it can be refreshed in 8K. 8K refreshes N storage units at a time according to a preset method. That is, with a total of 8000N storage units, all storage units are refreshed in 8000 refreshes. The purpose of the refresh is to refresh all storage units once.

[0123] In some embodiments, before restoring the capacitance of the memory cell connected to the first target word line to its default value in step S2111, the method further includes:

[0124] After completing the second voltage adjustment in step S211 and turning the second target word line on and off a second preset number of times, the process is maintained for a period of time to allow the memory cell to reach a stable state.

[0125] In some embodiments, the method further includes: when performing the first voltage adjustment on the memory cell connected to the first target word line in step S205, adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line to increase the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line. The absolute value of the voltage adjustment of the bit line reference voltage corresponding to the memory cell connected to the second target word line is less than the absolute value of the first voltage adjustment of the memory cell connected to the first target word line. In an optional embodiment, the bit line reference voltage corresponding to the memory cell connected to the second target word line is stepped down, with the adjustment value being 75mV (i.e., VBLT-75mV in the figure).

[0126] In this embodiment, while reducing the voltage of the lower plate of the capacitor connected to the first target word line, the bit line reference voltage of the second target word line is also adjusted. On the one hand, by reducing the bit line reference voltage of the second target word line, the charge of the corresponding memory cell that was written with a 1 can be flushed back more quickly during refresh. On the other hand, by adjusting the voltage of the lower plate of the capacitor connected to the first target word line, the voltage difference between the first and second target word lines can be increased, ensuring more accurate test results.

[0127] In some embodiments, before writing the first data to the memory cell connected to the first target word line in step 201, the method further includes:

[0128] The memory cell connected to the second target word line is subjected to voltage boosting, wherein the voltage boosting range is 0–500 mV. In a preferred embodiment, the voltage boosting range is 0–350 mV (VARY+(0–350 mV) in the figure).

[0129] In this embodiment, the solution involves writing a 0 to the memory cell connected to the first target word line and a 1 to the memory cell connected to the second target word line, then continuously turning the memory cell of the second target word line (where a 1 is written) on and off. The solution then tests whether the memory cell of the first target word line (where a 0 is written) will fail. In this step, the charge value of the memory cell of the second target word line (where a 1 is written) is pre-adjusted to be 0-500mV higher, so that the voltage of the memory cell of the second target word line is placed in the 1-1.5V range when a 1 is finally written. This mitigates charge loss caused by natural leakage in the memory cell of the second target word line (where a 1 is written), preventing any impact on detection.

[0130] In some embodiments, the charge value of the memory cell of the second target word line is pre-adjusted by 350mV to make the voltage of the memory cell of the second target word line 1.35V when writing 1.

[0131] refer to Figure 3 Another embodiment of this application provides a detection method including:

[0132] S301. Write the first data to the storage unit connected to the first target word line;

[0133] In this embodiment, the first data is written to the memory cells connected by word lines numbered 0 / 4 / 8 / C… using the page write method, wherein the value of the first data is 1;

[0134] S303. Write second data into the memory cell between the first target word lines and connected to the second target word line; wherein, the value of the second data is 0;

[0135] In this embodiment, the second target data is written to the memory cells connected by word lines numbered 1 / 5 / 9 / D…, 2 / 6 / A / E…, 3 / 7 / B / F… using the page write method, wherein the value of the second target data is 0.

[0136] S305. Perform a first voltage adjustment on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line; wherein, the voltage of the lower plate of the memory cell capacitor is boosted, and the boost adjustment value is 150mV (i.e., VPLT+150mV in the figure, where VPLT is the voltage of the lower plate of the memory cell capacitor connected to the first target word line).

[0137] In this embodiment, by increasing the voltage of the lower plate of the capacitor of the memory cell connected to the first target word line, the voltage difference between the memory cell connected to the first target word line and the memory cell connected to the second target word line is increased, so that memory cells with potential risks can be tested earlier.

[0138] S307. After completing the first voltage adjustment, turn the second target word line on and off for the first preset number of times.

[0139] In this embodiment, the second target word line is turned on and off a preset number of times, that is, high / low level gate voltages are repeatedly applied, so that the interference between word lines can be made more prominent, and the memory cells with potential risks can be tested earlier.

[0140] S309. Perform a second voltage adjustment on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line; wherein, the lower plate of the capacitor of the memory cell connected to the first target word line is subjected to a voltage boosting process, and the voltage boosting adjustment value is 350mV (i.e., VPLT+350mV in the figure, where VPLT is the voltage of the lower plate of the capacitor of the memory cell connected to the first target word line).

[0141] In this embodiment, the voltage of the lower plate of the capacitor in the memory cell connected to the first target word line is further increased to widen the voltage difference between the memory cell connected to the first target word line and the memory cell connected to the second target word line, allowing potentially risky memory cells to be detected earlier. In this embodiment, a total voltage increase of 500mV is applied in conjunction with the first voltage increase. A one-time 500mV increase might fail memory cells that were not initially faulty, introducing additional testing risks. A gradual voltage increase mitigates these risks and ensures more accurate test results.

[0142] S311. After completing the second voltage adjustment, turn the second target word line on and off a second preset number of times.

[0143] In this embodiment, the second target word line is turned on and off a preset number of times, that is, high / low level gate voltages are repeatedly applied, so that the interference between word lines can be made more prominent, and the memory cells with potential risks can be tested earlier.

[0144] S313, Perform a read operation on the memory cell connected to the first target word line.

[0145] The write value on the memory cell connected to the first target word line is read using the SA (sensing amplifier). It is then determined whether the 1 stored in the memory cell connected to the first target word line can be read correctly. If a 0 is read, it indicates that the memory cell connected to the first target word line has been interfered with and has failed.

[0146] In some embodiments, after performing the first voltage adjustment on the memory cell connected to the first target word line in step S305, the method further includes:

[0147] S306. Refresh the memory cell connected to the first target word line and the second target word line.

[0148] Among them, it can be refreshed at 8K. 8K is a preset method of refreshing N storage units at a time. That is, with a total of 8000N storage units, all storage units are refreshed in 8000 refreshes. The purpose of refreshing is to refresh all storage units once.

[0149] In some embodiments, after completing the second voltage adjustment in step S311 and performing a second preset number of on / off cycles on the second target word line, the method further includes:

[0150] S3111. Restore the capacitance of the memory cell connected to the first target word line to the default value (i.e., VARYDefault in the figure);

[0151] S3112, refresh the memory cell connected to the first target word line and the second target word line.

[0152] Similarly, it can be refreshed in 8K. 8K refreshes N storage units at a time according to a preset method. That is, with a total of 8000N storage units, all storage units are refreshed in 8000 refreshes. The purpose of the refresh is to refresh all storage units once.

[0153] In some embodiments, before restoring the capacitance of the memory cell connected to the first target word line to its default value in step S3111, the method further includes:

[0154] After completing the second voltage adjustment in step S311 and turning the second target word line on and off a second preset number of times, the process is maintained for a period of time to allow the memory cell to reach a stable state.

[0155] In some embodiments, the method further includes: when performing the first voltage adjustment on the memory cell connected to the first target word line in step S305, adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line to increase the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line. The absolute value of the voltage adjustment of the bit line reference voltage corresponding to the memory cell connected to the second target word line is less than the absolute value of the first voltage adjustment of the memory cell connected to the first target word line. In an optional embodiment, the bit line reference voltage corresponding to the memory cell connected to the second target word line is boosted, and the adjusted value is 75mV (i.e., VBLT+75mV in the figure).

[0156] In this embodiment, while increasing the voltage of the lower plate of the capacitor connected to the first target word line, the bit line reference voltage of the second target word line is also adjusted. On one hand, by increasing the bit line reference voltage of the second target word line, the charge of the memory cell corresponding to the write-0 memory cell can be flushed back more quickly during refresh. On the other hand, by adjusting the voltage of the lower plate of the capacitor connected to the first target word line, the voltage difference between the first and second target word lines can be increased, ensuring more accurate test results.

[0157] A second aspect of this application provides a memory detection device, characterized in that it includes:

[0158] The first write module is used to write first data to a storage unit connected to the first target word line;

[0159] The second writing module is used to write second data into the storage unit between the first target word lines and connected to the second target word lines;

[0160] The first adjustment module is used to perform the first voltage adjustment on the memory cell connected to the first target word line, thereby increasing the voltage difference between the first target word line and the second target word line.

[0161] The first control module is used to turn the second target word line on and off a first preset number of times after the first adjustment module completes the first voltage adjustment.

[0162] The second adjustment module is used to perform a second voltage adjustment on the memory cell connected to the first target word line, in order to increase the voltage difference between the first target word line and the second target word line.

[0163] The second control module is used to turn the second target word line on and off a second preset number of times after the second adjustment module completes the second voltage adjustment.

[0164] The read module is used to perform read operations on the storage unit connected to the first target word line.

[0165] In this embodiment, firstly, by performing a first voltage adjustment on the capacitor connected to the first target word line, the voltage difference between the memory cell connected to the first target word line and the memory cell connected to the second target word line is increased, so that memory cells with potential risks can be tested earlier; secondly, by continuously turning the second target word line on and off twice, and performing a first and second voltage adjustment on the capacitor connected to the first target word line, side effects are reduced and the test results are made more accurate.

[0166] In some embodiments, the memory detection device further includes a first refresh module. The first refresh module is used to refresh the memory cells connected to the first target word line and the second target word line.

[0167] In some embodiments, the first write module configures the value of the first data written to the memory cell connected to the first target word line to be 0, and the second write module configures the value of the second data written to the memory cell connected to the second target word line to be 1. The memory detection device further includes a recovery module and a second refresh module. The recovery module is used to restore the capacitance of the memory cell connected to the first target word line to a default value, and the second refresh module is used to refresh the memory cells connected to the first target word line and the second target word line.

[0168] In some embodiments, the memory detection device further includes a third adjustment module. The third adjustment module is used to adjust the bit line reference voltage corresponding to the memory cell connected to the second target word line when the first adjustment module performs the first voltage adjustment on the memory cell connected to the first target word line, thereby increasing the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line.

[0169] A third aspect of this application provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described detection method.

[0170] A fourth aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the detection method described above.

[0171] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of this application and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of this application should be included within the protection scope of this application. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

[0172] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes the flows of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0173] The steps in the method of this application embodiment can be adjusted, merged, or deleted according to actual needs. The modules in the system of this application embodiment can be merged, divided, or deleted according to actual needs.

Claims

1. A memory detection method, comprising: Write the first data to the memory cell connected to the first target word line; Write the second data into the storage unit between the first target word lines and the second target word line; The storage cell connected to the first target word line is subjected to a first voltage adjustment to increase the voltage difference between the first target word line and the second target word line; After the first voltage adjustment is completed, the second target word line is turned on and off a first preset number of times; A second voltage adjustment is performed on the memory cell connected to the first target word line to increase the voltage difference between the first target word line and the second target word line; After the second voltage adjustment is completed, the second target word line is turned on and off a second preset number of times; Perform a read operation on the memory cell connected to the first target word line; Specifically, a sensing amplifier is used to read the written value on the memory cell connected to the first target word line. If the written value is different from the first data, it indicates that the storage cell connected to the first target word line has failed. If the written value is the same as the first data, it indicates that the storage unit connected to the first target word line is normal.

2. The method according to claim 1, characterized in that, After performing the first voltage adjustment on the memory cell connected to the first target word line, the method further includes: The memory cells connected to the first target word line and the second target word line are refreshed.

3. The method according to claim 1, characterized in that, The value of the first data written to the storage unit connected to the first target word line is configured as 0, and the value of the second data written to the storage unit connected to the second target word line is configured as 1; wherein, before writing the first data to the storage unit connected to the first target word line, the method further includes: The capacitance of the memory cell connected to the first target word line is increased from the default value to the first target capacitance value, and the voltage difference between the first target capacitance value and the default value is 0 to 350 mV.

4. The method according to claim 3, characterized in that, After completing the second voltage adjustment, and after turning the second target word line on and off a second preset number of times, the method further includes: The capacitance of the memory cell connected to the first target word line is restored to the default value; The memory cells connected to the first target word line and the second target word line are refreshed.

5. The method according to claim 1, characterized in that, Also includes; When the first voltage adjustment is performed on the memory cell connected to the first target word line, the bit line reference voltage corresponding to the memory cell connected to the second target word line is adjusted to increase the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line.

6. The method according to claim 5, characterized in that, The value of the first data written to the storage unit connected to the first target word line is configured as 0, and the value of the second data written to the storage unit connected to the second target word line is configured as 1; The first voltage regulation configuration is to reduce the voltage of the lower plate of the storage cell capacitor, and the second voltage regulation configuration is to reduce the voltage of the lower plate of the storage cell capacitor.

7. The method according to claim 6, characterized in that, The step of adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line includes: The bit line reference voltage corresponding to the memory cell connected to the second target word line is stepped down.

8. The method according to claim 5, characterized in that, The sum of the voltage drop values ​​from the first and second voltage adjustments is less than or equal to 500mV; The voltage drop value of the first voltage regulation is less than or equal to 150mV, and the voltage drop value of the second voltage regulation is less than or equal to 350mV.

9. The method according to claim 5, characterized in that, Before the second target word line is turned on and off a first preset number of times, the method further includes: Increase the capacitance of the memory cell connected to the first target word line to the second target capacitance value.

10. The method according to claim 9, characterized in that, The voltage difference between the second target capacitance value and the default capacitance value of the memory cell connected to the first target word line is 500-750mV.

11. The method according to claim 5, characterized in that, The value of the first data written to the storage unit connected to the first target word line is configured as 1, and the value of the second data written to the storage unit connected to the second target word line is configured as 0; The first voltage regulation configuration is to increase the voltage of the lower plate of the storage cell capacitor, and the second voltage regulation configuration is to increase the voltage of the lower plate of the storage cell capacitor.

12. The method according to claim 11, characterized in that, The step of adjusting the bit line reference voltage corresponding to the memory cell connected to the second target word line includes: The bit line reference voltage corresponding to the memory cell connected to the second target word line is boosted.

13. The method according to claim 11, characterized in that, The sum of the boost values ​​from the first and second voltage adjustments is less than or equal to 500mV; The boost value of the first voltage regulation is less than or equal to 150mV, and the boost value of the second voltage regulation is less than or equal to 350mV.

14. A memory detection device, comprising: The first write module is used to write first data to a storage unit connected to the first target word line; The second writing module is used to write second data into the storage unit between the first target word lines and connected to the second target word line; The first adjustment module is used to perform a first voltage adjustment on the memory cell connected to the first target word line, thereby increasing the voltage difference between the first target word line and the second target word line. The first control module is used to turn the second target word line on and off a first preset number of times after the first adjustment module completes the first voltage adjustment. The second adjustment module is used to perform a second voltage adjustment on the memory cell connected to the first target word line, thereby increasing the voltage difference between the first target word line and the second target word line. The second control module is used to turn the second target word line on and off a second preset number of times after the second adjustment module completes the second voltage adjustment. The read module is used to perform read operations on the storage unit connected to the first target word line.

15. The memory detection device according to claim 14, characterized in that, Also includes: The first refresh module is used to refresh the storage unit connected to the first target word line and the second target word line.

16. The memory detection device according to claim 14, characterized in that, The first write module configures the value of the first data written to the memory cell connected to the first target word line as 0, and the second write module configures the value of the second data written to the memory cell connected to the second target word line as 1; wherein, the memory detection device further includes: A recovery module is used to restore the capacitance of the memory cell connected to the first target word line to its default value; The second refresh module is used to refresh the storage units connected to the first target word line and the second target word line.

17. The memory detection device according to claim 14, characterized in that, Also includes; The third adjustment module is used to adjust the bit line reference voltage corresponding to the memory cell connected to the second target word line when the first adjustment module performs the first voltage adjustment on the memory cell connected to the first target word line. This adjustment module is used to increase the voltage difference between the bit line reference voltage and the bit line output voltage of the memory cell connected to the second target word line.

18. A computer storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the detection method according to any one of claims 1-13.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the detection method according to any one of claims 1-13.

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