Device with through silicon via, guard ring and method of fabrication thereof

Abstract

The present disclosure relates to devices with through silicon via, guard ring and methods of making the same. A semiconductor article includes a semiconductor substrate, a back end of line (BEOL) wiring portion on the semiconductor substrate, a through silicon via, and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring, and an electrically insulating material. The through silicon via provides an electrically conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion, and in some embodiments, the through silicon via in the semiconductor substrate.

Description

Technical Field

[0001] This disclosure relates to the field of through-silicon vias and guard rings. Background Technology

[0002] The need to increase the computing power of electronic devices, including smartphones, tablets, desktop computers, laptops, and many other types of electronic devices, has always existed. Integrated circuits provide the computing power for these electronic devices. One way to increase the computing power of integrated circuits is to increase the number of transistors and other integrated circuit features that can be included in a given area of ​​a semiconductor substrate.

[0003] A semiconductor device or chip (hereinafter referred to as a "chip") can consist of a semiconductor substrate (where all front-end processing (FEOL) is typically performed to form semiconductor transistors, capacitors, etc.) and back-end processing (BEOL) wiring (where multiple wiring layers are formed to connect various transistors, capacitors, etc., in the semiconductor substrate). BEOL wiring may also have input / output (I / O) pads for connecting the chip to the next level of package, such as a printed circuit board or ceramic substrate. The semiconductor substrate is made of semiconductor material, while the BEOL wiring is made of metallic material for wiring and dielectric material for insulation.

[0004] Current semiconductor chips can have through-silicon vias (TSVs) that extend partially or completely through the semiconductor substrate and BEOL wiring. For example, such TSVs can be used to connect two chips (by stacking them one on top of the other). In some cases, the TSV extends entirely through the semiconductor substrate. A TSV can be characterized as the first TSV formed before the formation of a separate device, the intermediate TSV formed after the formation of a separate device but before the formation of the BEOL layer, or the last TSV formed after or during the formation of the BEOL layer. Summary of the Invention

[0005] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a semiconductor substrate (112) including a semiconductor material; a back-end process (BEOL) wiring portion (114) located on the semiconductor substrate, the BEOL wiring portion including a plurality of conductive layers (128) and an insulating material (110); a through-silicon via (TSV) (122) located in the semiconductor substrate and the BEOL wiring portion; and a guard ring (130) surrounding the TSV in the BEOL wiring portion, the guard ring including a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements including an upper portion (156) and a lower portion (158), the upper portion (156) of each of the plurality of guard ring elements including a spaced apart by a distance W.a A first surface (160) and a second surface (162), the first surface being closer to the through-silicon via than the second surface, and the lower portion (158) of each of the plurality of guard ring elements including a spaced distance W. b The first surface (164) and the second surface (166) of the lower part (158) are closer to the through-silicon via than the second surface of the lower part (158). a Unlike W b Furthermore, the first surface of one of the plurality of protective ring elements is coplanar with the first surface of another of the plurality of protective ring elements.

[0006] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: providing (40) a semiconductor substrate (112) comprising a semiconductor material (112); forming (42) a back-end process (BEOL) wiring portion (114), the back-end process wiring portion comprising a plurality of conductive layers (128), an insulating material (110), and a guard ring (130), the guard ring comprising a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements comprising an upper portion (156) and a lower portion (158), the upper portion (156) of each of the plurality of guard ring elements comprising a spaced apart by a distance W. a The first surface (160) and the second surface (162), the first surface being closer to the through-silicon via than the second surface, and the lower portion (158) of each of the plurality of guard ring elements including a spaced distance W b The first surface (164) and the second surface (166) of the lower part (158) are closer to the through-silicon via than the second surface of the lower part (158). a Unlike W b And the first surface of one of the plurality of guard ring elements is coplanar with the first surface of another of the plurality of guard ring elements; and the through-silicon via (TSV) (122) surrounded by the guard ring is formed (46) in the semiconductor substrate and the back-end process wiring portion.

[0007] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a semiconductor substrate (112) including a semiconductor material; a back-end process (BEOL) wiring portion (114) located on the semiconductor substrate, the BEOL wiring portion including a plurality of conductive layers (128) and an insulating material (110); and a through-silicon via (TSV) (122) located in the semiconductor substrate and the BEOL wiring portion, the TSV in the semiconductor substrate having a size D adjacent to the BEOL wiring portion. bAnd in the semiconductor substrate, the surface adjacent to the surface of the semiconductor substrate opposite to the surface adjacent to the back-end process wiring portion has a size D. c D b Greater than D c ; and a guard ring (130) surrounding the through-silicon vias in the back-end process wiring portion, the guard ring comprising a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements comprising an upper portion (156) and a lower portion (158), the upper portion (156) of each of the plurality of guard ring elements comprising a spaced apart by a distance W a The first surface (160) and the second surface (162), the first surface being closer to the through-silicon via than the second surface, and the lower portion (158) of each of the plurality of guard ring elements including a spacing distance W b The first surface (164) and the second surface (166) of the lower part (158) are closer to the through-silicon via than the second surface of the lower part (158). a Unlike W b . Attached Figure Description

[0008] Figure 1A and Figure 1B This is a cross-sectional view illustrating a method for forming through-silicon vias in a semiconductor chip.

[0009] Figures 2A to 2F This is a cross-sectional view illustrating a method for forming through-silicon vias and a top metal material according to some embodiments of the present disclosure.

[0010] Figure 2G This is a top view schematic diagram of through-silicon vias and guard rings according to some embodiments of the present disclosure.

[0011] Figure 3 Similar to some embodiments of this disclosure Figure 2D The cross-sectional view shows the two guard ring elements separated.

[0012] Figures 4A to 4E This disclosure illustrates various embodiments of the protection ring according to the embodiments described herein. Figure 3 Cross-sectional view in the direction of the middle arrow 3-3.

[0013] Figure 5 This is a flowchart illustrating a method according to an embodiment of the present disclosure.

[0014] Figures 6A to 6E This is a cross-sectional view illustrating a method according to an embodiment of the present disclosure.

[0015] Figure 7This is a cross-sectional view of a through-silicon via and a guard ring according to some embodiments of the present disclosure.

[0016] Figure 8 This is a cross-sectional view of a through-silicon via and a guard ring according to some embodiments of the present disclosure. Detailed Implementation

[0017] In the following description, the thicknesses and materials of various layers and structures within an integrated circuit die may be described. Specific dimensions and materials are given by way of example of various embodiments. Based on this disclosure, those skilled in the art will recognize that other dimensions and materials may be used in many cases without departing from the scope of this disclosure.

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the described subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] In addition, for ease of description, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0020] "Vertical direction" and "horizontal direction" should be understood as indicating relative directions. Therefore, the horizontal direction should be understood as substantially perpendicular to the vertical direction, and vice versa. However, within the scope of this disclosure, the described embodiments and aspects can be rotated as a whole such that the dimension referred to as the vertical direction is horizontally oriented, while the dimension referred to as the horizontal direction is vertically oriented.

[0021] In the following description, certain specific details are set forth to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will understand that the present disclosure can be practiced without these specific details. In other instances, well-known structures associated with electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of embodiments of the present disclosure.

[0022] Unless the context otherwise requires, throughout the specification and the appended claims, the word “comprising” and its variations, such as “including” and “containing”, shall be interpreted as open-ended and inclusive, meaning “including, but not limited to”.

[0023] The use of ordinal numbers such as first, second, and third does not necessarily imply a sequential order, but may simply distinguish multiple instances of an action or structure.

[0024] Throughout this specification, references to "an embodiment" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the appearance of the phrase "in one embodiment" or "in one embodiment" throughout this specification does not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0025] The singular forms “a,” “an,” and “the” used in this specification and the appended claims include the plural forms unless otherwise expressly provided. It should also be noted that the term “or” is generally used to include the meaning of “and / or” unless otherwise expressly provided.

[0026] According to a first aspect of the disclosed embodiments, various advantages and objectives of the embodiments of the present disclosure as described above and hereinafter are achieved by providing a semiconductor structure including a semiconductor substrate, wherein the semiconductor substrate comprises a semiconductor material. The semiconductor structure also includes back-end process (BEOL) wiring portions on the semiconductor substrate. The BEOL wiring portions include a plurality of wiring layers having conductive layers (e.g., metal layers) and an insulating material. Through-silicon vias are present in the BEOL wiring portions and the semiconductor substrate. The semiconductor structure includes a guard ring surrounding the through-silicon vias in the BEOL wiring portions, the guard ring including a plurality of guard ring elements, each of the plurality of guard ring elements including an upper portion and a lower portion. The upper portion of each of the plurality of guard ring elements includes a spaced distance W. a The first and second surfaces, with the first surface closer to the through-silicon via than the second surface. The lower portion of each of the plurality of guard ring elements includes a spacing of W. b The first surface and the second surface, with the lower first surface being closer to the through-silicon via than the lower second surface. According to some disclosed embodiments, Wa Unlike W b Furthermore, the first surface of one of the multiple guard ring elements is coplanar with the first surface of another of the multiple guard ring elements.

[0027] According to a second aspect of the embodiments disclosed herein, a method for forming a semiconductor structure is provided, the method comprising the step of providing a semiconductor substrate comprising a semiconductor material. The method further comprises the step of forming a back-end process (BEOL) wiring portion, the back-end process wiring portion comprising a plurality of conductive layers (e.g., metal layers), an insulating material, and a guard ring. The guard ring comprises a plurality of guard ring elements. Each of the plurality of guard ring elements includes an upper portion and a lower portion. The upper portion of each of the plurality of guard ring elements includes a spaced apart by a distance W. a The first and second surfaces, with the first surface closer to the through-silicon via than the second surface. The lower portion of each of the plurality of guard ring elements includes a spacing of W. b The first surface and the second surface, wherein the lower first surface is closer to the through-silicon via than the lower second surface. According to some embodiments, W a Unlike W b Furthermore, the first surface of one of the plurality of guard ring elements is coplanar with the first surface of another of the plurality of guard ring elements. The disclosed method also includes the step of forming a through-silicon via opening surrounded by guard rings in the BEOL wiring portion and the semiconductor substrate. According to some embodiments of this disclosure, the method includes metallizing the through-silicon via opening.

[0028] According to a third aspect of the embodiments described herein, a semiconductor device is provided including a semiconductor substrate comprising a semiconductor material. The semiconductor device includes a back-end process (BEOL) wiring portion on the semiconductor substrate, the BEOL wiring portion including a plurality of conductive layers (e.g., metal layers) and an insulating material. The semiconductor device also includes through-silicon vias (TSVs) in the semiconductor substrate and the BEOL wiring portion, the TSVs in the semiconductor substrate having a dimension D adjacent to the BEOL wiring portion. b Furthermore, the surface of the semiconductor substrate adjacent to the surface of the semiconductor substrate opposite to the surface of the adjacent back-end process wiring portion has a size D. c In some embodiments, D b Greater than D c The device also includes a guard ring surrounding the through-silicon vias in the back-end process wiring section. The guard ring comprises multiple guard ring elements. Each of the multiple guard ring elements includes an upper portion and a lower portion. The upper portion of each of the multiple guard ring elements includes a spaced distance W. a The first and second surfaces, with the first surface closer to the through-silicon via than the second surface. The lower portion of each of the plurality of guard ring elements includes a spacing of W.b The first surface and the second surface, wherein the lower first surface is closer to the through-silicon via than the lower second surface. In some embodiments, W a Unlike W b .

[0029] Please refer to the attached diagram for more details. Figure 1A and Figure 1B A method for forming through-silicon vias is shown. First, refer to... Figure 1A The semiconductor chip 10 includes a semiconductor substrate 12 and BEOL wiring 14. It should be understood that in... Figure 1A and Figure 1B Only a portion of the semiconductor chip 10 is shown. The semiconductor substrate 12 has undergone front-end processing (FEOL) to form various individual devices, such as transistors, capacitors, etc., within the semiconductor substrate 12. For clarity, these individual devices are not shown. The BEOL wiring 14 comprises multiple layers (not shown) of conductive material, such as metallic wiring within an insulating dielectric material. The precise details of the BEOL wiring 14 are well known to those skilled in the art and are not shown or described herein. Figure 1A The image also shows a through-silicon via opening 16 that has been etched through the BEOL wiring 14 and the semiconductor substrate 12.

[0030] refer to Figure 1B Then, insulating material 18 can be deposited on the walls of the through-silicon via opening 16. In one process for depositing insulating material 18, O3 / TEOS (tetraethyl orthosilicate) is used. A byproduct of forming insulating material 18 using O3 / TEOS (tetraethyl orthosilicate) is the generation of water that can migrate into the dielectric material of BEOL wiring 14, such as... Figure 1B As indicated by arrow 20 in the diagram. Water can be harmful to the insulating material of BEOL wiring 14 and may also be harmful to the materials forming the conductive features of the BEOL. For example, the conductive features of the BEOL include features with a barrier layer (e.g., TiN, TaN, etc.) and a conductive metal (e.g., copper or aluminum). When water generated during the formation of insulating material 18 migrates into the dielectric material of BEOL wiring 14, it can promote oxidation of the barrier layer of the BEOL wiring features. This oxidation weakens the barrier layer, allowing the conductive material of the BEOL wiring (e.g., copper or aluminum) to diffuse through the barrier layer and form metallic nodules in the insulating dielectric material of BEOL wiring 14. These metallic nodules eventually coalesce and form unwanted electrical paths between the BEOL wiring features within the insulating dielectric material. For example, when the BEOL wiring features are biased, such as during testing or normal operation, BEOL metal can migrate through the weakened barrier layer and form metallic nodules.

[0031] Continue to refer to Figure 1BThe through-silicon via opening 16 is metallized by depositing a metallic material, such as copper or aluminum, into the through-silicon via opening 16 using techniques such as electroplating. The through-silicon via opening 16 may also include a liner layer, such as TiN or Ta / TaN.

[0032] Now for reference Figures 2A to 2D The following illustrates embodiments of this disclosure. First, refer to... Figure 2A The semiconductor chip 110 includes a semiconductor substrate 112 and a BEOL wiring 114 located on one side of the semiconductor substrate 112. An additional wiring layer 111 exists on the opposite side of the semiconductor substrate 112 and includes a plurality of conductive features 111a, 111b, and 111c. For clarity, the semiconductor substrate 112 is not shown in cross-section, and therefore structures or devices within the semiconductor substrate 112 are not visible; however, such structures or devices exist within the semiconductor substrate 112 and are schematically represented by box 115. Such structures or devices include semiconductor structures such as transistors. It should be understood that in Figures 2A to 2D Only a portion of the semiconductor chip 110 is shown. Suitable materials for the semiconductor substrate 112 include, but are not limited to, group IV semiconductors (e.g., silicon, silicon germanium, or germanium), group III-V compound semiconductors, or group II-VI compound semiconductors. The metallic material of the BEOL wiring 114 is typically copper, but may also be other conductive materials such as aluminum. The dielectric insulating material of the BEOL wiring 114 can be any suitable material, such as silicon dioxide, silicon nitride, or SiCOH (a compound composed of silicon, carbon, oxygen, and hydrogen).

[0033] Semiconductor substrate 112 has undergone front-end processing (FEOL) to form various individual devices, such as transistors, capacitors, etc., within semiconductor substrate 112. For clarity, such individual devices are not shown. BEOL wiring 114 comprises multilayer (not shown) metal wiring within an insulating dielectric material. The precise details of BEOL wiring 114 are well known to those skilled in the art and do not require further description. Figure 2AThe diagram also shows a guard ring 130, which in some embodiments may be formed in the same order and at the same time as the formation of individual wiring layers of BEOL wiring 114 and interconnections or vias between different metal wiring layers. The guard ring may or may not be electrically connected to the metal material of BEOL wiring 114. When the guard ring 130 is formed in the same order and at the same time as the formation of individual wiring layers of BEOL wiring 114 and vias therebetween, the guard ring includes a plurality of segments or portions identified as 131a-131j. Each of these segments 131a-131j includes an upper, wider portion 131u formed during the same process of forming a layer of BEOL wiring and a lower, narrower portion 131n formed during the same process of forming vias between adjacent BEOL wiring layers. The formation of the guard ring 130 will be discussed in more detail below. In one embodiment of the embodiments described herein, the guard ring 130 is a ring or enclosure of conductive material, such as a metallic material surrounding the area where a through-silicon via will be formed. In the illustrated embodiment, the guard ring 130 extends at least the entire vertical length of the BEOL wiring 114.

[0034] Figure 2B The diagram shows a through-silicon via opening 116, which has been etched through BEOL wiring 114 using a dielectric or conductor etching technique (e.g., gas plasma etching). Figure 2C As shown, the through-silicon via opening 116 extends into a portion of the additional wiring layer 111, where it terminates at the conductive feature 111b. The etching process employed can be an isotropic dry etching process, such as the Bosch process. Due to the use of an isotropic etching process (as opposed to an anisotropic etching process), lateral and longitudinally extending grooves are formed. Typically, the Bosch process involves introducing a first gas that etches the substrate until the desired groove depth is reached, at which point the first gas is stopped and a second gas is introduced, which forms a protective liner along the surface of the sidewalls. When the first gas is reintroduced, it removes the protective liner along the bottom of the groove (leaving the protective liner along the sidewalls) and continues etching the substrate along the bottom of the groove. The process of introducing the first and second gases is repeated until the desired depth is reached.

[0035] For example, an etching gas (e.g., SF6) can be used as an etchant. The above process can be repeated any number of times to form an opening of the desired depth. After forming the opening of the desired depth, the opening can be filled with a conductive material to form... Figure 2E TSV122 in the middle. An insulating layer is formed along the sidewall of the opening ( Figure 2DThe insulating layer 118 is used to form a diffusion barrier to prevent conductive material (e.g., copper) from diffusing into the substrate 112 and / or one or more dielectric layers (e.g., the dielectric material of the additional wiring layer 111). The insulating layer 118 can be formed by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating deposition, or other suitable methods. After forming the insulating layer 118, a TSV 122 is formed using a conductive material. The conductive material can be, for example, copper, tungsten, aluminum, silver, or combinations thereof. In one embodiment, a seed layer (not shown) is formed over the insulating layer 118, and the opening is filled using an electrodeposition process, but other suitable methods, such as electrodeposition-free deposition, electroplating, or CVD, can also be used. The process may include using processes such as chemical mechanical polishing (CMP), etching, or combinations thereof to overfill the opening and remove excess conductive material located outside the TSV opening.

[0036] exist Figure 2C In the process, the through-silicon via opening 116 has been extended through the semiconductor substrate 112 using an etching process (e.g., plasma etching). Figure 2C The through-silicon via opening 116 is shown extending through the semiconductor substrate 112 and into the additional wiring layer 111. In other embodiments, the through-silicon via opening does not extend through the semiconductor substrate 112, but rather extends through a portion of the semiconductor substrate 112 to... Figure 2C Metallic features on opposite sides of this portion of the semiconductor substrate 112 shown. The location of the through-silicon via opening 116 has been chosen to be within the guard ring 130. Although the through-silicon via opening 116 is shown as being etched completely through the BEOL wiring 114 and the semiconductor substrate 112, the following is within the scope of this disclosure: the through-silicon via opening 116 is etched only partially through the BEOL wiring 114 and / or partially through the semiconductor substrate 112.

[0037] In some embodiments of this disclosure, such as in Figure 2C As can be best seen, the process of extending the through-silicon via opening 116 through the semiconductor substrate 112 does not remove a portion of the semiconductor substrate 112 near the interface between the semiconductor substrate 112 and the BEOL wiring 114. These remaining portions of the semiconductor substrate 112 are designated as protrusions 117. Without being bound by theory, protrusions 117 are likely a result of the remaining insulating dielectric material portion of the BEOL wiring 114 shielding a portion of the semiconductor substrate 112 from the etchant material used to etch the semiconductor substrate 112 to extend the through-silicon via opening 116 after the formation of the through-silicon via opening 116 in the BEOL wiring 114. This remaining portion... Figure 2BThe protrusion 117 is best shown in the diagram and is located at the bottom of the through-silicon via opening 116 formed in the dielectric insulating material of the BEOL wiring 114. According to some embodiments of this disclosure, a second etching step is performed to remove the protrusion 117 and create a flatter wall for the through-silicon via opening 116. In one embodiment, the protrusion 117 is removed using an etching process of the same type as that used to extend the through-silicon via opening 116 into the semiconductor substrate 112. In other embodiments, the protrusion 117 is removed using an etching process of a different type than that used to extend the through-silicon via opening 116 into the semiconductor substrate 112. Removal of the protrusion 117 is necessary to reduce stress concentration in the material of the semiconductor substrate 112.

[0038] refer to Figure 2D , Figure 2D The top of the through-silicon via opening 116 (adjacent to the top of the BEOL wiring 114) includes dimension D. a Size D a This represents the lateral distance between the left side wall 119a and the right side wall 119b of the through-silicon via opening 116. In some embodiments, D a The area is in the range of 1.5 to 3 micrometers. The bottom of the through-silicon via opening 116 (adjacent to the bottom of the semiconductor substrate 112) includes a dimension D. c Size D c This indicates the lateral distance between the left side wall 119a and the right side wall 119b of the through-silicon via opening 116. c Less than D a Near the interface between BEOL wiring 114 and semiconductor substrate 112, the through-silicon via opening 116 includes a dimension D. b Size D b This indicates the lateral distance between the left side wall 119a and the right side wall 119b of the through-silicon via opening 116. b Less than D a And greater than D c According to some embodiments of this disclosure, when D b Greater than D c This indicates satisfactory removal of protrusion 117. (D) b Less than D c ,like Figure 2C As shown, this indicates that satisfactory removal of protrusion 117 has not yet been achieved. As stated above, unsatisfactory removal of protrusion 117 is undesirable due to stress concentration when protrusion 117 is present.

[0039] After successful removal of the protrusion 117, as described above, an insulating material 118, such as an oxide or a low-k dielectric material, is formed on the wall of the through-silicon via opening 116. The insulating material serves to electrically isolate the conductive material from the silicon substrate. The specific insulating material used and its thickness affect the performance of the TSV, such as its capacitance and leakage current. In one process for depositing the insulating material 118, O3 / TEOS (tetraethyl orthosilicate) is used. In some embodiments, the insulating material 118 may have a thickness of about 1 micrometer. As described above, a byproduct of forming the insulating material 118 is the generation of water that can migrate into the dielectric material of the BEOL wiring 114. As described above, water can be detrimental to the insulating material of the BEOL wiring 114, and it can also be detrimental to the material forming the conductive features of the BEOL. For example, the conductive features of the BEOL include features having a barrier layer (e.g., TiN, TaN, etc.) and a conductive metal (e.g., copper or aluminum) at least partially surrounded by the barrier layer. As described above, when water generated during the formation of insulating material 118 migrates into the dielectric material of BEOL wiring 114, it can promote oxidation of the barrier layer of the BEOL wiring features. This oxidation weakens the barrier layer, allowing the conductive material of the BEOL wiring (e.g., copper or aluminum) to diffuse through the barrier layer and form metal nodules in the insulating dielectric material of the BEOL wiring 114. For example, when the BEOL wiring features are biased, such as during testing or normal operation, BEOL metal can migrate through the weakened barrier layer and form metal nodules. These metal nodules eventually converge and form unwanted electrical paths between the BEOL wiring features within the insulating dielectric material. According to embodiments of this disclosure, a guard ring 130 prevents water generated during the formation of insulating layer 118 from crossing the guard ring 130, where water could damage the barrier layer of the BEOL wiring features.

[0040] Next, the via opening 116 is metallized by depositing a metal material 122 (e.g., copper or aluminum) into it, thereby creating... Figure 2E The structure shown. The through-silicon via opening 116 may also include an insulating layer or a liner layer, for example... Figure 2E The material is not shown as TEOS, Ti, TiN, Ta, or TaN. The liner layer may have a thickness of approximately 10 nm to 100 nm. If the liner layer does not completely cover the walls of the through-silicon via opening 116, this may allow metal material 122 (especially if it is copper) to diffuse into the wiring layer of the BEOL wiring 114. However, the presence of the guard ring 130 prevents metal material 122 from entering the functional portion of the wiring layer of the BEOL wiring 114. In another embodiment of this disclosure, the liner layer can be omitted because any migration of metal material 122 to the functional portion of the BEOL wiring 114 will be prevented by the guard ring 130.

[0041] like Figure 2EThe metallized through-silicon via opening 116 shown can extend through all BEOL wiring 114 and semiconductor substrate 112, such as Figure 2E As shown. In other embodiments of this disclosure, the metallized through-silicon via opening 116 may extend only partially through the BEOL wiring 114 and / or the semiconductor substrate 112.

[0042] It should be noted that the metallized through-silicon via opening 116 can extend continuously through BEOL wiring 114 and semiconductor substrate 112. "Continuously" means that the metallized through-silicon via opening 116 extends through semiconductor chip 110 from or near the surface 128 of BEOL wiring 114 in a straight path (without any lateral bend) to or near the surface 132 of semiconductor substrate 112.

[0043] exist Figure 2F In this embodiment, a top metal layer 134 has been formed above some portions of the surface 128 of the BEOL wiring 114, the upper surface of the guard ring 130, and the upper surface of the metal material 122 in the through-silicon via opening 116. The formation of the top metal layer 134 includes the following steps: forming an insulating dielectric material above the surface 128 of the BEOL wiring 114, the upper surface of the guard ring 130, and the upper surface of the metal material 122 in the through-silicon via opening 116; patterning the thus formed insulating dielectric material; and forming additional metal material in the patterned insulating dielectric material above the guard ring 130 and the metal material 122 in the through-silicon via opening 116. Although Figure 2F As not shown, an insulating or passivation layer (e.g., a combination of oxide and nitride layers, such as a combination of oxide and TEOS, Ti, TiN, Ta, or TaN layers) separates the features of the top metal layer 134 from the dielectric material forming the BEOL wiring 114.

[0044] exist Figure 2F In the middle, the top metal layer 134 includes a portion 135, the width of which is W. T Basically equal to the diameter Dg of the protective ring 130 (in Figure 2G (Middle). Part 135 extends above the upper surface of the metal material 122 in the through-silicon via opening 116, and also extends above the upper surface of the dielectric material between the guard ring 130 and the metal material 122 in the through-silicon via opening 116. While part 135 electrically connects the metal material 122 to the guard ring 130, in some embodiments as described above, the guard ring 130 is an electrically passive structure. In other embodiments, for example... Figure 7 As shown, the top metal layer 134 has a portion 135, and the width of portion 135 is W. TBasically equal to the diameter D of the metal material 122 in the through-silicon via opening 116 a (exist Figure 2G (Middle). The top metal layer 134 also includes a portion 135a above the protective ring 130, which is separated from the portion 135 by a dielectric material. Using this structure, the protective ring 130 is electrically isolated from the metal material 122. (Reference) Figure 8 In another embodiment, the top metal layer 134 includes a portion 135, the width of which is W. T The diameter Dg is greater than 130 of the protective ring (in Figure 2G According to embodiments of this disclosure, Dg (see below for reference). Figure 2G The above) and W T The ratio ranges from approximately 1:0.5 to 1:2. In other embodiments, Dg and W... T The ratio ranges from approximately 1:0.75 to 1:1.5. When Dg and W... T When the ratio is below these ranges, the density of TSVs in the layer containing BEOL wiring will decrease because the relative size of portion 135 of metal layer 134 is larger. When Dg and W T When the ratio is higher than these ranges, the density of TSVs in layers containing BEOL wiring will decrease because the relative size of the guard ring is larger.

[0045] exist Figure 2G The image shows a top view of TSV 122 and guard ring 130. Figure 2G In this configuration, multiple metal lines 125 and multiple dummy metal structures 123 are present to provide a desired metal density in the BEOL. This desired metal density can protect non-metallic features from acid etching and can improve the flatness of different BEOL layers by acting as a stop for the planarization step. The TSV 122 is characterized by a diameter D as described below. a W a The following is for reference. Figure 3 The width of the wiring portion 156 of the described guard ring element 131a. TSV 122 is separated from guard ring 130 by an insulating material ring 127 between guard ring 130 and TSV 122. The width W of ring 127 is... r With W a The ratio ranges from approximately 1:1 to approximately 1:1.5. r The range is approximately 0.3 to 0.5 micrometers. When the width W of ring 127... r With W a When the ratio is less than 1:1.1, the possibility of current leakage from TSV 122 to protection ring 130 increases. When the width W of ring 127... r With W aWhen the ratio is greater than approximately 1:1.5, the density of BEOL wiring decreases because the proportion of dielectric material between TSV 122 and guard ring 130 is larger. Guard ring 130 is electrically isolated from dummy metal structure 123 and metal wire 125 by dielectric 129. a With W r The ratio ranges from approximately 3:1 to approximately 7:1. When D a With W r A ratio below approximately 3:1 may negatively impact TSV performance. a With W r When the ratio is higher than about 7:1, the possibility of current leakage from TSV 122 increases.

[0046] refer to Figure 3 A portion of the two elements 131a and 131b of the protective ring 130 is shown in a magnified view. Figure 3 In the embodiments described, guard ring element 131a and guard ring element 131b are identical. Therefore, only guard ring element 131a will be described below. The description of guard ring element 131a also applies to guard ring element 131b. Guard ring element 131a includes a first portion 150 and a second portion 152. Figure 3 In the illustrated embodiment, the first portion 150 is rectangular, and the second portion 152 is also rectangular. The first portion 150 is a rectangle smaller than the second portion 152. The dashed line 154 in the second portion 152 is an imaginary line separating the upper portion 156 and the lower portion 158 of the guard ring element 131a. According to some embodiments of this disclosure, the upper portion 156 is formed using the same semiconductor process used to form the metal wiring layer of the BEOL wiring 114. The lower portion 158 is formed using the same process used to form vias between the two layers of the BEOL wiring 114. The portion below the upper portion 156 may be referred to as the wiring portion of the guard ring element 131a, and the portion below the lower portion 158 may be referred to as the via portion of the guard ring element 131a. The upper portion 156 includes a wiring portion spaced apart by W. a The distances indicated are between the first surface 160 and the second surface 162. W a It is the width of the wiring portion 156 of the protective ring 131a. Figure 3 In the illustrated embodiment, the distance between the first surface 160 and the metal material 122 in the through-silicon via opening 116 is smaller than the distance between the second surface 162 and the metal material 122 in the through-silicon via opening 116. The lower portion 158 includes spaced apart by W... b The distances indicated are between the first surface 164 and the second surface 166. W b It is the width of the through-hole portion 158 of the protective ring 131a. Figure 3In the illustrated embodiment, the distance between the first surface 164 and the metal material 122 in the through-silicon via opening 116 is smaller than the distance between the second surface 166 and the metal material 122 in the through-silicon via opening 116. In other words, W a Unlike W b .exist Figure 3 In the illustrated embodiment, the distance between the second surface 162 and the metal material 122 in the through-silicon via opening 116 is greater than the distance between the second surface 166 and the metal material 122 in the through-silicon via opening 116. Figure 3 In the illustrated embodiment, the protective ring element 131a includes a dimension H parallel to the first surfaces 160 and 164. b .exist Figure 3 In the middle, dimension H b It extends between the upper surface 168 and the lower surface 170 of the protective ring element 131a. Figure 3 In the illustrated embodiment, some of the protective ring elements 131a-131j have a size H. b Different. For example, in Figure 3 In the middle, the H of the guard ring element 131j b H is greater than that of other guard ring elements (e.g., guard ring elements 131a-131h). b For example, the H of the guard ring element 131a b H can be different from the guard ring element 131b a Given Figure 3 The same properties of guard ring elements 131a and 131b, and the above description of features 150, 152, 154, 156, 158, 160, 162, 164, 166, 168, and 170 also apply to guard ring element 131b and guard ring elements 131c-131j. Given the same properties of guard ring elements 131a and 131b, the dimension W of guard ring element 131a... a W b and H b The description also applies to guard ring element 131b. In some embodiments, guard ring elements 131a-131j all have the same size. In other embodiments, guard ring elements 131a-131j all have different sizes. In other embodiments, some guard ring elements 131a-131j have the same size, while some guard ring elements 131a-131j have different sizes. For example, the W of guard ring element 131a... a The W may be different from one or more of the other guard ring elements 131b-132j. a The remaining guard ring elements have the same W. a For example, the W of the guard ring element 131a bThe W may be different from one or more of the other guard ring elements 131b-132j. b The remaining guard ring elements have the same W. b .Although Figure 3 The embodiments shown depict 10 guard ring elements, but in other embodiments of this disclosure, the BEOL wiring 114 includes more than 10 guard ring elements, and in other embodiments, the BEOL wiring 114 includes fewer than 10 guard ring elements.

[0047] According to some embodiments of this disclosure, W a With W b The ratio is between approximately 1.8 and 1.1. In other embodiments, W a With W b The ratio is between approximately 1.6 and 1.2. When W a With W b When the ratio falls above 1.8, the wiring portion 156 of the guard ring element 131 becomes too close to the adjacent wiring element of the BEOL wiring 140 and increases the possibility of forming unwanted electrical paths between the BEOL wiring feature and the wiring portion 156 or between adjacent BEOL wiring features. When W a With W b When the ratio falls below 1.1, the protective ring element 131 may not effectively protect the BEOL wiring from water that may form during TSV formation. In some embodiments, W a Within the range of 0.15 to 0.5 micrometers. In other embodiments, W a Within the range of 0.2 to 0.4 micrometers. In some embodiments, W b Within the range of 0.1 to 0.4 micrometers. In other embodiments, W b Within the range of 0.1 to 0.3 micrometers.

[0048] According to embodiments of this disclosure, the first surface 160 of the protective ring element 131a and the first surface 164 of the protective ring element 131b are coplanar. In other embodiments of this disclosure, the first surfaces 160 and 164 of the protective ring element 131a are coplanar with the first surfaces 160 and 164 of the protective ring element 131b. In other embodiments, one of the first surfaces 160 and / or 164 of one or more given protective rings is coplanar with one of the first surfaces 160 and / or 164 of one or more other protective rings. The protective ring elements of embodiments of this disclosure having coplanar first surfaces 160 and / or 164 are... Figure 2C and Figure 2DThe elements shown and described above are unlikely to be damaged during the etching steps. When the guard ring has non-coplanar inner surfaces, the likelihood increases that the etching forming the opening for the TSV also etches some of the first surface 160 and / or first surface 164 of the guard ring element.

[0049] The guard ring 130 can be formed into different shapes to suit the needs of semiconductor design. Figures 4A to 4E It is a semiconductor chip 110 edge Figure 3 The cross-section in the direction of arrow 3-3. Figures 4A-4E In the middle, the protective ring 131j has the aforementioned dimension W. a The top surface of the wiring section 156 is visible; however, the area with dimension W... b The via portion 158 is below the wiring portion 156 and is not visible. The TSV116 has the aforementioned dimension D. a The protective ring 130A has the aforementioned dimension Dg. First, refer to... Figure 4A It can be seen that the cross-section of the protective ring 130A is rectangular. Figure 4B In the middle, the cross-section of the protective ring 130A is square, while... Figure 4C In the middle, the cross-section of the protective ring 130A is circular. Figure 4D An embodiment of the protective ring 130A with an octagonal cross-section is shown. Figure 4E An embodiment is shown where the guard ring 130A has a hexagonal cross-section. The metallized through-silicon via opening 116 can be solid, such as... Figures 4A-4E As shown, and in other embodiments, the through-silicon via opening 116 may be hollow at the center. Figures 4A to 4E This is merely an example of the cross-section of the protective ring and is not intended to be limiting. Figure 4B , Figure 4C , Figure 4D and Figure 4E In the middle, the space between the TSV and the inner circumference or surface of the guard ring 130A is Figure 2G The size W in the middle r .

[0050] The dimensions of the guard ring 130A and the metallized through-silicon via opening 116 will vary depending on the design requirements of the semiconductor chip. In one embodiment, for illustrative and non-limiting purposes, the metallized through-silicon via opening 116 may have an outer diameter in the range of about 1 to 3 micrometers. In some embodiments, the guard ring 130A ( Figure 4BThe guard ring 130A may have an outer diameter in the range of about 2 to 4 micrometers. In some embodiments, the guard ring 130A has an inner diameter in the range of 1.5 to 3 micrometers. In some embodiments, the distance between the opposing surfaces 164 or 160 of the guard ring element 131C and the through-silicon via opening 116 is in the range of about 0.2 to 0.5 micrometers. When the guard ring element 131C is circular, this results in an opening diameter in the guard ring in the range of about 2.5 to 3.5 micrometers. In some embodiments, W a The ratio of the inner diameter to that of the guard ring element 131C is approximately 1 to 1.5. When W a When the ratio of the inner diameter to the guard ring element 131C is less than about 1, the guard ring element 131C may be ineffective in isolating the BEOL wiring from water that may form during TSV formation. When W a When the ratio of the inner diameter of the guard ring element 131C to that of the guard ring element 131C is greater than about 1.5, the wiring portion of the guard ring element 131C becomes too close to the adjacent wiring elements of the BEOL wiring 140 and increases the possibility of forming unwanted electrical paths between BEOL wiring features. In some embodiments, W b The ratio of the inner diameter to that of the guard ring element 131C is slightly greater than 1. When W b When the ratio of the inner diameter to the guard ring element 131C is less than 1, the guard ring element 131C may be ineffective in isolating BEOL wiring from water that may form during TSV formation.

[0051] Next, we will refer to Figure 5 and Figures 6A to 6E A method 500 is described for forming a semiconductor article having through-silicon vias and guard rings. In the first step of this method, a semiconductor substrate 112 is provided, such as... Figure 5 Box 40 and Figure 6A As shown. That is, preparing a semiconductor wafer with all the necessary semiconductor devices such as transistors and capacitors. It should be understood that... Figure 6A Only a portion of the semiconductor wafer is shown. Next, a first BEOL wiring layer 114A is formed, which includes a metal material 140 and a dielectric material 142, such as... Figure 5 Box 42 and Figure 6BAs shown. Note that BEOL wiring layer 114A includes a guard ring portion 144, which may or may not perform electrical functions within the BEOL wiring 114. The formation of BEOL wiring layer 114A includes the formation of via portions 140a and wiring portions 140b. When via portions 140a and wiring portions 140b are formed, via portions 144a and wiring portions 144b, or guard ring 144, are formed. These features, and the subsequent BEOL wiring layer and guard ring portion, are formed using known methods. Additional BEOL wiring layers are formed until a predetermined number of BEOL wiring layers are formed to meet the design requirements of the semiconductor chip, such as... Figure 5 Box 44 and Figure 6C As shown. Figure 6C As shown, this forms an additional BEOL routing layer 114C, but in practice, more such BEOL routing layers are usually formed, such as... Figures 6C-6E As shown by the dashed lines. It should be noted that the guard ring portion 144 of each BEOL wiring layer is stacked on top of the guard ring portion 144 of the previous BEOL wiring layer. The various guard ring portions 144 are formed in shapes such as squares, rectangles, circles, or other forms, as described above. Within the guard ring portion 144 is an open region 146, in which through-silicon via openings 116 will be formed. As... Figure 5 Box 46 and Figure 6D As shown, a through-silicon via (TSV) opening 116 is formed in the opening region 146 (and within the guard ring portion 144), and an insulating layer 118 is formed on the surface of the TSV opening 116. Finally, the TSV opening 116 is metallized using an optional liner layer 124 and a metal material 122, as shown. Figure 5 Box 48 and Figure 6E As shown. Then the semiconductor processing is performed in a conventional manner.

[0052] In one embodiment, this disclosure describes a semiconductor structure including a semiconductor substrate comprising a semiconductor material. The semiconductor structure also includes a back-end process (BEOL) wiring portion on the semiconductor substrate. The BEOL wiring portion includes multiple wiring layers having metal layers and an insulating material. Through-silicon vias are present in the BEOL wiring portion and the semiconductor substrate. The semiconductor structure includes a guard ring surrounding the through-silicon vias in the BEOL wiring portion, the guard ring including a plurality of guard ring elements, each of the plurality of guard ring elements including an upper portion and a lower portion. The upper portion of each of the plurality of guard ring elements includes a spaced distance W. a The first and second surfaces, with the first surface closer to the through-silicon via than the second surface. The lower portion of each of the plurality of guard ring elements includes a spacing of W. b The first surface and the second surface, with the lower first surface being closer to the through-silicon via than the lower second surface. According to some disclosed embodiments, Wa Unlike W b Furthermore, the first surface of one of the multiple guard ring elements is coplanar with the first surface of another of the multiple guard ring elements.

[0053] According to a second aspect of the embodiments disclosed herein, a method for forming a semiconductor structure is provided, the method comprising the step of providing a semiconductor substrate comprising a semiconductor material. The method further comprises the step of forming a back-end process (BEOL) wiring portion, the back-end process wiring portion comprising a plurality of metal layers, an insulating material, and a guard ring. The guard ring comprises a plurality of guard ring elements. Each of the plurality of guard ring elements includes an upper portion and a lower portion. The upper portion of each of the plurality of guard ring elements includes a spaced apart by a distance W. a The first and second surfaces, with the first surface closer to the through-silicon via than the second surface. The lower portion of each of the plurality of guard ring elements includes a spacing of W. b The first surface and the second surface, wherein the lower first surface is closer to the through-silicon via than the lower second surface. According to some embodiments, W a Unlike W b Furthermore, the first surface of one of the plurality of guard ring elements is coplanar with the first surface of another of the plurality of guard ring elements. The disclosed method also includes the step of forming a through-silicon via opening surrounded by guard rings in the BEOL wiring portion and the semiconductor substrate. According to some embodiments of this disclosure, the method includes metallizing the through-silicon via opening.

[0054] According to a third aspect of some embodiments described herein, a semiconductor device is provided including a semiconductor substrate comprising a semiconductor material. The semiconductor device includes a back-end process (BEOL) wiring portion on the semiconductor substrate, the BEOL wiring portion including a plurality of metal layers and an insulating material. The semiconductor device also includes through-silicon vias (TSVs) in the semiconductor substrate and the BEOL wiring portion, wherein the TSVs in the semiconductor substrate adjacent to the BEOL wiring portion have a size D. b Furthermore, the surface of the semiconductor substrate adjacent to the surface of the semiconductor substrate opposite to the surface of the adjacent back-end process wiring portion has a size D. c In some embodiments, D b Greater than D c The device also includes a guard ring surrounding the through-silicon vias in the back-end process wiring section. The guard ring comprises multiple guard ring elements. Each of the multiple guard ring elements includes an upper portion and a lower portion. The upper portion of each of the multiple guard ring elements includes a spaced distance W. a The first and second surfaces, with the first surface closer to the through-silicon via than the second surface. The lower portion of each of the plurality of guard ring elements includes a spacing of W. bThe first surface and the second surface, wherein the lower first surface is closer to the through-silicon via than the lower second surface. In some embodiments, W a Unlike W b

[0055] The various embodiments described above can be combined to provide further embodiments. If necessary, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide even more advanced embodiments.

[0056] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which such claims are conferred. Therefore, the claims are not limited to this disclosure.

[0057] Example 1. A semiconductor structure comprising: a semiconductor substrate (112) including a semiconductor material; a back-end process (BEOL) wiring portion (114) located on the semiconductor substrate, the BEOL wiring portion including a plurality of conductive layers (128) and an insulating material (110); a through-silicon via (TSV) (122) located in the semiconductor substrate and the BEOL wiring portion; and a guard ring (130) surrounding the TSV in the BEOL wiring portion, the guard ring including a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements including an upper portion (156) and a lower portion (158), the upper portion (156) of each of the plurality of guard ring elements including a spaced distance W. a A first surface (160) and a second surface (162), the first surface being closer to the through-silicon via than the second surface, and the lower portion (158) of each of the plurality of guard ring elements including a spaced distance W. b The first surface (164) and the second surface (166) of the lower part (158) are closer to the through-silicon via than the second surface of the lower part (158). a Unlike W b Furthermore, the first surface of one of the plurality of protective ring elements is coplanar with the first surface of another of the plurality of protective ring elements.

[0058] Example 2. A semiconductor structure as described in Example 1, wherein W a Greater than W b .

[0059] Example 3. A semiconductor structure as described in Example 1, wherein W a W bBetween 10% and 80%.

[0060] Example 4. A semiconductor structure as described in Example 1, wherein one or more of the plurality of guard ring elements are electrically connected to a conductive feature of the back-end process wiring portion.

[0061] Example 5. A semiconductor structure as described in Example 1, wherein the first guard ring element has a dimension H in a direction parallel to the first surface of the first guard ring element. a Furthermore, the second protective ring element has a dimension H in a direction parallel to the first surface of the second protective ring element. b H a Unlike H b .

[0062] Example 6. A semiconductor structure as described in Example 1, wherein the guard ring comprises a conductive material.

[0063] Example 7. A method of forming a semiconductor structure, comprising: providing (40) a semiconductor substrate (112) comprising a semiconductor material (112); forming (42) a back-end process (BEOL) wiring portion (114), the back-end process wiring portion comprising a plurality of conductive layers (128), an insulating material (110), and a guard ring (130), the guard ring comprising a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements comprising an upper portion (156) and a lower portion (158), the upper portion (156) of each of the plurality of guard ring elements comprising a spaced apart by a distance W. a The first surface (160) and the second surface (162), the first surface being closer to the through-silicon via than the second surface, and the lower portion (158) of each of the plurality of guard ring elements including a spaced distance W b The first surface (164) and the second surface (166) of the lower part (158) are closer to the through-silicon via than the second surface of the lower part (158). a Unlike W b And the first surface of one of the plurality of guard ring elements is coplanar with the first surface of another of the plurality of guard ring elements; and the through-silicon via (TSV) (122) surrounded by the guard ring is formed (46) in the semiconductor substrate and the back-end process wiring portion.

[0064] Example 8. The method as described in Example 7, wherein forming a through-silicon via comprises: removing insulating material from the back-end process wiring portion, performing a first removal step to remove a portion of the semiconductor material of the semiconductor substrate, and performing a second removal step to remove the remaining portion of the semiconductor material of the semiconductor substrate.

[0065] Example 9. The method of Example 8, wherein forming a through-silicon via further comprises: forming a conductive through-silicon via in the back-end process wiring portion and the semiconductor substrate.

[0066] Example 10. The method as described in Example 9, wherein the through-silicon via in the semiconductor substrate has a size D adjacent to the back-end process wiring portion. b And in the semiconductor substrate, the surface adjacent to the surface of the semiconductor substrate opposite to the surface adjacent to the back-end process wiring portion has a size D. c D b Greater than D c .

[0067] Example 11. The method as described in Example 7, wherein at least one of the plurality of conductive layers and at least a portion of the guard ring of the back-end process wiring portion are formed simultaneously.

[0068] Example 12. The method as described in Example 8, wherein the first guard ring element has a dimension H in a direction parallel to the first surface of the first guard ring element. a Furthermore, the second protective ring element has a dimension H in a direction parallel to the first surface of the second protective ring element. b H a Unlike H b .

[0069] Example 13. The method described in Example 7, where W a Greater than W b .

[0070] Example 14. A semiconductor device comprising: a semiconductor substrate (112) including a semiconductor material; a back-end process (BEOL) wiring portion (114) located on the semiconductor substrate, the BEOL wiring portion including a plurality of conductive layers (128) and an insulating material (110); and a through-silicon via (TSV) (122) located in the semiconductor substrate and the BEOL wiring portion, the TSV in the semiconductor substrate having a size D adjacent to the BEOL wiring portion. b And in the semiconductor substrate, the surface adjacent to the surface of the semiconductor substrate opposite to the surface adjacent to the back-end process wiring portion has a size D. c D b Greater than D c ; and a guard ring (130) surrounding the through-silicon vias in the back-end process wiring portion, the guard ring comprising a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements comprising an upper portion (156) and a lower portion (158), the upper portion (156) of each of the plurality of guard ring elements comprising a spaced apart by a distance Wa The first surface (160) and the second surface (162), the first surface being closer to the through-silicon via than the second surface, and the lower portion (158) of each of the plurality of guard ring elements including a spacing distance W b The first surface (164) and the second surface (166) of the lower part (158) are closer to the through-silicon via than the second surface of the lower part (158). a Unlike W b .

[0071] Example 15. The device as described in Example 14, wherein the first surface of one of the plurality of guard ring elements is coplanar with the first surface of another of the plurality of guard ring elements.

[0072] Example 16. The device as described in Example 14, wherein the protective ring comprises copper or aluminum.

[0073] Example 17. The device as described in Example 14, wherein W a Greater than W b .

[0074] Example 18. The device as described in Example 14, wherein one or more of the plurality of guard ring elements are electrically connected to a conductive feature of the back-end process wiring portion.

[0075] Example 19. The device as described in Example 14, wherein the first guard ring element has a dimension H in a direction parallel to a first surface of the first guard ring element. a Furthermore, the second protective ring element has a dimension H in a direction parallel to the first surface of the second protective ring element. b H a Unlike H b .

[0076] Example 20. The device as described in Example 14, wherein the first surfaces of three or more of the plurality of guard ring elements are coplanar with each other.

Claims

1. A semiconductor structure, comprising: Semiconductor substrate (112), comprising semiconductor material; Back-to-office (BEOL) wiring portion (114) is located on the semiconductor substrate, and the back-to-office wiring portion includes multiple conductive layers (128) and insulating material (110). A through-silicon via (TSV) (122) is located in the semiconductor substrate and the back-end process wiring portion; as well as A guard ring (130) includes an inner surface facing the through-silicon via and completely surrounding the through-silicon via in the back-end process wiring portion. The guard ring includes a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements including an upper portion (156) and a lower portion (158). The upper portion (156) of each of the plurality of guard ring elements includes a spacing of W. a The first surface (160) and the second surface (162) of the plurality of guard ring elements, wherein the upper first surface is closer to the through-silicon via than the upper second surface, and the lower portion (158) of each of the plurality of guard ring elements includes a spacing distance W. b The first surface (164) and the second surface (166), wherein the first surface of the lower portion (158) is closer to the through-silicon via than the second surface of the lower portion (158), W a Unlike W b Furthermore, the upper first surface and the lower first surface of one of the plurality of protective ring elements are coplanar with each other around the entire inner surface of the protective ring.

2. The semiconductor structure as claimed in claim 1, wherein W a Greater than W b .

3. The semiconductor structure as described in claim 1, wherein W a W b Between 10% and 80%.

4. The semiconductor structure of claim 1, wherein one or more of the plurality of guard ring elements are electrically connected to a conductive feature of the back-end process wiring portion.

5. The semiconductor structure of claim 1, wherein the first guard ring element has a dimension H in a direction parallel to the first surface of the upper portion of the first guard ring element. a Furthermore, the second protective ring element has a dimension H in a direction parallel to the first surface of the upper portion of the second protective ring element. b H a Unlike H b .

6. The semiconductor structure of claim 1, wherein the guard ring comprises a conductive material.

7. A method for forming a semiconductor structure, comprising: Provided (40) a semiconductor substrate (112) comprising semiconductor material; A back-end process (BEOL) wiring section (114) is formed, the back-end process wiring section including multiple conductive layers (128), insulating material (110) and guard ring (130), the guard ring including an inner surface facing the through-silicon via and completely surrounding the through-silicon via in the back-end process wiring section, the guard ring including multiple guard ring elements (131a / 131b), each of the multiple guard ring elements including an upper part (156) and a lower part (158), the upper part (156) of each of the multiple guard ring elements including a spaced distance W a The first surface (160) and the second surface (162) of the upper portion, wherein the upper first surface is closer to the through-silicon via than the upper second surface, and the lower portion (158) of each of the plurality of guard ring elements includes a spacing distance W. b The first surface (164) and the second surface (166), wherein the first surface of the lower portion (158) is closer to the through-silicon via than the second surface of the lower portion (158), W a Unlike W b Furthermore, the upper first surface and the lower first surface of one of the plurality of protective ring elements are coplanar with each other around the entire inner surface of the protective ring; as well as The through-silicon via (TSV) (122) surrounded by the guard ring is formed in the semiconductor substrate and the back-end process wiring portion.

8. The method of claim 7, wherein forming a through-silicon via comprises: The insulating material is removed from the back-end process wiring portion, a first removal step is performed to remove a portion of the semiconductor material of the semiconductor substrate, and a second removal step is performed to remove the remaining portion of the semiconductor material of the semiconductor substrate.

9. The method of claim 8, wherein forming the through-silicon via further comprises: Conductive through-silicon vias are formed in the back-end process wiring portion and the semiconductor substrate.

10. The method of claim 9, wherein the interface between the through-silicon via in the semiconductor substrate and the back-end wiring portion and the semiconductor substrate has a size D. b And the bottom of the semiconductor substrate has a size D c D b Greater than D c .

11. The method of claim 7, wherein at least one of the plurality of conductive layers and at least a portion of the protective ring of the back-end process wiring portion are formed simultaneously.

12. The method of claim 8, wherein the first guard ring element has a dimension H in a direction parallel to the first surface of the upper portion of the first guard ring element. a Furthermore, the second protective ring element has a dimension H in a direction parallel to the first surface of the upper portion of the second protective ring element. b H a Unlike H b .

13. The method of claim 7, wherein W a Greater than W b .

14. A semiconductor device, comprising: Semiconductor substrate (112), comprising semiconductor material; Back-to-office (BEOL) wiring portion (114) is located on the semiconductor substrate, and the back-to-office wiring portion includes multiple conductive layers (128) and insulating material (110). A through-silicon via (TSV) (122) is located in the semiconductor substrate and the back-end process wiring portion, wherein the TSV in the semiconductor substrate has a size D at the interface between the back-end process wiring portion and the semiconductor substrate. b And the bottom of the semiconductor substrate has a size D c D b Greater than D c ; as well as A guard ring (130) includes an inner surface facing the through-silicon via and completely surrounding the through-silicon via in the back-end process wiring portion. The guard ring includes a plurality of guard ring elements (131a / 131b), each of the plurality of guard ring elements including an upper portion (156) and a lower portion (158). The upper portion (156) of each of the plurality of guard ring elements includes a spacing of W. a The first surface (160) and the second surface (162) of the upper portion, wherein the upper first surface is closer to the through-silicon via than the upper second surface, and the lower portion (158) of each of the plurality of guard ring elements includes a spacing distance W. b The first surface (164) and the second surface (166), wherein the first surface of the lower portion (158) is closer to the through-silicon via than the second surface of the lower portion (158), W a Unlike W b Furthermore, the upper first surface and the lower first surface of one of the plurality of protective ring elements are coplanar with each other around the entire inner surface of the protective ring.

15. The device of claim 14, wherein the upper first surface and the lower first surface of one of the plurality of guard ring elements are coplanar with the upper first surface and the lower first surface of another of the plurality of guard ring elements around the entire inner surface of the guard ring.

16. The device of claim 14, wherein the protective ring comprises copper or aluminum.

17. The device of claim 14, wherein W a Greater than W b .

18. The device of claim 14, wherein one or more of the plurality of guard ring elements are electrically connected to a conductive feature of the back-end process wiring portion.

19. The device of claim 14, wherein the first guard ring element has a dimension H in a direction parallel to the first surface of the upper portion of the first guard ring element. a Furthermore, the second protective ring element has a dimension H in a direction parallel to the first surface of the upper portion of the second protective ring element. b H a Unlike H b .

20. The device of claim 14, wherein the first surfaces of the upper portions of three or more of the plurality of guard ring elements are coplanar with each other.

Images