Planar power semiconductor devices

Abstract

The present invention discloses a planar power semiconductor device, wherein the device unit comprises: a first epitaxial layer formed on a substrate; a gate structure formed on the surface of the first epitaxial layer; a source region self-aligned with a first side of the gate structure; a drain region spaced apart from a second side of the gate structure; a drift region located between the second side of the gate structure and the drain region; a conductive channel formed by an inversion layer formed when the surface of the first epitaxial layer covered by the gate structure is inverted; and a doping concentration distribution in the drift region forming a charge-balanced structure. Under reverse bias, the charge-balanced structure completely depletes the drift region and uniformly distributes the surface electric field. The present invention can achieve a charge-balanced structure in the drift region, thereby reducing the specific on-resistance and significantly reducing the energy loss of the device when it is turned on. The present invention is particularly suitable for gallium nitride power devices, fully utilizing the advantages of gallium nitride materials, reducing the cost of gallium nitride device manufacturing, and simplifying the process flow.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a planar power semiconductor device. Background Art

[0002] The specific on-resistance (Ron,sp) of existing power devices is linked to their breakdown voltage (BV). A higher breakdown voltage often results in a higher specific on-resistance. Traditional power semiconductor devices face a physical limit in the ratio of Ron,sp to BV, also known as the one-dimensional physical limit (1-D limit). The invention of charge-balanced power devices could overcome this limit. The most typical charge-balanced device structure is the superjunction device. Traditional superjunction devices use different doping levels (N-type and P-type) in the drift region to create a charge-balanced structure. This superjunction process is relatively mature in silicon devices, but it is not applicable to wide-bandgap semiconductors. In particular, in GaN, due to the unique process constraints, the charge-balance design concept needs to be specifically modified to effectively apply it in GaN devices.

[0003] As a typical wide-bandgap semiconductor material, gallium nitride (GaN) is often used in various research projects for the manufacture of power semiconductor devices. GaN offers significant advantages, particularly in high-temperature and high-pressure applications, due to its large bandgap (3.4 eV), high breakdown electric field (3 MV / cm), high electron mobility, and high thermal conductivity. To date, the mainstream GaN device research has focused on planar high-electron-mobility transistors (HEMTs), and the mainstream products on the market also use this device structure. HEMTs primarily utilize a two-dimensional electron gas (2DEG) formed by a heterojunction of GaN and AlGaN as the conductive channel.

[0004] In addition, due to the favorable interface conditions between GaN and SiO2, high-performance devices can also be fabricated by fabricating insulated gate field-effect transistors (IGFETs) on GaN materials. Insulated gate field-effect transistors (IGFETs) fabricated on GaN materials are typically GaN MOSFETs, where the conductive channel is formed by an inversion layer formed by the gate structure inverting the GaN surface. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a planar power semiconductor device that can realize a charge-balanced structure in the drift region, thereby reducing the specific on-resistance and significantly reducing the energy loss of the device when it is turned on. The present invention is particularly suitable for gallium nitride power devices, can give full play to the advantages of gallium nitride materials, reduce the cost of gallium nitride device manufacturing, and simplify the process flow.

[0006] In order to solve the above technical problems, the device unit of the planar power semiconductor device provided by the present invention includes:

[0007] A first epitaxial layer is formed on the substrate.

[0008] A gate structure is formed on the surface of the first epitaxial layer, and includes a gate dielectric layer formed on the surface of the first epitaxial layer and a gate conductive material layer formed on the surface of the gate dielectric layer.

[0009] The source region heavily doped with the first conductivity type is self-aligned with the first side surface of the gate structure.

[0010] A gap exists between the drain region heavily doped with the first conductive type and the second side surface of the gate structure.

[0011] The drift region doped with the first conductivity type is located between the second side surface of the gate structure and the drain region.

[0012] The conductive channel is composed of an inversion layer formed when the surface of the first epitaxial layer covered by the gate structure is inverted.

[0013] The doping concentration distribution of the drift region forms a charge balance structure. When reverse biased, the charge balance structure causes the drift region to be completely depleted and the surface electric field to be uniformly distributed.

[0014] A further improvement is that the planar power semiconductor device is a gallium nitride planar field effect transistor;

[0015] The substrate is an insulating substrate;

[0016] The first epitaxial layer is a gallium nitride epitaxial layer;

[0017] The first epitaxial layer is doped with the second conductivity type or is undoped.

[0018] A further improvement is that the drift region is composed of an ion implantation region formed in the first epitaxial layer after annealing.

[0019] A further improvement is that the junction depth of the drift region is less than or equal to the junction depth of the drain region.

[0020] A further improvement is that the drift region is uniformly doped, and the total doping dose of the drift region is controlled so that the drift region forms a charge-balanced structure.

[0021] A further improvement is that, while keeping the total doping dose of the drift region unchanged, the drift region is divided into multiple drift sub-regions in the laterally direction, the doping concentration of each drift sub-region is different, and the surface electric field of the drift region is regulated by setting the doping concentration of each drift sub-region and is regulated to make the surface electric field of the drift region uniformly distributed.

[0022] The widths of the drift sub-regions are equal or unequal.

[0023] A further improvement is that when the planar power semiconductor device is a gallium nitride planar field effect transistor, the total doping dose of the drift region is 2e13 cm -2 .

[0024] A further improvement is that the depths of the drift sub-regions are the same, and the doping concentration of the drift sub-regions is adjusted by the ion implantation dose corresponding to the drift sub-regions.

[0025] A further improvement is that, in the direction from the second side of the gate structure to the drain region, the doping concentration of each drift sub-region increases successively or decreases successively or first increases successively and then decreases successively after increasing to a maximum value or first decreases successively and then increases successively after decreasing to a minimum value.

[0026] A further improvement is that the depths of the drift sub-regions are different, the ion implantation doses corresponding to the drift sub-regions are equal, and the doping concentrations of the drift sub-regions are adjusted by the ion implantation energies corresponding to the drift sub-regions. The greater the ion implantation energy, the deeper the depth of the drift sub-region and the lower the doping concentration.

[0027] A further improvement is that, in the direction from the second side of the gate structure to the drain region, the doping concentration of each drift sub-region increases successively or decreases successively or first increases successively and then decreases successively after increasing to a maximum value or first decreases successively and then increases successively after decreasing to a minimum value.

[0028] A further improvement is that the drift region is composed of a second epitaxial layer formed on the surface of the first epitaxial layer and subjected to local etching.

[0029] A further improvement is that the junction depth of the drift region is less than or equal to the junction depth of the drain region.

[0030] In a longitudinal direction, the drain region extends from a top surface of the second epitaxial layer into the first epitaxial layer.

[0031] A further improvement is that the drift region is uniformly doped, and the total doping dose of the drift region is controlled so that the drift region forms a charge-balanced structure.

[0032] A further improvement is that, under the condition that the total doping dose of the drift region remains unchanged, the second epitaxial layer of the drift region is divided into a plurality of second epitaxial sub-layers in the longitudinal direction.

[0033] The second side surfaces of the second epitaxial sub-layers are flush and aligned with the first side surfaces of the drain region.

[0034] In a longitudinal direction from bottom to top, a distance between the first side surface of each second epitaxial sub-layer and the first side surface of the gate structure increases.

[0035] A further improvement is that when the planar power semiconductor device is a gallium nitride planar field effect transistor, the total doping dose of the drift region is 2e13 cm -2 .

[0036] A further improvement is that the doping concentrations of the second epitaxial sub-layers are equal or unequal.

[0037] A further improvement is that when the doping concentrations of each second epitaxial sublayer are not equal, in the longitudinal direction from bottom to top, the doping concentrations of each second epitaxial sublayer increase or decrease successively, or first increase successively and then decrease successively after increasing to a maximum value, or first decrease successively and then increase successively after decreasing to a minimum value.

[0038] A further improvement is that the thicknesses of the second epitaxial sub-layers are equal or unequal.

[0039] A further improvement is that when the thicknesses of each second epitaxial sublayer are not equal, in the longitudinal direction from bottom to top, the thicknesses of each second epitaxial sublayer increase or decrease successively, or first increase successively and then decrease successively after increasing to the maximum value, or first decrease successively and then increase successively after decreasing to the minimum value.

[0040] A further improvement is that the material of the gate dielectric layer includes silicon oxide or aluminum oxide.

[0041] The present invention can realize a charge balance structure in the drift region, thereby reducing the specific on-resistance and greatly reducing the energy loss of the device when it is turned on.

[0042] The present invention is particularly suitable for gallium nitride power devices. In a gallium nitride planar field-effect transistor, a charge-balanced structure can be achieved by adjusting the doping distribution of the drift region. For example, under the condition that the total doping dose of the drift region is controlled, the drift region can be uniformly doped or segmentedly doped. Finally, the surface electric field strength of the drift region can be well adjusted to achieve a charge-balanced effect in the drift region. Compared with existing gallium nitride planar field-effect transistors, the gallium nitride planar field-effect transistor of the present invention can improve the on-resistance by several orders of magnitude compared to existing power devices at the same breakdown voltage, significantly reducing the power loss of power semiconductor devices and thus saving energy and reducing emissions. At the same time, the advantages of gallium nitride devices are fully utilized, the process flow is simplified, and the manufacturing cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0044] Figure 1 is a schematic structural diagram of a planar power semiconductor device according to a first embodiment of the present invention;

[0045] Figure 2 is a schematic structural diagram of a planar power semiconductor device according to a second embodiment of the present invention;

[0046] Figure 2A yes Figure 2 The structural diagram of the corresponding drift sub-area when the number of segments is 2;

[0047] Figure 2B yes Figure 2 The structural diagram of the corresponding drift sub-area when the number of segments is 3;

[0048] Figure 3 is a schematic structural diagram of a planar power semiconductor device according to a third embodiment of the present invention;

[0049] Figure 3A yes Figure 3 The structural diagram of the corresponding drift sub-area when the number of segments is 2;

[0050] Figure 3B yes Figure 3 The structural diagram of the corresponding drift sub-area when the number of segments is 3;

[0051] Figure 4 is a schematic structural diagram of a planar power semiconductor device according to a fourth embodiment of the present invention;

[0052] Figure 4A yes Figure 4 The structural diagram of the corresponding drift sub-area when the number of segments is 3;

[0053] Figure 5 is a schematic structural diagram of a planar power semiconductor device according to a fifth embodiment of the present invention;

[0054] Figure 6 is a schematic structural diagram of a planar power semiconductor device according to a sixth embodiment of the present invention;

[0055] Figure 7 is a schematic structural diagram of a planar power semiconductor device according to a seventh embodiment of the present invention;

[0056] Figure 8 is a schematic structural diagram of a planar power semiconductor device according to an eighth embodiment of the present invention;

[0057] Figure 8A yes Figure 8 A schematic structural diagram of the corresponding second epitaxial sub-layer when the number of layers is 2;

[0058] Figure 8B yes Figure 8 Schematic diagram of the structure when the number of layers of the corresponding second epitaxial sub-layer is 3. DETAILED DESCRIPTION

[0059] A planar power semiconductor device according to a first embodiment of the present invention:

[0060] like Figure 1 FIG. 1 is a schematic structural diagram of a planar power semiconductor device according to a first embodiment of the present invention. The device unit of the planar power semiconductor device according to the embodiment of the present invention includes:

[0061] A first epitaxial layer 2 is formed on a substrate 1 .

[0062] The gate structure is formed on the surface of the first epitaxial layer 2. The gate structure includes a gate dielectric layer 5 formed on the surface of the first epitaxial layer 2 and a gate conductive material layer 6 formed on the surface of the gate dielectric layer 5.

[0063] The heavily doped source region 3 of the first conductivity type is self-aligned with the first side surface of the gate structure.

[0064] There is a gap between the drain region 4 heavily doped with the first conductivity type and the second side surface of the gate structure.

[0065] The drift region 101 doped with the first conductivity type is located between the second side surface of the gate structure and the drain region 4 .

[0066] The conductive channel is composed of an inversion layer formed when the surface of the first epitaxial layer 2 covered by the gate structure is inverted.

[0067] The doping concentration distribution of the drift region 101 forms a charge balance structure. When reverse biased, the charge balance structure causes the drift region 101 to be completely depleted and the surface electric field to be uniformly distributed.

[0068] In a first embodiment of the present invention, the planar power semiconductor device is a gallium nitride planar field-effect transistor.

[0069] The substrate 1 is an insulating substrate 1 .

[0070] The first epitaxial layer 2 is a gallium nitride epitaxial layer.

[0071] The first epitaxial layer 2 is doped with the second conductivity type or is undoped.

[0072] The drift region 101 is composed of an ion implantation region formed in the first epitaxial layer 2 after annealing.

[0073] The drift region 101 is uniformly doped, and the total doping dose of the drift region 101 is controlled to form a charge-balanced structure. In order to optimize the effect of the charge-balanced device, the doping dose of the drift region 101 needs to be precisely controlled. The appropriate doping dose is determined by the breakdown electric field and dielectric constant of the GaN epitaxial layer. Preferably, the total doping dose of the drift region 101 is 2e13cm -2 The present invention can also be extended to planar field-effect transistors using other wide-bandgap materials. In this case, the total doping dose of the corresponding drift region needs to be set according to the breakdown electric field and dielectric constant of the wide-bandgap material.

[0074] In addition, the length of the drift region 101 determines the breakdown voltage of the device and is designed according to needs.

[0075] The junction depth of the drift region 101 is less than or equal to the junction depth of the drain region 4 , that is, the junction depth of the drift region 101 is more appropriately selected to be shallower than the junction depth of the drain region 4 .

[0076] In the first embodiment of the present invention, the gate dielectric layer 5 of the gate structure includes silicon oxide or aluminum oxide. Both silicon oxide and aluminum oxide form a good interface with gallium nitride, thereby facilitating the formation of a conductive channel. The thickness of the gate dielectric layer 5 determines the threshold voltage of the device and needs to be set according to the threshold voltage requirements.

[0077] The gate conductive material layer 6 is made of polysilicon or other metal materials.

[0078] The top of the source region 3 is connected to a source electrode formed of a metal layer, the top of the drain region 4 is connected to a drain electrode formed of a metal layer, and the top of the gate conductive material layer 6 is also connected to a gate electrode formed of a metal layer.

[0079] The source electrode, the gate electrode, and the drain electrode are isolated from each other by an interlayer film.

[0080] In the first embodiment of the present invention, the planar power semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the planar power semiconductor device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0081] The first embodiment of the present invention achieves a charge-balanced structure in the drift region 101 by precisely controlling the total doping dose in the drift region 101, thereby reducing the specific on-resistance and significantly reducing the device's energy loss when turned on. Compared to existing GaN planar field-effect transistors, the GaN planar field-effect transistor of the first embodiment of the present invention achieves an improvement in on-resistance of several orders of magnitude over existing power devices at the same breakdown voltage, significantly reducing power loss in power semiconductor devices and achieving energy conservation and emission reduction. Furthermore, the advantages of GaN devices are fully utilized, the process flow is simplified, and manufacturing costs are reduced.

[0082] A planar power semiconductor device according to a second embodiment of the present invention:

[0083] like Figure 2 FIG. 1 is a schematic structural diagram of a planar power semiconductor device according to a second embodiment of the present invention. Compared with the first embodiment of the present invention, the planar power semiconductor device according to the second embodiment of the present invention has the following features:

[0084] While keeping the total doping dose of the drift region 101 unchanged, the drift region 101 is divided into multiple drift sub-regions 101a in the transverse direction. The doping concentration of each drift sub-region 101a is different, and the surface electric field of the drift region 101 is regulated by setting the doping concentration of each drift sub-region 101a so that the surface electric field of the drift region 101 is uniformly distributed. Figure 2 In FIG. 1 , each drift sub-region is individually marked with a mark 101 a.

[0085] The widths of the drift sub-regions 101 a are equal or unequal.

[0086] The total doping dose of the drift region 101 is 2e13 cm -2 .

[0087] In the second embodiment of the present invention, the depth of each drift sub-region 101a is the same, and the doping concentration of each drift sub-region 101a is adjusted by the ion implantation dose corresponding to each drift sub-region 101a. In other words, in the second embodiment of the present invention, the doping concentration of each drift sub-region 101a is unequal, which can be achieved through multiple ion implantations. The difference in doping concentration between each drift sub-region 101a can be achieved by adjusting the implantation dose. The choice of doping concentration determines the distribution of the surface electric field.

[0088] In the direction from the second side of the gate structure to the drain region 4, the doping concentration of each drift sub-region 101a increases or decreases in sequence, or first increases in sequence and then decreases after increasing to the maximum value, or first decreases in sequence and then increases after decreasing to the minimum value.

[0089] like Figure 2A As shown, Figure 2 The structural diagram of the corresponding drift sub-area when the number of segments is 2; it can be seen that Figure 2A There are two drift sub-regions 101a in the structure, which can be achieved by two ion implantations. The doping concentration of the corresponding drift sub-region 101a can be adjusted by adjusting the implantation dose in each ion implantation. The total doping dose of the two ion implantations is precisely controlled to be 2e13cm -2 .

[0090] like Figure 2B As shown, Figure 2 The structural diagram of the corresponding drift sub-area when the number of segments is 3; it can be seen that Figure 2B The three drift sub-regions 101a can be achieved by three ion implantations. The total doping dose of the three ion implantations is precisely controlled to be 2e13cm -2 .

[0091] In the second embodiment of the present invention, while the total doping dose of the drift region 201 is controlled, the drift region 201 can be doped in sections, thereby effectively adjusting the surface electric field strength of the drift region 201 to achieve a charge balance effect in the drift region 201. Thus, compared with existing GaN planar field-effect transistors, the GaN planar field-effect transistor of the second embodiment of the present invention can achieve an improvement in on-resistance by several orders of magnitude over existing power devices at the same breakdown voltage, significantly reducing power loss in power semiconductor devices and achieving energy conservation and emission reduction. Furthermore, the advantages of GaN devices are fully utilized, the process flow is simplified, and manufacturing costs are reduced.

[0092] A planar power semiconductor device according to a third embodiment of the present invention:

[0093] like Figure 3 FIG. 1 is a schematic structural diagram of a planar power semiconductor device according to a third embodiment of the present invention. Compared with the first embodiment of the present invention, the planar power semiconductor device according to the third embodiment of the present invention has the following features:

[0094] While keeping the total doping dose of the drift region 101 unchanged, the drift region 101 is divided into multiple drift sub-regions 101b in the transverse direction. The doping concentration of each drift sub-region 101b is different, and the surface electric field of the drift region 101 is regulated by setting the doping concentration of each drift sub-region 101b so that the surface electric field of the drift region 101 is uniformly distributed. Figure 3 In FIG. 1 , each drift sub-region is individually marked with a mark 101b.

[0095] The widths of the drift sub-regions 101 b are equal or unequal.

[0096] The total doping dose of the drift region 101 is 2e13 cm -2 .

[0097] The depths of the drift sub-regions 101b are different, and the ion implantation doses corresponding to the drift sub-regions 101b are equal. The doping concentrations of the drift sub-regions 101b are adjusted by the ion implantation energies corresponding to the drift sub-regions 101b. The greater the ion implantation energy, the deeper the depth of the drift sub-regions 101b and the lower the doping concentration.

[0098] In the third embodiment of the present invention, the doping concentration of each drift sub-region 101 b decreases sequentially from the second side surface of the gate structure toward the drain region 4, corresponding to a sequential increase in the depth of each drift sub-region 101 b. Since the ion implantation dose corresponding to each drift sub-region 101 b is equal, the deeper the drift sub-region 101 b, the lower the corresponding doping concentration, and vice versa.

[0099] like Figure 3A As shown, Figure 3 Schematic diagram of the structure when the number of segments of the corresponding drift sub-region is 2; two ion implantations were performed with equal implantation doses and the total dose controlled to be equal to 2e13 cm -2 ; The injection energy increases successively, so that the doping concentration decreases successively, and finally the surface electric field of the drift region 101 is adjusted by the doping concentration.

[0100] like Figure 3B As shown, Figure 3 Schematic diagram of the structure when the number of segments of the corresponding drift sub-region is 3; three ion implantations were performed with equal implantation doses and the total dose controlled to be equal to 2e13 cm -2 ; The injection energy increases successively, so that the doping concentration decreases successively, and finally the surface electric field of the drift region 101 is adjusted by the doping concentration.

[0101] A planar power semiconductor device according to a fourth embodiment of the present invention:

[0102] like Figure 4 FIG. 1 is a schematic structural diagram of a planar power semiconductor device according to a fourth embodiment of the present invention. Compared with the third embodiment of the present invention, the planar power semiconductor device according to the fourth embodiment of the present invention has the following features:

[0103] In a direction from the second side surface of the gate structure to the drain region 4 , the doping concentration of each drift sub-region 101 b increases sequentially, corresponding to a sequential decrease in the depth of each drift sub-region 101 b .

[0104] like Figure 4A As shown, Figure 4 Schematic diagram of the structure when the number of segments of the corresponding drift sub-region is 3; three ion implantations were performed with equal implantation doses and the total dose controlled to be equal to 2e13 cm -2; The injection energy is reduced successively, so that the doping concentration is increased successively, and finally the surface electric field of the drift region 101 is adjusted by the doping concentration.

[0105] A planar power semiconductor device according to a fifth embodiment of the present invention:

[0106] like Figure 5 FIG. 1 is a schematic structural diagram of a planar power semiconductor device according to a fifth embodiment of the present invention. Compared with the third embodiment of the present invention, the planar power semiconductor device according to the fifth embodiment of the present invention has the following features:

[0107] In the direction from the second side of the gate structure to the drain region 4, the doping concentration of each drift sub-region 101b first increases in sequence and then decreases in sequence after increasing to the maximum value; the depth of each drift sub-region 101b first decreases in sequence and then increases in sequence after decreasing to the minimum value.

[0108] A planar power semiconductor device according to a sixth embodiment of the present invention:

[0109] like Figure 6 FIG. 1 is a schematic structural diagram of a planar power semiconductor device according to a sixth embodiment of the present invention. Compared with the third embodiment of the present invention, the planar power semiconductor device according to the sixth embodiment of the present invention has the following features:

[0110] In the direction from the second side of the gate structure to the drain region 4, the doping concentration of each drift sub-region 101b first decreases in sequence and then increases in sequence after decreasing to a minimum value; the depth corresponding to each drift sub-region 101b first increases in sequence and then decreases in sequence after increasing to a maximum value.

[0111] A planar power semiconductor device according to a seventh embodiment of the present invention:

[0112] like Figure 7 FIG. 1 is a schematic structural diagram of a planar power semiconductor device according to a seventh embodiment of the present invention. Compared with the first embodiment of the present invention, the planar power semiconductor device according to the seventh embodiment of the present invention has the following features:

[0113] The drift region 201 is composed of a second epitaxial layer formed on the surface of the first epitaxial layer 2 and partially etched. Figure 7 In FIG. 2 , the drift region is marked separately with a mark 201 .

[0114] The junction depth of the drift region 201 is less than or equal to the junction depth of the drain region 4 .

[0115] In a longitudinal direction, the drain region 4 extends from the top surface of the second epitaxial layer into the first epitaxial layer 2 .

[0116] The drift region 201 is uniformly doped, and the total doping dose of the drift region 201 is controlled so that the drift region 201 forms a charge-balanced structure. The total doping dose of the drift region 201 is precisely controlled to be 2e13cm -2 .

[0117] The eighth embodiment of the present invention is a planar power semiconductor device:

[0118] like Figure 8 FIG. 1 is a schematic structural diagram of a planar power semiconductor device according to an eighth embodiment of the present invention. Compared with the seventh embodiment of the present invention, the planar power semiconductor device according to the eighth embodiment of the present invention has the following features:

[0119] Under the condition that the total doping dose of the drift region 201 remains unchanged, the second epitaxial layer of the drift region 201 is divided into a plurality of second epitaxial sub-layers 201a in the longitudinal direction. The total doping dose of the drift region 201 is 2e13cm -2 .

[0120] The second side surface of each second epitaxial sub-layer 201 a is flush and aligned with the first side surface of the drain region 4 .

[0121] In a longitudinal direction from bottom to top, the distance between the first side surface of each second epitaxial sub-layer 201 a and the first side surface of the gate structure increases.

[0122] The doping concentrations of the second epitaxial sub-layers 201 a are equal or unequal.

[0123] When the doping concentrations of each second epitaxial sub-layer 201a are not equal, in the longitudinal direction from bottom to top, the doping concentrations of each second epitaxial sub-layer 201a increase or decrease successively, or first increase successively and then decrease successively after increasing to the maximum value, or first decrease successively and then increase successively after decreasing to the minimum value.

[0124] The thicknesses of the second epitaxial sub-layers 201 a are equal or unequal.

[0125] When the thicknesses of each second epitaxial sublayer 201a are not equal, in the longitudinal direction from bottom to top, the thicknesses of each second epitaxial sublayer 201a increase or decrease successively, or first increase successively and then decrease successively after increasing to the maximum value, or first decrease successively and then increase successively after decreasing to the minimum value.

[0126] like Figure 8A As shown, Figure 8 The corresponding structural diagram of the second epitaxial sub-layer 201a is 2; two epitaxial growths are performed, and the total implantation dose of the two epitaxial growths is controlled to be equal to 2e13cm -2 .

[0127] like Figure 8B As shown, Figure 8 The corresponding structural diagram of the second epitaxial sub-layer 201a is 3 layers; three epitaxial growths are performed, and the total implantation dose of the three epitaxial growths is controlled to be equal to 2e13cm -2 .

[0128] The device structure proposed in the embodiments of the present invention has important value in power semiconductor devices based on gallium nitride. However, the device structure is not limited to gallium nitride materials, and any material used to manufacture power semiconductor devices is applicable.

[0129] The main core of the embodiment of the present invention is to use the concept of charge balance to design the drift region of the planar device. Through this structure, the electric field distribution can be optimized to make it more uniform. The effect is to reduce the device's specific on-resistance while increasing the device's breakdown voltage, thereby achieving the purpose of reducing costs and improving device reliability.

[0130] The embodiments of the present invention have the following significant features:

[0131] The device structure of the embodiment of the present invention utilizes the concept of charge balance to specifically optimize the drift region. The device structures of the embodiment of the present invention mainly fall into two categories, primarily differing in their implementation methods. One is through ion implantation and activation, such as the devices of the first to sixth embodiments of the present invention; the other is through epitaxial growth and local etching, such as the devices of the seventh to eighth embodiments of the present invention. Although both implementation methods are common semiconductor processes, they have different significance for the device structure.

[0132] The embodiment of the present invention further divides the drift region into different areas on the basis of charge balance, can be specifically designed according to device requirements, and can set the length, width, doping concentration and dosage of each divided area of ​​the drift region.

[0133] The drift region of the embodiment of the present invention can be divided into finite element division or extended to infinite element division, that is, the drift region can be divided into infinitely small individuals so that the depth or doping concentration becomes a gradient structure.

[0134] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A planar power semiconductor device, characterized in that: The device unit includes: a first epitaxial layer formed on a substrate; A gate structure is formed on the surface of the first epitaxial layer; the gate structure includes a gate dielectric layer formed on the surface of the first epitaxial layer and a gate conductive material layer formed on the surface of the gate dielectric layer; A source region heavily doped with a first conductivity type is self-aligned with a first side surface of the gate structure; A gap exists between the drain region heavily doped with the first conductivity type and the second side surface of the gate structure; A drift region doped with a first conductivity type is located between the second side surface of the gate structure and the drain region; The conductive channel is composed of an inversion layer formed when the surface of the first epitaxial layer covered by the gate structure is inverted; The doping concentration distribution of the drift region forms a charge balance structure, and when reverse biased, the charge balance structure causes the drift region to be completely depleted and the surface electric field to be uniformly distributed; The planar power semiconductor device is a gallium nitride planar field-effect transistor; The substrate is an insulating substrate; The first epitaxial layer is a gallium nitride epitaxial layer; The first epitaxial layer is doped with the second conductivity type or is undoped; controlling a total doping dose of the drift region so that the drift region forms a charge-balanced structure; The drift region is composed of a second epitaxial layer formed on the surface of the first epitaxial layer and partially etched; the drain region extends vertically from the top surface of the second epitaxial layer into the first epitaxial layer; the second epitaxial layer in the drift region is divided into a plurality of second epitaxial sublayers in the vertical direction; the second side surface of each second epitaxial sublayer is flush and aligned with the first side surface of the drain region; and the distance between the first side surface of each second epitaxial sublayer and the first side surface of the gate structure increases vertically from bottom to top; The doping concentrations of the second epitaxial sub-layers are not equal; In the longitudinal direction from bottom to top, the doping concentration of each second epitaxial sublayer increases or decreases sequentially, or first increases sequentially and then decreases sequentially after increasing to a maximum value, or first decreases sequentially and then increases sequentially after decreasing to a minimum value.

2. The planar power semiconductor device according to claim 1, wherein: The total doping dose of the drift region is 2e13 cm -2 .

3. The planar power semiconductor device according to claim 1, wherein: The thicknesses of the second epitaxial sub-layers are equal or unequal.

4. The planar power semiconductor device according to claim 3, wherein: When the thicknesses of each second epitaxial sublayer are not equal, in the longitudinal direction from bottom to top, the thicknesses of each second epitaxial sublayer increase or decrease successively, or first increase successively and then decrease successively after increasing to the maximum value, or first decrease successively and then increase successively after decreasing to the minimum value.

5. The planar power semiconductor device according to claim 1, wherein: The material of the gate dielectric layer includes silicon oxide or aluminum oxide.

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