Multi-chip systems and their operation methods

Abstract

This invention provides a multi-chip system and a method for operating the multi-chip system. The multi-chip system includes a first chip and a second chip. The first chip and at least one second chip are disposed on a circuit layer. The first chip includes a first select pin and a first test circuit. The first select pin receives a first select signal. The first test circuit is coupled to the first select pin and includes multiple first input / output pins. Each second chip includes a second select pin and a second test circuit. The second select pin receives a second select signal. The second test circuit is coupled to the second select pin and includes multiple second input / output pins. The multiple first input / output pins are correspondingly connected to the multiple second input / output pins of each second chip and are connected to multiple common traces. The multi-chip system and the method for operating the multi-chip system of this invention can effectively save the number of solder balls and provide good design-for-test functionality.

Description

Technical Field

[0001] This invention relates to an integrated system, and more particularly to a multi-chip system and a method of operating the multi-chip system. Background Technology

[0002] To meet the design-for-testability (DFT) requirements in the manufacturing process of high-speed chips, each chip in a multi-chip system currently requires corresponding test circuits and multiple input / output pins for DFT testing functions. This results in the integrated size of the multi-chip system being affected by the large number of solder balls used to connect to the multiple input / output pins, leading to excessive board space usage and hindering the reduction of the system's overall size. Summary of the Invention

[0003] This invention relates to a multi-chip system and a method for operating a multi-chip system, which can effectively save the number of solder balls and demonstrate good Design for Testing (DFT) testing capabilities.

[0004] According to an embodiment of the present invention, the multi-chip system of the present invention includes a first chip and at least one second chip. The first chip is disposed on a line layer. The first chip includes a first select pin and a first test circuit. The first select pin receives a first select signal. The first test circuit is coupled to the first select pin and includes a plurality of first input / output pins. At least one second chip is disposed on a line layer. Each second chip includes a second select pin and a second test circuit. The second select pin receives a second select signal. The second test circuit is coupled to the second select pin and includes a plurality of second input / output pins. The plurality of first input / output pins are correspondingly connected to the plurality of second input / output pins and connected to a plurality of common traces.

[0005] According to embodiments of the present invention, the operation method of the multi-chip system of the present invention is applicable to a multi-chip system. The multi-chip system includes a first chip and at least one second chip. The first chip includes a first select pin and a first test circuit. The first test circuit is coupled to the first select pin. The first test circuit includes a plurality of first input / output pins. Each second chip includes a second select pin and a second test circuit. The second test circuit is coupled to the second select pin. The second test circuit includes a plurality of second input / output pins. The first chip and at least one second chip are disposed on a line layer. The plurality of first input / output pins are correspondingly connected to the plurality of second input / output pins of each second chip and are connected to a plurality of common traces. The operation method includes the following steps: receiving a first selection signal through a first selection pin and receiving a second selection signal through a second selection pin; when the first chip operates in test mode according to the first selection signal, and each second chip operates in high-impedance mode according to the second selection signal, obtaining first input data of the first chip or sending first output data of the first chip through multiple first input / output pins and multiple common traces; and when the first chip operates in high-impedance mode according to the first selection signal, and one of the at least two second chips under test operates in test mode according to the second selection signal, while a non-under-test second chip other than the under-test second chip operates in high-impedance mode according to the second selection signal of the non-under-test second chip, obtaining second input data of the second chip or sending second output data of the second chip through multiple second input / output pins and multiple common traces.

[0006] Based on the above, the multi-chip system and its operation method of the present invention can achieve the characteristic of having common traces through the design of test circuits and coupling methods within each chip, thereby effectively saving the number of solder balls (effectively saving the size of the multi-chip system) and demonstrating good testability design and testing functions.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a circuit diagram of a multi-chip system according to an embodiment of the present invention;

[0009] Figure 2A This is a flowchart of an operation method of a multi-chip system according to an embodiment of the present invention;

[0010] Figure 2B This is a circuit diagram of a test unit according to an embodiment of the present invention;

[0011] Figure 3This is a schematic diagram of the structure of a multi-chip system according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of the structure of a multi-chip system according to another embodiment of the present invention. Detailed Implementation

[0013] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0014] Figure 1 This is a circuit diagram of a multi-chip system according to an embodiment of the present invention. (Reference) Figure 1 The multi-chip system 100 includes a first chip 110 and at least one second chip. The first chip 110 and at least one second chip are disposed on a circuit layer. For example, the first chip 110 and at least one second chip may be disposed side by side on the circuit layer. It should be noted that the number of second chips in this invention may be one or more, and is not limited to this. Figure 1As shown, and in the following embodiment, a second chip 120 is used as an example. The first chip 110 includes a first test circuit 111 and a first selection pin 112. The first test circuit 111 is coupled to the first selection pin 112. The first test circuit 111 includes a plurality of first input / output pins 113_1 to 113_N, where N is a positive integer. The first selection pin 112 can receive a first selection signal SS1. The second chip 120 includes a second test circuit 121 and a second selection pin 122 (each second chip includes a second test circuit and a second selection pin). The second test circuit 121 is coupled to the second selection pin 122. The second test circuit 121 includes a plurality of second input / output pins 123_1 to 123_N (each second chip's second test circuit includes a plurality of second input / output pins). The second selection pin 112 can receive a second selection signal SS2. In this embodiment, the first input / output pins 113_1 to 113_N are connected one-to-one with the second input / output pins 123_1 to 123_N (the first input / output pins 113_1 to 113_N are correspondingly connected to multiple second input / output pins of each second chip), and are connected to multiple common traces to transmit multiple input data Di1 to DiN and / or multiple output data Do1 to DoN through the multiple common traces. It is worth noting that the circuit layer can be disposed on a substrate (e.g., a printed circuit board, PCB) using multiple first solder balls, and the substrate can also be provided with multiple second solder balls opposite to the multiple first solder balls. The multiple first solder balls can be formed using a controlled collapse chip connection (C4) process technology, and the multiple second solder balls can be formed using a ball grid array (BGA) process technology. Therefore, the structural configuration of the circuit layer, the plurality of common traces, the plurality of first solder balls, the plurality of second solder balls, and the substrate will be as follows: Figure 3 and Figure 4 Detailed description of the embodiments.

[0015] Figure 2A This is a flowchart illustrating an operation method of a multi-chip system according to an embodiment of the present invention. (See reference...) Figure 1 as well as Figure 2AThe multi-chip system 100 can perform the following steps S210 to S230 to achieve good data transmission functionality. In step S210, the first chip 110 can receive a first selection signal SS1 through the first selection pin 112, and the second chip 120 can receive a second selection signal SS2 through the second selection pin 122 (different second chips receive different second selection signals). In step S220, when the first chip 110 operates in test mode according to the first selection signal SS1, and the second chip 120 operates in high-impedance mode according to the second selection signal SS2 (each second chip operates in high-impedance mode), the first chip 110 can obtain its first input data (e.g., input data Di1 to DiN) or send its first output data (e.g., output data Do1 to DoN) through multiple first input / output pins 113_1 to 113_N and multiple common traces. In some examples, the first chip 110 can obtain first input data or send first output data through at least a portion of the first input / output pins 113_1 to 113_N and at least a portion of the common traces. In step S230, when the first chip 110 operates in high-impedance mode according to the first selection signal SS1, and one of the at least two second chips, the second chip under test 120, operates in test mode according to the second selection signal SS2 of the second chip under test 120, and simultaneously other non-test second chips besides the second chip under test 120 operate in high-impedance mode according to the second selection signal of the non-test second chip, the second chip under test 120 can obtain second input data (e.g., input data Di1 to DiN) or send second output data (e.g., output data Do1 to DoN) through the multiple second input / output pins 123_1 to 123_N and the multiple common traces. In some examples, the second chip under test 120 can obtain second input data or send second output data through at least a portion of the multiple second input / output pins 123_1 to 123_N and at least a portion of the multiple common traces. In this way, the first chip 110 and the second chip 120 (at least one second chip) can use the multiple common traces to transmit data in a time-division multiplexing or simultaneously. Therefore, the multi-chip system 100 of the present invention can effectively save the number of solder balls and the size of the multi-chip system 100, and can demonstrate good Design for Testing (DFT) testing capabilities.

[0016] Figure 2B This is a circuit diagram of a test unit according to an embodiment of the present invention. (Reference) Figure 2B Each of the plurality of first input / output pins 113_1 to 113_N and the plurality of second input / output pins 123_1 to 123_N of the first test circuit 111 and the second test circuit 121 described above can individually correspond to, as follows: Figure 2B The test architecture 210 is shown. In this embodiment, the test architecture 210 includes a test unit 211 and an AND gate unit 212. The test unit 211 includes an output enable terminal OE, a data output terminal DATA_OUT, a data input terminal DATA_C, and input / output pins 213 coupled to the input / output terminals PAD (i.e., Figure 1 (One of the multiple first input / output pins 113_1 to 113_N shown, or one of the multiple second input / output pins 123_1 to 123_N). The first input of AND gate unit 212 receives the selection signal SS. The second input of AND gate unit 212 receives the test control signal TC. The output of AND gate unit 212 is coupled to the output enable terminal OE of test unit 211.

[0017] In this embodiment, when the output enable pin OE of the test unit 211 is enabled, the test unit 211 receives output data Do from the data output pin DATA_OUT, and outputs output data Do from the input / output pin 213. The output data Do can be provided by an internal computational test unit coupled to the data output pin DATA_OUT. When the output enable pin OE of the test unit 211 is disabled, the test unit 211 receives input data Di from an input / output pin 213, and outputs input data Di from the data input pin DATA_C. The input data Di can be provided to the internal computational test unit coupled to the data input pin DATA_C for testing. Therefore, the test architecture 210 can effectively implement the Design for Testing (DFT) testing function of the corresponding chip.

[0018] Figure 3 This is a schematic diagram of a multi-chip system according to an embodiment of the present invention. (Reference) Figure 3 , Figure 3 Multi-chip system 300 Figure 1An exemplary implementation architecture of a multi-chip system 100. In this embodiment, a first chip 310 and a second chip 320 are disposed on a circuit layer 330, wherein the circuit layer 330 may be a silicon interposer. The circuit layer 330 is disposed on a substrate 340. A first select pin of the first chip 310 is disposed on the circuit layer 330 via solder balls 314, and a plurality of first input / output pins of the first chip 310 are disposed on the circuit layer 330 via solder balls 315_1 to 315_N. A second select pin of the second chip 320 is disposed on the circuit layer 330 via solder balls 324, and a plurality of second input / output pins of the second chip 320 are disposed on the circuit layer 330 via solder balls 325_1 to 325_N. The number of the plurality of first input / output pins may be the same as the number of the plurality of second input / output pins, but the present invention is not limited thereto. Solder balls 314 and 315_1 to 315_N, as well as solder balls 324 and 325_1 to 325_N, can be microbumps formed by connecting upper and lower micro-copper pillars and solder (e.g., solder). Solder balls 314 and 324 can be connected to solder balls 334 and 335 on the other side of the circuit layer 330 via traces 331 and 332 (or, for example, vias and through-silicon vias, TSVs) provided in the circuit layer 330. Solder balls 315_1 to 315_N and 325_1 to 325_N can be connected to solder balls 336_1 to 336_N on the other side of the circuit layer 330 via common traces 333_1 to 333_N provided in the circuit layer 330 (or, for example, vias and through-silicon vias). The circuit layer 330 is disposed on the substrate 340 via solder balls 334, 335, and 336_1 to 336_N. Multiple first input / output pins of the first chip 310 and multiple second input / output pins of the second chip 320 (each second chip) are connected in the circuit layer 330 via solder balls 315_1 to 315_N, 325_1 to 325_N, and common traces 333_1 to 333_N. Common traces 333_1 to 333_N, the first selection pin of the first chip 310 (via solder ball 314 and trace 331), and the second selection pin of the second chip 320 (each second chip) (via solder ball 324 and trace 332) are respectively connected to solder balls 334, 335, and 336_1 to 336_N. Solder balls 334, 335, 336_1 to 336_N can be connected to solder balls 345, 346, 347_1 to 347_N on the other side of substrate 340 via traces 341, 342, 343_1 to 343_N provided in substrate 340 (or, for example, vias and silicon vias). Solder balls 345, 346, 347_1 to 347_N can be connected to other circuit boards, other external traces, or other external circuits.In the above embodiments, the number of solder balls 334, 335, 336_1 to 336_N (or solder balls 345, 346, 347_1 to 347_N) is equal to the sum of the number of chips (including the first chip 310 and the second chip 320) in the chip system 300 and the number of multiple first (or second) input / output pins. Therefore, compared to the case where there is no common routing, the multi-chip system 300 of the present invention can effectively save the number of solder balls and can effectively save the size of the multi-chip system 300.

[0019] Figure 4 This is a schematic diagram of a multi-chip system according to another embodiment of the present invention. (See reference) Figure 4 , Figure 4 Multi-chip system 400 Figure 1Another exemplary implementation architecture of the multi-chip system 100. In this embodiment, a first chip 410 and a second chip 420 are disposed on a circuit layer 430, wherein the circuit layer 430 may be a silicon interposer. The circuit layer 430 is disposed on a substrate 440. A first select pin of the first chip 410 may be disposed on the circuit layer 430 via solder balls 414, and a plurality of first input / output pins of the first chip 410 may be disposed on the circuit layer 430 via solder balls 415_1 to 415_N. A second select pin of the second chip 420 may be disposed on the circuit layer 430 via solder balls 424, and a plurality of second input / output pins of the second chip 420 may be disposed on the circuit layer 430 via solder balls 425_1 to 425_N. The number of the plurality of first input / output pins may be the same as the number of the plurality of second input / output pins, but the invention is not limited thereto. Solder balls 414 and 415_1 to 415_N, as well as solder balls 424 and 425_1 to 425_N, can be microbumps (μbumps) formed by connecting upper and lower microcopper pillars and solder (e.g., solder). Solder balls 414 and 424 can be connected to solder balls 435 and 436 on the other side of circuit layer 430 via traces 431 and 432 (or vias, for example, circuits and through-silicon vias) provided in circuit layer 430. Solder balls 415_1 to 415_N can be connected to solder balls 437_1 to 437_N on the other side of circuit layer 430 via traces 433_1 to 433_N provided in circuit layer 430 (or vias, for example, circuits and through-silicon vias). Solder balls 425_1 to 425_N can be connected to solder balls 438_1 to 438_N on the other side of the circuit layer 430 via traces 434_1 to 434_N (or, for example, vias and through-silicon vias) provided in the circuit layer 430. The circuit layer 430 can be disposed on the substrate 440 via solder balls 435, 436, 437_1 to 437_N, and 438_1 to 438_N. On the other side of the substrate 440, there are also multiple solder balls 444, 445, and 446_1 to 446_N opposite to the solder balls 435, 436, 437_1 to 437_N, and 438_1 to 438_N. Solder balls 435 and 436 can be connected to solder balls 444 and 445 on the other side of the substrate 440 via traces 441 and 442 provided in the substrate 440 (or, for example, vias and through-silicon vias). Solder balls 437_1 to 437_N and 438_1 to 438_N can be connected to solder balls 446_1 to 446_N on the other side of substrate 440 via common traces 443_1 to 443_N provided in substrate 440 (or, for example, vias and through-silicon vias).Multiple first input / output pins of the first chip 410 and multiple second input / output pins of the second chip 420 (each second chip) (connected via solder balls 415_1 to 415_N, 425_1 to 425_N, 437_1 to 437_N, 438_1 to 438_N, and traces 433_1 to 433_N, 434_1 to 434_N, and common traces 443_1 to 443_N) are connected in the substrate 440. Multiple common traces 443_1 to 443_N, the first selection pins of the first chip 410 (connected via solder balls 414, 435 and traces 431, 441), and the second selection pins of the second chip 420 (each second chip) (connected via solder balls 424, 436 and traces 432, 442) are respectively connected to solder balls 444, 445, 446_1 to 446_N. Solder balls 444, 445, 446_1 to 446_N can be connected to other circuit boards, other external traces, or other external circuits. In the above embodiments, the number of solder balls 444, 445, 446_1 to 446_N is equal to the sum of the number of chips (including the first chip 410 and the second chip 420) in the chip system 300 and the number of multiple first (or second) input / output pins. Therefore, compared to the case without common traces, the multi-chip system 400 of the present invention can effectively save the number of solder balls and can effectively save the size of the multi-chip system 300.

[0020] In summary, the multi-chip system and its operation method of the present invention can effectively reduce the number of solder balls used for design-for-testability testing functions in common routing designs in the circuit layer and / or substrate (effectively reducing the size of the multi-chip system). Therefore, the multi-chip system of the present invention can further integrate more chips and provide good design-for-testability testing functions.

[0021] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-chip system, characterized in that, include: The first chip, located on the circuit layer, includes: The first selection pin receives the first selection signal; and A first test circuit, coupled to the first selection pin, and including a plurality of first input / output pins; and Multiple second chips are disposed on the circuit layer, each second chip comprising: The second selection pin receives the second selection signal; and The second test circuit is coupled to the second selection pin and includes multiple second input / output pins. The plurality of first input / output pins are connected to the plurality of second input / output pins of each of the second chips, and are connected to a plurality of common traces in the circuit layer or substrate, and each of the plurality of common traces is connected to a solder ball located between the circuit layer and the substrate. The first test circuit includes: Multiple first test units, each corresponding to a plurality of first input / output pins, each first test unit including a first output enable terminal, a first data output terminal, a first data input terminal, and one of the plurality of first input / output pins; A first AND gate unit, wherein a first input terminal of the first AND gate unit receives the first selection signal, a second input terminal of the first AND gate unit receives a first test control signal, and the output terminal of the first AND gate unit is respectively coupled to the first output enable terminal of the plurality of first test units; and A first internal computation test unit, wherein when the first output enable terminal of the first test unit is enabled, the first internal computation test unit provides first output data to the first data output terminal; when the first output enable terminal of the first test unit is disabled, the first internal computation test unit receives first input data from the first data input terminal and tests the first input data. The second test circuit includes: Multiple second test units, each corresponding to a plurality of second input / output pins, each second test unit including a second output enable terminal, a second data output terminal, a second data input terminal, and one of the plurality of second input / output pins; A second AND gate unit, wherein the first input of the second AND gate unit receives the second selection signal, the second input of the second AND gate unit receives the second test control signal, and the output of the second AND gate unit is respectively coupled to the second output enable terminals of the plurality of second test units; and The second internal operation test unit, wherein when the second output enable terminal of the second test unit is enabled, the second internal operation test unit provides second output data to the second data output terminal; when the second output enable terminal of the second test unit is disabled, the second internal operation test unit receives second input data from the second data input terminal and tests the second input data.

2. The multi-chip system according to claim 1, characterized in that, The circuit layer is disposed on the substrate by a plurality of first solder balls. The plurality of first input / output pins and the plurality of second input / output pins of each second chip are connected in the circuit layer. The plurality of common traces, the first selection pins and the second selection pins of each second chip are respectively connected to the plurality of first solder balls.

3. The multi-chip system according to claim 1, characterized in that, The circuit layer is disposed on the substrate by a plurality of first solder balls. The substrate is also disposed with a plurality of second solder balls opposite to the plurality of first solder balls. The plurality of first input / output pins and the plurality of second input / output pins of each second chip are connected in the substrate. The plurality of common traces, the first selection pins and the second selection pins of each second chip are respectively connected to the plurality of second solder balls.

4. The multi-chip system according to claim 1, characterized in that, When the first chip operates in test mode according to the first selection signal, and each of the second chips operates in high-impedance mode according to the second selection signal, the first chip obtains the first input data of the first chip or sends the first output data of the first chip through the plurality of first input / output pins and the plurality of common traces.

5. The multi-chip system according to claim 4, characterized in that, When the output enable terminal of the first test unit is enabled, the first test unit receives the first output data from the data output terminal and outputs the first output data from one of the plurality of first input / output pins. When the output enable terminal of the first test unit is disabled, the first test unit receives the first input data from one of the plurality of first input / output pins and outputs the first input data from the first data input terminal.

6. The multi-chip system according to claim 1, characterized in that, When the first chip operates in high-impedance mode according to the first selection signal, and one of the plurality of second chips, the second chip under test, operates in test mode according to the second selection signal of the second chip under test, while other second chips among the plurality of second chips operate in high-impedance mode according to the second selection signal of the other second chips, the second chip under test obtains the second input data of the second chip under test or sends the second output data of the second chip under test through the plurality of second input / output pins and the plurality of common traces.

7. The multi-chip system according to claim 6, characterized in that, When the output enable terminal of the second test unit is enabled, the second test unit receives the second output data from the data output terminal and outputs the second output data from one of the plurality of second input / output pins. When the output enable terminal of the second test unit is disabled, the second test unit receives the second input data from one of the plurality of second input / output pins and outputs the second input data from the second data input terminal.

8. The multi-chip system according to claim 1, characterized in that, The first chip and the plurality of second chips are arranged side by side on the circuit layer.

9. A method for operating a multi-chip system, characterized in that, The multi-chip system includes a first chip and a plurality of second chips. The first chip includes a first select pin and a first test circuit, the first test circuit being coupled to the first select pin and including a plurality of first input / output pins. Each second chip includes a second select pin and a second test circuit, the second test circuit being coupled to the second select pin and including a plurality of second input / output pins. The first chip and the plurality of second chips are disposed on a circuit layer. The plurality of first input / output pins are correspondingly connected to the plurality of second input / output pins of each second chip and are connected to a plurality of common traces in the circuit layer or substrate. Each of the plurality of common traces is connected to a solder ball located between the circuit layer and the substrate. The operation method includes: The first selection signal is received through the first selection pin, and the second selection signal is received through the second selection pin; When the first chip operates in test mode according to the first selection signal, and each of the second chips operates in high-impedance mode according to the second selection signal, the first input data of the first chip is obtained or the first output data of the first chip is sent through the plurality of first input / output pins and the plurality of common traces; and When the first chip operates in the high-impedance mode according to the first selection signal, and one of the plurality of second chips, the second chip under test, operates in the test mode according to the second selection signal of the second chip under test, while other second chips (excluding the second chip under test) operate in the high-impedance mode according to the second selection signal of the other second chips, the second input data of the second chip under test is obtained or the second output data of the second chip under test is sent through the plurality of second input / output pins and the plurality of common traces. The first test circuit includes: Multiple first test units, each corresponding to a plurality of first input / output pins, each first test unit including a first output enable terminal, a first data output terminal, a first data input terminal, and one of the plurality of first input / output pins; A first AND gate unit, wherein a first input terminal of the first AND gate unit receives the first selection signal, a second input terminal of the first AND gate unit receives a first test control signal, and the output terminal of the first AND gate unit is respectively coupled to the first output enable terminal of the plurality of first test units; and A first internal computation test unit, wherein when the first output enable terminal of the first test unit is enabled, the first internal computation test unit provides first output data to the first data output terminal; when the first output enable terminal of the first test unit is disabled, the first internal computation test unit receives first input data from the first data input terminal and tests the first input data. The second test circuit includes: Multiple second test units, each corresponding to a plurality of second input / output pins, each second test unit including a second output enable terminal, a second data output terminal, a second data input terminal, and one of the plurality of second input / output pins; A second AND gate unit, wherein the first input of the second AND gate unit receives the second selection signal, the second input of the second AND gate unit receives the second test control signal, and the output of the second AND gate unit is respectively coupled to the second output enable terminals of the plurality of second test units; and The second internal operation test unit, wherein when the second output enable terminal of the second test unit is enabled, the second internal operation test unit provides second output data to the second data output terminal; when the second output enable terminal of the second test unit is disabled, the second internal operation test unit receives second input data from the second data input terminal and tests the second input data.

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