Micro light emitting diode

Abstract

The present application provides a micro light emitting diode, comprising a first stack layer, a second stack layer, a third stack layer, a bonding layer, at least one etching stop layer and a plurality of electrodes. The first stack layer is disposed above the third stack layer, the second stack layer is disposed between the first stack layer and the third stack layer, and the first stack layer, the second stack layer and the third stack layer are three different color semiconductor light emitting stack layers. The first stack layer comprises a first active layer. The second stack layer comprises a second active layer. The third stack layer comprises a third active layer. The bonding layer is disposed between the second stack layer and the third stack layer. At least one etching stop layer is disposed between the first active layer and the second active layer. The plurality of electrodes are electrically connected to the first stack layer, the second stack layer and the third stack layer respectively, and at least one electrode contacts the etching stop layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a light emitting diode, and more particularly to a micro light emitting diode. BACKGROUND

[0002] In a micro light emitting diode display panel, the red, green and blue light emitting diode chips of each pixel are usually arranged in horizontal direction, that is, the chips of three colors are juxtaposed without overlapping each other on the panel. Under this structure, several problems to be improved will be generated. First, the space utilization of the panel is not good, and under the same pixel size, smaller chips need to be used. The size reduction of the chips will further affect the conversion efficiency of the chips. In addition, this structure needs to be transferred for the red, green and blue micro light emitting diode chips respectively during manufacturing, and three times of transfer are needed for each pixel, which increases the steps of the process. SUMMARY

[0003] The present invention is directed to a micro light emitting diode which can improve the space utilization of the panel.

[0004] In an embodiment of the present invention, a micro light emitting diode includes an epitaxial structure and a plurality of electrodes. The epitaxial structure includes a first stack layer, a second stack layer, a third stack layer, a bonding layer, and at least one etch stop layer. The first stack layer is disposed above the third stack layer, and the second stack layer is disposed between the first stack layer and the third stack layer. The first stack layer, the second stack layer, and the third stack layer are semiconductor light emitting stack layers of three different light emitting colors. The first stack layer includes a first semiconductor layer, a second semiconductor layer, and a first active layer. The first active layer is disposed between the first semiconductor layer and the second semiconductor layer. The second stack layer includes a third semiconductor layer, a fourth semiconductor layer, and a second active layer. The second active layer is disposed between the third semiconductor layer and the fourth semiconductor layer. The third stack layer includes a fifth semiconductor layer, a sixth semiconductor layer, and a third active layer. The third active layer is disposed between the fifth semiconductor layer and the sixth semiconductor layer. The bonding layer is disposed between the second stack layer and the third stack layer. The at least one etch stop layer is disposed at least between the first active layer and the second active layer, and is relatively far away from the first semiconductor layer and the fourth semiconductor layer. The plurality of electrodes are electrically connected to the first stack layer, the second stack layer, and the third stack layer, respectively. At least one electrode contacts the etch stop layer.

[0005] In an embodiment of the present application, a micro light emitting diode includes a first stack layer, a second stack layer, a third stack layer, at least one etch stop layer, and a plurality of electrodes. The first, second, and third stack layers are semiconductor light emitting stack layers of three different light emitting colors. The first stack layer is disposed above the third stack layer, and the second stack layer is disposed between the first and third stack layers. The at least one etch stop layer is disposed between at least one of the first and second stack layers and the third stack layer. The plurality of electrodes are electrically connected to the first, second, and third stack layers, respectively, and at least one of the electrodes contacts the etch stop layer.

[0006] In an embodiment of the present application, a micro light emitting diode includes a first stack layer, a second stack layer, a third stack layer, at least one etch stop layer, and a plurality of electrodes. The first, second, and third stack layers are semiconductor light emitting stack layers of three different light emitting colors. The first stack layer is disposed above the third stack layer, and the second stack layer is disposed above the third stack layer. The at least one etch stop layer is disposed between at least one of the first and second stack layers and the third stack layer. The plurality of electrodes are electrically connected to the first, second, and third stack layers, respectively, and at least one of the electrodes contacts the etch stop layer.

[0007] Based on the above, in the micro light emitting diode of the embodiment of the present application, because three light emitting diode chips are disposed in a vertical stack, the space utilization and display effect of a display panel can be increased without changing the pixel size of the display panel, and the conversion efficiency problem of chip miniaturization can be avoided. In addition, because the at least one etch stop layer is disposed between at least one of the first and second active layers, and at least one of the electrodes contacts the etch stop layer, in the process of forming the electrodes, over-etching can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application;

[0009] Figures 2A-2C is Figure 1 is a flowchart of a manufacturing process of an epitaxial structure of a micro light emitting diode;

[0010] Figure 3A and Figure 3B is a flowchart of a manufacturing process of an epitaxial structure of a micro light emitting diode according to an embodiment of the present application;

[0011] Figure 4 is formed by Figure 3A and Figure 3B is a cross-sectional view of an epitaxial structure of a micro light emitting diode formed by the process of

[0012] Figure 5A is a cross-sectional view of an epitaxial structure of a micro light emitting diode according to an embodiment of the present application;

[0013] Figure 5B is a cross-sectional view of an epitaxial structure of a micro light emitting diode according to another embodiment of the present application;

[0014] Figure 6A is a cross-sectional view of an epitaxial structure of a micro light emitting diode according to an embodiment of the present application;

[0015] Figure 6B is a cross-sectional view of an epitaxial structure of a micro light emitting diode according to another embodiment of the present application;

[0016] Figure 6C is a perspective view of a micro light emitting diode according to another embodiment of the present application;

[0017] Figure 6D is a perspective view of a micro light emitting diode according to another embodiment of the present application;

[0018] Figure 7 is a cross-sectional view of an epitaxial structure of a micro light emitting diode according to an embodiment of the present application;

[0019] Figure 8 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application;

[0020] Figure 9 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application;

[0021] Figure 10 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application;

[0022] Figure 11 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application;

[0023] Figure 12 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application;

[0024] Figure 13 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application;

[0025] Figures 14A-14C is a flow chart of a manufacturing process of a micro light emitting diode according to an embodiment of the present application;

[0026] Figure 14D is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application;

[0027] Figure 14EThis is a cross-sectional schematic diagram of a micro light-emitting diode according to an embodiment of the present invention;

[0028] Figure 15A and Figure 15B This is a manufacturing process diagram of a miniature light-emitting diode according to an embodiment of the present invention;

[0029] Figure 15C This is a cross-sectional schematic diagram of a micro light-emitting diode according to an embodiment of the present invention;

[0030] Figure 16 This is a cross-sectional schematic diagram of a micro light-emitting diode according to an embodiment of the present invention;

[0031] Figure 17 This is a cross-sectional schematic diagram of a micro light-emitting diode according to an embodiment of the present invention;

[0032] Figure 18 This is a cross-sectional schematic diagram of a micro light-emitting diode according to an embodiment of the present invention;

[0033] Figure 19 This is a cross-sectional schematic diagram of a micro light-emitting diode according to an embodiment of the present invention. Detailed Implementation

[0034] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0035] Figure 1 This is a cross-sectional schematic diagram of a miniature light-emitting diode according to an embodiment of the present invention. Please refer to... Figure 1 In this embodiment, the micro light-emitting diode 10a includes an epitaxial structure 100a and a plurality of electrodes 200. The epitaxial structure 100a includes a first stacked layer 110, a second stacked layer 120, a third stacked layer 130, a bonding layer 140, and at least one etch-stop layer 150 (in... Figure 1For example, an etch stop layer 150. A first stack layer 110 is disposed above a third stack layer 130, and a second stack layer 120 is disposed between the first stack layer 110 and the third stack layer 130. The first stack layer 110, the second stack layer 120, and the third stack layer 130 are semiconductor light-emitting stack layers with three different light-emitting colors. The first stack layer 110 includes a first semiconductor layer 112, a second semiconductor layer 114, and a first active layer 116. The first active layer 116 is disposed between the first semiconductor layer 112 and the second semiconductor layer 114. The second stack layer 120 includes a third semiconductor layer 122, a fourth semiconductor layer 124, and a second active layer 126. The second active layer 126 is disposed between the third semiconductor layer 122 and the fourth semiconductor layer 124. The third stack layer 130 includes a fifth semiconductor layer 132, a sixth semiconductor layer 134, and a third active layer 136. The third active layer 136 is disposed between the fifth semiconductor layer 132 and the sixth semiconductor layer 134, and the doping modes of the fifth semiconductor layer 132 and the sixth semiconductor layer 134 are opposite. A bonding layer 140 is disposed between the second stack layer 120 and the third stack layer 130. At least one etch stop layer 150 is disposed at least between the first active layer 110 and the second active layer 120 (in...). Figure 1 For example, it is disposed between the second semiconductor layer 114 and the third semiconductor layer 122, and is away from the first semiconductor layer 112 and the fourth semiconductor layer 124. Multiple electrodes 200 are electrically connected to the first stacked layer 110, the second stacked layer 120, and the third stacked layer 130, respectively, wherein at least one electrode 200 contacts the etch stop layer 150. In one embodiment, the spacing between the first active layer 110 and the second active layer 120 is less than 1 micrometer; therefore, the etch stop layer 150 can prevent over-etching and damage to the first active layer 110.

[0036] Specifically, in this embodiment, the first stacked layer 110 and the second stacked layer 120 belong to the same epitaxial material system, while the third stacked layer 130 belongs to a different epitaxial material system than the first stacked layer 110 and the second stacked layer 120. The epitaxial materials of the first stacked layer 110 and the second stacked layer 120 are, for example, selected from group III-V nitride-based compound semiconductors, and their composition includes Al. x In y Ga zN, where x and y and z are numbers satisfying 0≤x, y, z≤1, such as gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum nitride (AIN), but not limited thereto. The epitaxial material of the third stack layer 130 is, for example, selected from a phosphide-based compound semiconductor or an arsenide-based compound semiconductor, such as a quaternary compound including gallium indium arsenide phosphide (InGaAsP) or indium aluminum arsenide phosphide (AlGaAsP), but not limited thereto. That is, the third stack layer 130 can be formed by stacking in another epitaxial process different from the first stack layer 110 and the second stack layer 120. In the present embodiment, the semiconductor energy gap of the first active layer 116 is, for example, a photon energy corresponding to blue light, the semiconductor energy gap of the second active layer 126 is, for example, a photon energy corresponding to green light, and the semiconductor energy gap of the third active layer 136 is, for example, a photon energy corresponding to red light. By matching different materials with different light-emitting colors, better epitaxial quality can be achieved, and better chip yield can be achieved by subsequent bonding. The first stack layer 110, the second stack layer 120, and the third stack layer 130 can form the epitaxial structure 100a by a bonding process, and the positional relationship (e.g., up and down) of the layers of the micro light-emitting diode 10a in the epitaxial process and the positional relationship of the layers of the micro light-emitting diode 10a after bonding can be different. Here, by configuring the shortest wavelength blue light closest to the light-emitting surface, followed by the second shortest wavelength green light, and finally the longest wavelength red light, the absorption of light with a short wavelength can be reduced, and the light-emitting efficiency can be increased.

[0037] Figures 2A-2C is Figure 1 a flow chart of the manufacturing process of the epitaxial structure of the micro light-emitting diode. Please refer to Figures 2A-2C In the present embodiment, as Figure 2AAs shown, a first semiconductor layer 112 of N-type is formed on a first substrate 182, a first active layer 116 is formed on the first semiconductor layer 112 of N-type, a second semiconductor layer 114 of P-type is formed on the first active layer 116, an etching stop layer 150 is formed on the second semiconductor layer 114 of P-type, a third semiconductor layer 122 of P-type is formed on the etching stop layer 150, a second active layer 126 is formed on the third semiconductor layer 122 of P-type, and a fourth semiconductor layer 124 of N-type is formed on the second active layer 126. The first substrate 182 is, for example, a sapphire substrate. In addition, as shown in FIG. 1B, a first electrode 160 is formed on the fourth semiconductor layer 124 of N-type, and a second electrode 162 is formed on the third semiconductor layer 122 of P-type. Figure 2A As shown, a fifth semiconductor layer 132 of N-type is formed on a second substrate 184, a third active layer 136 is formed on the fifth semiconductor layer 132 of N-type, and a sixth semiconductor layer 134 of P-type is formed on the third active layer 136. The second substrate 184 is, for example, a gallium arsenide (GaAs) substrate. Then, as shown in FIG. 1C, the sixth semiconductor layer 134 of P-type is connected to a third substrate 186 through a connecting layer 170, and the second substrate 184 is removed. In addition, as shown in FIG. 1D, the fourth semiconductor layer 124 of N-type is connected to the fifth semiconductor layer 132 of N-type through a bonding layer 140, and the first substrate 182 is removed. Figure 2B Figure 2C As shown, a fifth semiconductor layer 132 of N-type is formed on a second substrate 184, a third active layer 136 is formed on the fifth semiconductor layer 132 of N-type, and a sixth semiconductor layer 134 of P-type is formed on the third active layer 136. The second substrate 184 is, for example, a gallium arsenide (GaAs) substrate. Then, as shown in FIG. 1C, the sixth semiconductor layer 134 of P-type is connected to a third substrate 186 through a connecting layer 170, and the second substrate 184 is removed. In addition, as shown in FIG. 1D, the fourth semiconductor layer 124 of N-type is connected to the fifth semiconductor layer 132 of N-type through a bonding layer 140, and the first substrate 182 is removed.

[0038] Please continue to refer to Figures 1-2C In the present embodiment, the material of the etching stop layer 150 includes one of a nitride-based compound semiconductor, a phosphide-based semiconductor, an arsenide-based semiconductor, or a combination of two or more thereof, but is not limited thereto.

[0039] In the present embodiment, the etching stop layer 150 can have one of various different forms, but is not limited to the forms listed below. For example, the N-type doping and the P-type doping described below can be exchanged according to design requirements. In addition, in the present embodiment, the thickness of the etching stop layer 150 is, for example, less than or equal to 1 micrometer, and a thickness that is too thick can affect the yield of the epitaxial structure.

[0040] ​In one embodiment, the etch stop layer 150 includes a compound having a different elemental composition or ratio of elements than the compound included in the second semiconductor layer 114 or the third semiconductor layer 122. For example, the second semiconductor layer 114 and the third semiconductor layer 122 include gallium nitride, and the etch stop layer 150 can include indium gallium nitride. The etch stop layer 150 includes a compound that is different from the semiconductor compound material system of the second semiconductor layer 114 or the third semiconductor layer 122, such as gallium phosphide. The etch stop layer 150 includes a compound having a different ratio of elements (indium, gallium, nitrogen) than the compound included in the second semiconductor layer 114 or the third semiconductor layer 122. That is, the composition of the etch stop layer 150 is changed from the composition of the second semiconductor layer 114 and the third semiconductor layer 122 during formation of the etch stop layer 150, the second semiconductor layer 114, and the third semiconductor layer 122. By having a different elemental composition or ratio of elements of the compound, a detector, such as a secondary ion mass spectrometer (SIMS), detects a large change in the ratio of elements of the compound being etched away during etching, indicating that the etch has reached the etch stop layer 150, and etching is stopped.

[0041] In one embodiment, the etch stop layer 150 has a different doping concentration than the second semiconductor layer 114 or the third semiconductor layer 122. For example, the etch stop layer 150 can have a doping concentration that is 2 to 10 times different than the doping concentration of the second semiconductor layer 114 or the third semiconductor layer 122, which can be a large difference, where the doping concentration of the etch stop layer 150, the second semiconductor layer 114, and the third semiconductor layer 122 is greater than or equal to 10 18 cm -3 and less than or equal to 10 22 cm -3 , less than 10 18 cm -3 , or greater than 10 22 cm -3The quality of the epitaxial structure can be affected. The doping elements of the etch stop layer 150, the second semiconductor layer 114 and the third semiconductor layer 122 can be the same type of doping, and can be formed together in an epitaxial process to increase the quality of the epitaxial yield, such as P-type doping, including magnesium (Mg), carbon (C), zinc (Zn), copper (Cu), etc., but not limited thereto. The doping elements of the etch stop layer 150, the second semiconductor layer 114 and the third semiconductor layer 122 can also be N-type doping, including silicon (Si), germanium (Ge), manganese (Mn), tellurium (Te), etc., but not limited thereto. That is, during the process of forming the etch stop layer 150, the second semiconductor layer 114 and the third semiconductor layer 122, the etch stop layer 150 has a doping concentration contrast with the second semiconductor layer 114 or the third semiconductor layer 122. Through the above-mentioned different doping concentrations, during the etching process, when the detector detects that the doping concentration of the material being etched changes greatly, it can be known that the etching has reached the position of the etch stop layer 150, and the etching is stopped. It is particularly pointed out that the etch stop layer 150 is preferably arranged between the N-type doped second semiconductor layer 114 and the third semiconductor layer 122, and the subsequent first electrode 210 is in electrical contact with the etch stop layer 150 (here, the etch stop layer 150 is also N-type), which can have a better current diffusion effect.

[0042] In an embodiment, the etch stop layer 150 includes two or more doping elements. For example, the materials of the second semiconductor layer 114 and the third semiconductor layer 122 are N-type doped gallium nitride, and the etch stop layer 150 can further dope the N-type doped gallium nitride of the second semiconductor layer 114 and the third semiconductor layer 122 with a second doping element different from the N-type doped gallium nitride of the second semiconductor layer 114 or the third semiconductor layer 122, such as carbon, magnesium, manganese, etc. That is, during the process of forming the etch stop layer 150, the second semiconductor layer 114 and the third semiconductor layer 122, the second element doping in the etch stop layer 150 is added as a detection target. Through the above-mentioned addition of the second element, during the etching process, when the detector detects the second element, it can be known that the etching has reached the position of the etch stop layer 150, and the etching is stopped.

[0043] In one embodiment, the doping element of the etch stop layer 150 is different from the doping element of the second semiconductor layer 114 or the third semiconductor layer 122. For example, the second semiconductor layer 114 and the third semiconductor layer 122 are made of N-type doped gallium nitride, and the etch stop layer 150 is made of P-type doped gallium nitride. That is, during the formation of the etch stop layer 150, the second semiconductor layer 114 and the third semiconductor layer 122, the doping type of the etch stop layer 150 is switched to a doping type different from that of the second semiconductor layer 114 or the third semiconductor layer 122. Through the difference in the doping element, when the detector detects a change in the element of the material being etched away during the etching process, it is known that the etching has reached the position of the etch stop layer 150, and the etching is stopped.

[0044] Please continue to refer to Figure 1In this embodiment, the epitaxial structure 10a has vias through the second stack layer 120, the bonding layer 140, and the third stack layer 130, the vias expose a portion of the lower surface of the etch stop layer 150, wherein at least one electrode 200 is disposed in the vias to contact the etch stop layer 150. For example, in this embodiment, a first via 192 passes through the third semiconductor layer 122, the second active layer 126, the fourth semiconductor layer 124, the bonding layer 140, the fifth semiconductor layer 132, the third active layer 136, and the sixth semiconductor layer 134, and the first via 192 exposes a portion of the lower surface of the etch stop layer 150, the electrode 210 is disposed in the first via 192 to contact the etch stop layer 150. A second via 194 passes through the third active layer 136 and the sixth semiconductor layer 134. A third via 196 passes through the bonding layer 140, the fifth semiconductor layer 132, the third active layer 136, and the sixth semiconductor layer 134. A fourth via 198 passes through the first active layer 116, the second semiconductor layer 114, the etch stop layer 150, the third semiconductor layer 122, the second active layer 126, the fourth semiconductor layer 124, the bonding layer 140, the fifth semiconductor layer 132, the third active layer 136, and the sixth semiconductor layer 134. The micro light emitting diode 10a further includes an insulating layer 300. At least a portion of the insulating layer 300 is in the first via 192, and the insulating layer 300 exposes a surface of the etch stop layer 150. At least a portion of the insulating layer 300 is in the second via, the third via, and the fourth via, and is on the sidewalls of the second via, the third via, and the fourth via. The plurality of electrodes 200 includes a first electrode 210, a second electrode 220, a third electrode 230, and a fourth electrode 240. The first electrode 210, the second electrode 220, the third electrode 230, and the fourth electrode 240 are respectively partially in the first via, the second via, the third via, and the fourth via, and are respectively partially in the insulating layer 300. The insulating layer 300 covers the side surface of the first electrode 210, and exposes the surface of the first electrode 210 connected to the etch stop layer 150, covers the side surface of the second electrode 220, and exposes the surface of the second electrode 220 connected to the fifth semiconductor layer 132, covers the side surface of the third electrode 230, and exposes the surface of the third electrode 230 connected to the fourth semiconductor layer 124, covers the side surface of the fourth electrode 240, and exposes the surface of the fourth electrode 240 connected to the first semiconductor layer 112.

[0045] In this embodiment, the first electrode 210 penetrates through the third semiconductor layer 122, the second active layer 126, the fourth semiconductor layer 124, the bonding layer 140, the fifth semiconductor layer 132, the third active layer 136 and the sixth semiconductor layer 134, and the first electrode 210 electrically connects the second semiconductor layer 114, the third semiconductor layer 122 (P-type doped in this embodiment), and the sixth semiconductor layer 134 (P-type doped in this embodiment). That is, the first electrode 210 is a shared anode of the first stack layer 110, the second stack layer 120 and the third stack layer 130. The second electrode 220 is a cathode of the third stack layer 130, which contacts the fifth semiconductor layer 132 (N-type doped in this embodiment) and electrically connects the fifth semiconductor layer 132 through the surface exposed by the insulating layer 300. The third electrode 230 is a cathode of the second stack layer 120, which contacts the fourth semiconductor layer 124 (N-type doped in this embodiment) and electrically connects the fourth semiconductor layer 124 through the surface exposed by the insulating layer 300. The fourth electrode 240 is a cathode of the first stack layer 110, which contacts the first semiconductor layer 112 (N-type doped in this embodiment) and electrically connects the first semiconductor layer 112 through the surface exposed by the insulating layer 300.

[0046] In this embodiment, because three light emitting diode chips are arranged in a vertical stack, the space utilization of the display panel can be increased, and larger light emitting diode chips can be used without changing the pixel size of the display panel, thereby avoiding the conversion efficiency problem of chip miniaturization. In addition, because at least one etching stop layer 150 is arranged between the first stack layer 110 and the second stack layer 120, and the first electrode 210 contacts the etching stop layer 150, in the case of each layer of the micro light emitting diode having a thickness in the nanometer level, over-etching and damage to the first active layer 110 can be avoided during the process of forming the first electrode 210, especially when a through hole is needed. In another embodiment, the at least one etching stop layer 150 can also be arranged between the second stack layer 120 and the third stack layer 130.

[0047] Figure 3A and Figure 3B is a flowchart of the manufacturing process of the epitaxial structure of the micro light emitting diode according to an embodiment of the present application. Figure 4 is an epitaxial structure of a micro light emitting diode formed by the process of Figure 3A and Figure 3B is a cross-sectional schematic view of the epitaxial structure of the micro light emitting diode formed by the process of Figures 3A-4 The manufacturing process of this embodiment is similar to that of the embodiment of Figures 2A-2C The difference between this embodiment and the embodiment of Figure 3AAs shown, an N-type sixth semiconductor layer 134a is formed on the second substrate 184, a third active layer 136 is formed on the N-type sixth semiconductor layer 134a, and a P-type fifth semiconductor layer 132a is formed on the third active layer. Next, as... Figure 3B The N-type fourth semiconductor layer 124 is bonded to the P-type fifth semiconductor layer 132a via bonding layer 140. The result is obtained by removing the first substrate 182 and the second substrate 184. Figure 4 The epitaxial structure of a miniature light-emitting diode 100b. Figure 4 The epitaxial structure 100b and Figure 1 The difference in the epitaxial structure 100a is that the fifth semiconductor layer 132a is doped with P-type and the sixth semiconductor layer 134a is doped with N-type. Depending on different design or process requirements, the formation order of the N-type doped semiconductor layer and the P-type doped semiconductor layer on the first substrate 182 or the second substrate 184 (such as the gallium arsenide substrate, sapphire substrate, etc. mentioned above) can be changed.

[0048] For ease of explanation, Figures 5A-7 The electrodes of the micro LED are omitted, and only the epitaxial structure of the micro LED is shown. Figure 5A This is a cross-sectional schematic diagram of the epitaxial structure of a micro light-emitting diode according to an embodiment of the present invention. Please refer to... Figure 5AIn this embodiment, the epitaxial structure 100c further comprises a semiconductor tunneling layer 160a disposed between the first stack layer 110a and the second stack layer 120, and having a first type doped region 162a, a second type doped region 164a, and a tunneling region 166a between the first type doped region 162a and the second type doped region 164a. In this embodiment, the semiconductor tunneling layer 160a is disposed below the etch stop layer 150, the first type doped region 162a is disposed above the second type doped region 164a, the semiconductor tunneling layer 160a has the same doping type as the second semiconductor layer 122 at the second type doped region 164a, the semiconductor tunneling layer 160a has the same doping type as the second semiconductor layer 114a at the first type doped region 162a, and the doping type of the semiconductor tunneling layer 160a at the first type doped region 162a is opposite to that at the second type doped region 164a. In this embodiment, the first type doped region 162a has a high concentration of N-type doping near the tunneling region 166a, the second type doped region 164a has a high concentration of P-type doping near the tunneling region 166a, and the doping concentration of the semiconductor tunneling layer 160a has a high gradient at the tunneling region 166a. In this embodiment, the first semiconductor layer 112a has a P-type doping, and the second semiconductor layer 114a has an N-type doping. In this embodiment, the etch stop layer 150 is disposed in the N-type doped second semiconductor layer 114a, and the etch stop layer 150 and the first electrode 210 have a good current spreading property. In another embodiment, the semiconductor tunneling layer 160a has a high concentration of N-type and P-type doping, the etch stop layer 150 is disposed in the N-type doped second semiconductor layer 114a, and a chip having a P-type semiconductor layer facing upward has a good current spreading property and increases the yield of the subsequent external connection circuit (not shown) connecting electrodes. As shown in Figure 5B the doping type of each of the first semiconductor layer 112 to the sixth semiconductor layer 134a of the epitaxial structure 100d is opposite to that of each of the first semiconductor layer 112a to the sixth semiconductor layer 134 of the epitaxial structure 100c, and the etch stop layer 150 is disposed in the P-type doped second semiconductor layer 114. In this embodiment, the first type doped region 162b of the semiconductor tunneling layer 160b has a high concentration of P-type doping near the tunneling region 166b, the second type doped region 164b has a high concentration of N-type doping near the tunneling region 166b, and the doping concentration of the semiconductor tunneling layer 160b has a high gradient at the tunneling region 166b.

[0049] Figure 6A is a cross-sectional view of an epitaxial structure of a micro light emitting diode according to an embodiment of the present application. Please refer to Figure 6A the epitaxial structure 100e of this embodiment and Figure 5AThe micro light emitting diode 100c is similar to the micro light emitting diode 100b, except that in the present embodiment, the epitaxial structure 100e further comprises a first Bragg reflector 172 disposed between the first active layer 116 and the second active layer 126, and a second Bragg reflector 174 disposed between the second active layer 126 and the third active layer 136. The first Bragg reflector 172 is disposed below the semiconductor tunneling layer 160a, and the second Bragg reflector 174 is disposed above the bonding layer 140, for example, in the present embodiment. In one embodiment, as shown in FIG. 1C, the first Bragg reflector 172 is disposed below the semiconductor tunneling layer 160a, and the second Bragg reflector 174 is disposed above the bonding layer 140. In another embodiment, as shown in FIG. 1D, the first Bragg reflector 172 is disposed above the semiconductor tunneling layer 160a, and the second Bragg reflector 174 is disposed below the bonding layer 140. Figure 6B or Figure 6C The first stack layer 110a, the second stack layer 120, and the third stack layer 130 of the epitaxial structure 100f can not completely overlap in the light emitting area. Here, the third stack layer 130 of red light has the lowest efficiency, so the largest light emitting area is configured, and the misalignment can be directly on the surface to make electrodes (such as the first electrode 210, the second electrode 220, and the third electrode 230) without the need for further holes (the electrode configuration is not repeated in the other figures), and the Bragg reflectors (such as the first Bragg reflector 172 and the second Bragg reflector 174) between the stack layers ensure light emission, which can have better manufacturing yield and light emitting efficiency. In an embodiment not shown, the light emitting areas can be equal but misaligned with each other. As shown in FIG. 1F, the first Bragg reflector 172 of the epitaxial structure 100f is disposed above the semiconductor tunneling layer 160a, and the second Bragg reflector 174 is disposed below the bonding layer 140. The configuration relationship is adjusted by the adaptability of the Bragg reflector material and the epitaxial structure, such as the Bragg reflector and the etching stop layer 150 of the same material, which are both gallium nitride. The multi-layer Bragg reflector is formed before the single-layer etching stop layer 150, which can increase the epitaxial yield. Figure 6B

[0050] In another embodiment, as shown in FIG. 1G, the first stack layer 110a is disposed above the third stack layer 130, and the second stack layer 120 is disposed above the third stack layer 130. At least one etching stop layer 150 (two etching stop layers 150 are taken as an example in FIG. 1G) is disposed between the first stack layer 110a and the third stack layer 130 or between the second stack layer 120 and the third stack layer 130. A plurality of electrodes (such as the first electrode 210, the second electrode 220, the third electrode 230, and the fourth electrode 240) are electrically connected to the first stack layer 110a, the second stack layer 120, and the third stack layer 130, respectively, wherein at least one electrode (such as the second electrode 220 and the third electrode 230) contacts the etching stop layer. Figure 6D Figure 6D

[0051] Figure 7 ​​​is a cross-sectional schematic view of an epitaxial structure of a micro light emitting diode according to an embodiment of the present application. Please refer to Figure 7 The epitaxial structure 100g of the present embodiment is similar to the epitaxial structure 100e of the above embodiment, except that the first Bragg reflection layer 172 is the etching stop layer 150 in the present embodiment. That is, the etching stop layer 150d (172) of the present embodiment is arranged in the form of a Bragg reflection layer below the semiconductor tunneling layer 160a, which can increase the efficiency of epitaxy. Figure 6A

[0052] In the embodiments of the present application, the materials of the first Bragg reflection layer 172 and the second Bragg reflection layer 174 are, for example, aluminum indium nitride (AlInN), gallium nitride, etc., but are not limited thereto. By arranging the Bragg reflection layers between the first active layer 116 and the second active layer 126, and between the second active layer 126 and the third active layer 136 in these embodiments, the Bragg reflection layers can achieve the effect of a long pass filter, reflecting light of a specific wavelength (for example, the arrangement of the first Bragg reflection layer 172 can allow the light emitted by the third active layer and the second active layer to pass through, and reflect the light emitted by the first active layer. The arrangement of the second Bragg reflection layer 174 can allow the light emitted by the third active layer to pass through, and reflect the light emitted by the first active layer and the second active layer. This can increase the light emission efficiency. Figures 6A-7

[0053] is a cross-sectional schematic view of a micro light emitting diode according to an embodiment of the present application. Please refer to Figure 8 The micro light emitting diode 10b of the present embodiment is similar to the micro light emitting diode 10a of the above embodiment, except that the first Bragg reflection layer 172 is the etching stop layer 150 in the present embodiment. That is, the etching stop layer 150d (172) of the present embodiment is arranged in the form of a Bragg reflection layer below the semiconductor tunneling layer 160a, which can increase the efficiency of epitaxy. Figure 8 Figure 1 ​​The micro light emitting diode 10a is similar to the micro light emitting diode 10a except that in the present embodiment, the at least one etch stop layer is a plurality of etch stop layers 150 disposed above the first active layer 116, between the first active layer 116 and the second active layer 126, and between the second active layer 126 and the third active layer 136 (e.g. between the bonding layer 140 and the third main layer 136), respectively, with the partial electrodes 200 contacting the etch stop layers 150, respectively. For example, in the present embodiment, the plurality of etch stop layers 150 are disposed in the first semiconductor layer 112, between the second semiconductor layer 114 and the third semiconductor layer 122, and in the fifth semiconductor layer 132. In the present embodiment, the second via hole 194 exposes the lower surface of the etch stop layer 150 in the fifth semiconductor layer 132, and the insulating layer 300 exposes the lower surface of the etch stop layer 150 in the fifth semiconductor layer 132. The fourth via hole 198 exposes the lower surface of the etch stop layer 150 in the first semiconductor layer 112, and the insulating layer 300 exposes the lower surface of the etch stop layer 150 in the first semiconductor layer 112. The second electrode 220 contacts the etch stop layer 150 at the surface exposed by the insulating layer 300, and is electrically connected to the fifth semiconductor layer 132 (N-type doped in the present embodiment). The fourth electrode 240 contacts the etch stop layer 150 at the surface exposed by the insulating layer 300, and is electrically connected to the first semiconductor layer 112 (N-type doped in the present embodiment). When the etch stop layer is disposed corresponding to the via hole formed in the micro light emitting diode, over-etching is avoided, and the active layers are not damaged.

[0054] Figure 9 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. Please refer to Figure 9 In the present embodiment, the epitaxial structure 100i of the micro light emitting diode 10c is similar to the epitaxial structure 100a of the micro light emitting diode 10a except that in the present embodiment, the at least one etch stop layer is a plurality of etch stop layers 150 disposed above the first active layer 116, between the first active layer 116 and the second active layer 126, and between the second active layer 126 and the third active layer 136 (e.g. between the bonding layer 140 and the third main layer 136), respectively, with the partial electrodes 200 contacting the etch stop layers 150, respectively. For example, in the present embodiment, the plurality of etch stop layers 150 are disposed in the first semiconductor layer 112, between the second semiconductor layer 114 and the third semiconductor layer 122, and in the fifth semiconductor layer 132. In the present embodiment, the second via hole 194 exposes the lower surface of the etch stop layer 150 in the fifth semiconductor layer 132, and the insulating layer 300 exposes the lower surface of the etch stop layer 150 in the fifth semiconductor layer 132. The fourth via hole 198 exposes the lower surface of the etch stop layer 150 in the first semiconductor layer 112, and the insulating layer 300 exposes the lower surface of the etch stop layer 150 in the first semiconductor layer 112. The second electrode 220 contacts the etch stop layer 150 at the surface exposed by the insulating layer 300, and is electrically connected to the fifth semiconductor layer 132 (N-type doped in the present embodiment). The fourth electrode 240 contacts the etch stop layer 150 at the surface exposed by the insulating layer 300, and is electrically connected to the first semiconductor layer 112 (N-type doped in the present embodiment). When the etch stop layer is disposed corresponding to the via hole formed in the micro light emitting diode, over-etching is avoided, and the active layers are not damaged. Figure 5Aepitaxial structure 100i, the difference is that the epitaxial structure 100i includes two etching stop layers 150, which are disposed in the N-type third semiconductor layer 122a and the N-type sixth semiconductor layer 134a, respectively. In this embodiment, the material of the bonding layer 140a is a non-conductor, such as an oxide, for example, silicon dioxide (SiO2), but is not limited to this. In this embodiment, the first electrode 210a is a shared positive electrode, and the first electrode 210a is connected to the P-type fourth semiconductor layer 124a and the P-type fifth semiconductor layer 132a from the side. The insulating layer 300 has a through hole (corresponding to the second through hole 220a) that exposes part of the upper surface of the N-type first semiconductor layer 112, and the second electrode 220a is partially located in the through hole and is electrically connected to the N-type first semiconductor layer 112 as the negative electrode of the first epitaxial structure 110. The first through hole (corresponding to the third electrode 230a) penetrates the first semiconductor layer 112, the first active layer 116, the second semiconductor layer 114, and the semiconductor tunneling layer 160b, and the first through hole exposes part of the upper surface of the etching stop layer 150 in the third semiconductor layer 122a, and the third electrode 230a is partially located in the first through hole and is electrically connected to the etching stop layer 150 as the negative electrode of the second epitaxial structure 120a. The second through hole (corresponding to the fourth electrode 240a) penetrates the first semiconductor layer 112, the first active layer 116, the second semiconductor layer 114, the semiconductor tunneling layer 160b, the etching stop layer 150, the third semiconductor layer 122a, the second active layer 126, the fourth semiconductor layer 124a, the bonding layer 140a, the fifth semiconductor layer 132a, and the third active layer 136, and the second through hole exposes part of the upper surface of the etching stop layer 150 in the sixth semiconductor layer 134a, and the fourth electrode 240a is partially located in the second through hole and is electrically connected to the etching stop layer 150 as the negative electrode of the third epitaxial structure 130a. Here, the micro light emitting diode 10d is, for example, a horizontal micro light emitting diode.

[0055] Figure 10 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. Please refer to Figure 10 In this embodiment, the micro light emitting diode 10d is similar to Figure 9The difference between the micro-LED 10c and the previous one lies in the different electrode types and the different positions of the etch-stop layers. In this embodiment, the epitaxial structure 100j includes three etch-stop layers 150, which are respectively disposed in the second semiconductor layer 114 (P-type), the fourth semiconductor layer 124a (P-type), and the fifth semiconductor layer 132a (P-type). The first electrode 210b is a shared negative electrode. The first electrode 210b is electrically connected to the sixth semiconductor layer 134a (N-type) from the side and extends along the side of the epitaxial structure 100j and is electrically connected to the first semiconductor layer 112 (N-type). The first via (corresponding to the second electrode 220b) passes through the first semiconductor layer 112 and the first active layer 116. The first via exposes a portion of the upper surface of the etch-stop layer 150 disposed in the second semiconductor layer 114. The second electrode 220b is partially located in the first via and is electrically connected to the etch-stop layer 150, serving as the positive electrode of the first epitaxial structure 110. The second via (corresponding to the third electrode 230b) passes through the first semiconductor layer 112, the first active layer 116, the second semiconductor layer 114, the semiconductor tunneling layer 160b, the etch stop layer 150, the third semiconductor layer 122a, and the second active layer 126. The second via exposes a portion of the upper surface of the etch stop layer 150 disposed in the fourth semiconductor layer 124a. The third electrode 230b is partially located in the second via and is electrically connected to the etch stop layer 150, serving as the positive electrode of the second epitaxial structure 120a. The third via (corresponding to the fourth electrode 240b) passes through the first semiconductor layer 112, the first active layer 116, the second semiconductor layer 114, the semiconductor tunneling layer 160b, the etch stop layer 150, the third semiconductor layer 122a, the second active layer 126, the fourth semiconductor layer 124a, and the bonding layer 140a. The third via exposes a portion of the upper surface of the etch stop layer 150 disposed in the fifth semiconductor layer 132a. The fourth electrode 240b is partially located in the third via and electrically connected to the etch stop layer 150, serving as the positive electrode of the third epitaxial structure 130a. Here, the micro-LED 10d is, for example, a flip-chip or horizontal micro-LED, and the electrodes of equal height can achieve better yield during subsequent transfer.

[0056] Figure 11 This is a cross-sectional schematic diagram of a miniature light-emitting diode according to an embodiment of the present invention. Please refer to... Figure 11 In this embodiment, the miniature light-emitting diode 10e is similar to Figure 10The micro light emitting diode 10d is similar to the micro light emitting diode 10c except that the type of the negative electrode is different and the number of the etching stop layers is different. In this embodiment, the epitaxial structure 100k includes a fourth etching stop layer 150 disposed in the first semiconductor layer 112 in addition to the three etching stop layers 150 of the epitaxial structure 100j. In this embodiment, a fourth via hole (corresponding to the first electrode 210c) passes through the first active layer 116, the second semiconductor layer 114, the semiconductor tunneling layer 160b, the etching stop layer 150, the third semiconductor layer 122a, the second active layer 126, the fourth semiconductor layer 124a, the bonding layer 140a, the fifth semiconductor layer 132a, the third active layer 136, and the sixth semiconductor layer 134a, exposing a portion of the lower surface of the etching stop layer 150 disposed in the first semiconductor layer 112, and the first electrode 210c is partially located in the fourth via hole and electrically connected to the etching stop layer 150 as a shared negative electrode of the first epitaxial structure 110, the second epitaxial structure 120a, and the third epitaxial structure 130a. The portion of the first electrode 210c away from the etching stop layer 150 extends along the bottom surface of the sixth semiconductor layer 134a. The micro light emitting diode 10d, for example, is a vertical micro light emitting diode that can increase the arrangement density during subsequent transfer and can be applied to devices requiring high resolution, such as augmented reality (AR) / virtual reality (VR).

[0057] Figure 12 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. Please refer to Figure 12 In this embodiment, the micro light emitting diode 10f is similar to the micro light emitting diode 10c except that the type of the negative electrode is different and the number of the etching stop layers is different. Figure 10 The micro light emitting diode 10d is similar to the micro light emitting diode 10c except that the type of the negative electrode is different and the number of the etching stop layers is different. In this embodiment, the epitaxial structure 100k includes a fourth etching stop layer 150 disposed in the first semiconductor layer 112 in addition to the three etching stop layers 150 of the epitaxial structure 100j. In this embodiment, a fourth via hole (corresponding to the first electrode 210c) passes through the first active layer 116, the second semiconductor layer 114, the semiconductor tunneling layer 160b, the etching stop layer 150, the third semiconductor layer 122a, the second active layer 126, the fourth semiconductor layer 124a, the bonding layer 140a, the fifth semiconductor layer 132a, the third active layer 136, and the sixth semiconductor layer 134a, exposing a portion of the lower surface of the etching stop layer 150 disposed in the first semiconductor layer 112, and the first electrode 210c is partially located in the fourth via hole and electrically connected to the etching stop layer 150 as a shared negative electrode of the first epitaxial structure 110, the second epitaxial structure 120a, and the third epitaxial structure 130a. The portion of the first electrode 210c away from the etching stop layer 150 extends along the bottom surface of the sixth semiconductor layer 134a. The micro light emitting diode 10d, for example, is a vertical micro light emitting diode that can increase the arrangement density during subsequent transfer and can be applied to devices requiring high resolution, such as augmented reality (AR) / virtual reality (VR). The micro light emitting diode 10d is similar to the micro light emitting diode 10c except that the type of the negative electrode is different and the number of the etching stop layers is different. In this embodiment, the epitaxial structure 100k includes a fourth etching stop layer 150 disposed in the first semiconductor layer 112 in addition to the three etching stop layers 150 of the epitaxial structure 100j. In this embodiment, a fourth via hole (corresponding to the first electrode 210c) passes through the first active layer 116, the second semiconductor layer 114, the semiconductor tunneling layer 160b, the etching stop layer 150, the third semiconductor layer 122a, the second active layer 126, the fourth semiconductor layer 124a, the bonding layer 140a, the fifth semiconductor layer 132a, the third active layer 136, and the sixth semiconductor layer 134a, exposing a portion of the lower surface of the etching stop layer 150 disposed in the first semiconductor layer 112, and the first electrode 210c is partially located in the fourth via hole and electrically connected to the etching stop layer 150 as a shared negative electrode of the first epitaxial structure 110, the second epitaxial structure 120a, and the third epitaxial structure 130a. The portion of the first electrode 210c away from the etching stop layer 150 extends along the bottom surface of the sixth semiconductor layer 134a. The micro light emitting diode 10d, for example, is a vertical micro light emitting diode that can increase the arrangement density during subsequent transfer and can be applied to devices requiring high resolution, such as augmented reality (AR) / virtual reality (VR).

[0058] In this embodiment, the first via (corresponding to the second electrode 220c) passes through the second active layer 126, the fourth semiconductor layer 124, the bonding layer 140b, the fifth semiconductor layer 132a, the third active layer 136, and the sixth semiconductor layer 134a, exposes a portion of the lower surface of the etching stop layer 150 disposed in the third semiconductor layer 122, and the second electrode 220c is partially located in the first via and electrically connected to the etching stop layer 150 as the positive electrode of the second epitaxial structure 120. The second via (corresponding to the third electrode 230c) passes through the first active layer 116, the second semiconductor layer 114a, the semiconductor tunneling layer 160a, the etching stop layer 150, the third semiconductor layer 122, the second active layer 126, the fourth semiconductor layer 124, the bonding layer 140b, the fifth semiconductor layer 132a, the third active layer 136, and the sixth semiconductor layer 134a, exposes a portion of the lower surface of the etching stop layer 150 disposed in the first semiconductor layer 112a, and the third electrode 230c is partially located in the second via and electrically connected to the etching stop layer 150 as the positive electrode of the first epitaxial structure 110a. The third via (corresponding to the fourth electrode 240c) passes through the third active layer 136 and the sixth semiconductor layer 134a, exposes a portion of the lower surface of the etching stop layer 150 disposed in the fifth semiconductor layer 132a, and the fourth electrode 240c is partially located in the third via and electrically connected to the etching stop layer 150 as the positive electrode of the third epitaxial structure 130a. Here, the micro LED 10d is, for example, a flip-chip micro LED, which can have a better yield and be easier to repair in subsequent transfer through the same height electrodes.

[0059] Figure 13 is a cross-sectional view of a micro LED according to an embodiment of the present application. Please refer to Figure 13 In this embodiment, the micro LED 10g is similar to the micro LED 10f of Figure 12 , except that the electrode types are different, and the doping types of the layers of the second epitaxial structure 130 are opposite to those of the layers of the third epitaxial structure 130a. In this embodiment, the first via and the second via corresponding to the second electrode 220c and the third electrode 230c in the micro LED 10f of Figure 12 are retained, and the insulating layer 300 has a via (corresponding to the fourth electrode 240d) exposing a portion of the lower surface of the sixth semiconductor layer 134, the fourth electrode 240d is partially located in the via, and electrically connected to the sixth semiconductor layer 134 as the positive electrode of the third epitaxial structure 130. The insulating layer 300 has a cross section exposing a portion of the upper surface of the bonding layer 140b, the first electrode 210e is disposed on the bonding layer 140b, and electrically connected to the fourth semiconductor layer 124 and the fifth semiconductor layer 132 through the bonding layer 140b.

[0060] Figures 14A-14C is a flow chart of manufacturing a micro light emitting diode according to an embodiment of the present application. Figure 14D is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. Figure 14E is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. Please refer to Figure 14A In this embodiment, an adhesive layer 142 is disposed on the fourth semiconductor layer 124 and the fifth semiconductor layer 132, the adhesive layer 142 has a groove, and a metal bump 144 is disposed in the groove. Please refer to Figure 14B The adhesive layer on the fourth semiconductor layer 124 and the adhesive layer 142 on the fifth semiconductor layer 132 are connected. Please refer to Figure 14C The metal bump 144 on the fourth semiconductor layer 124 and the metal bump 144 on the fifth semiconductor layer 132 are heated to contact each other, and a bonding layer 140c is formed. By disposing the metal bump 144 in the groove, overflow of the metal bump 144 after heating can be reduced. Please refer to Figure 14D The bonding layer 140d of this embodiment is formed in a flow chart of Figures 14A-14C , in which the metal bump 144 on the fourth semiconductor layer 124 and the metal bump 144 on the fifth semiconductor layer 132 are staggered. Please refer to Figure 14E The bonding layer 140e of this embodiment is formed in a flow chart of Figures 14A-14C , in which the metal bump 144 on the fourth semiconductor layer 124 and the metal bump 144 on the fifth semiconductor layer 132 are respectively close to two side surfaces of the epitaxial structure. In the above embodiments, the material of the adhesive layer 142 is an insulating material, for example, an oxide such as silicon dioxide, but is not limited thereto. The material of the metal bump 144 is a conductive material, for example, copper, gold, aluminum, or the like, but is not limited thereto. The bonding layer 140 includes the insulating adhesive layer 142 as a bonding function and the conductive metal bump 144 as a conductive function, and can achieve both adhesion and conduction, thereby increasing the yield of chip manufacturing.

[0061] Figure 15A and Figure 15B is a flow chart of manufacturing a micro light emitting diode according to an embodiment of the present application. Figure 15C is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. Please refer to Figure 15A In this embodiment, a metal bump 144 is disposed on the fourth semiconductor layer 124 and the fifth semiconductor layer 132, and an anisotropic conductive film 146 is disposed on at least one of the fourth semiconductor layer 124 and the fifth semiconductor layer 132, the metal bump 144 on the fourth semiconductor layer 124 and the metal bump 144 on the fifth semiconductor layer 132 are connected, and a bonding layer 140f is formed, as shown inFigure 15B In the embodiment shown in Figure 15A , the anisotropic conductive paste is only patterned on the metal bumps 144, and a transparent oxide layer 148 is disposed on at least one of the fourth semiconductor layer 124 and the fifth semiconductor layer 132, and the metal bump 144 on the fourth semiconductor layer 124 and the metal bump 144 on the fifth semiconductor layer 132 are connected to form Figure 15C a bonding layer 140g (anisotropic conductive paste between the metal bump 144 on the fourth semiconductor layer 124 and the metal bump 144 on the fifth semiconductor layer 132 after connection). The transparent oxide layer 148 can serve as adhesion while increasing light extraction efficiency.

[0062] Figure 16 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. The micro light emitting diode 10h of the present embodiment is similar to the micro light emitting diode 10a of Figure 1 the difference being that the type of the bonding layer 140d is different, and the connection positions of the second electrode 220 and the third electrode 230 are different. In addition, a second etching stop layer 150 is disposed in the first semiconductor layer 112, the insulating layer 300 exposes part of the lower surface of the etching stop layer 150, and the fourth electrode 240 contacts the part of the etching stop layer 150 exposed by the insulating layer 300. In the present embodiment, the surface of the second electrode 220 exposed by the insulating layer 300 contacts the metal bump 144 disposed on the fifth semiconductor layer 132, and electrically connects the fifth semiconductor layer 132 through the metal bump 144. The surface of the third electrode 230 exposed by the insulating layer 300 contacts the metal bump 144 disposed on the fourth semiconductor layer 124, and electrically connects the fourth semiconductor layer 124 through the metal bump 144. In addition, the first electrode 210 is electrically connected to the sixth semiconductor layer 134 and the etching stop layer 150.

[0063] Figure 17 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. The micro light emitting diode 10h of the present embodiment is similar to the micro light emitting diode 10a of Figure 16The micro light emitting diode 10h differs from the micro light emitting diode 10g in the type of the bonding layer 140e and the connection position and type of the second electrode 220d and the third electrode 230d. In this embodiment, the second electrode 220d contacts the metal bump 144 disposed on the fifth semiconductor layer 132 and electrically connects the fifth semiconductor layer 132 through the metal bump 144, and the second electrode 220d extends to cover part of the side surface and part of the bottom surface of the micro light emitting diode 10h. The third electrode 230d is disposed opposite to the second electrode 220d, the third electrode 230d contacts the metal bump 144 disposed on the fourth semiconductor layer 124 and electrically connects the fourth semiconductor layer 124 through the metal bump 144, and the third electrode 230d extends to cover part of the side surface and part of the bottom surface of the micro light emitting diode 10h.

[0064] Figure 18 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. In Figure 18In the micro light emitting diode 10j, etching stop layers 150 are respectively disposed in the N-type second semiconductor layer 114a and the N-type third semiconductor layer 122a, the P-type fourth semiconductor layer 124a, and the N-type sixth semiconductor layer 134a. A semiconductor tunneling layer 160a is disposed on the P-type first semiconductor layer 112a. In this embodiment, a first via (corresponding to the portion of the first electrode 210f near the side edge of the micro light emitting diode 10j) passes through the semiconductor tunneling layer 160a, the first semiconductor layer 112a, and the first active layer 116, and a second via (corresponding to the portion of the first electrode 210f near the center of the micro light emitting diode 10j) passes through the semiconductor tunneling layer 160a, the first semiconductor layer 112a, and the first active layer 116, the second semiconductor layer 114a, the etching stop layer 150, the second active layer 126, the bonding layer 140, the fifth semiconductor layer 132a, and the third active layer 136. The first via exposes the upper surface of the portion of the etching stop layer 150 disposed in the second semiconductor layer 114a and the third semiconductor layer 122a, and the second via exposes the upper surface of the portion of the etching stop layer 150 disposed in the sixth semiconductor layer 134a. The first electrode 210f is partially in the first via and partially in the second via, and electrically connects the two etching stop layers 150 as a shared negative electrode. The semiconductor tunneling layer 160a has a third via (corresponding to the second electrode 220e) on it, and the second electrode 220e is partially in the third via and electrically connected to the first semiconductor layer 112a (e.g., through the semiconductor tunneling layer 160a) as a positive electrode. A fourth via (corresponding to the third electrode 230e) passes through the semiconductor tunneling layer 160a, the first semiconductor layer 112a, the first active layer 116, the second semiconductor layer 114a, the etching stop layer 150, the second active layer 126, and the bonding layer 140, and the third electrode 230e is partially in the fourth via and electrically connected to the fifth semiconductor layer 132a as a positive electrode. A fifth via (corresponding to the fourth electrode 240e) passes through the semiconductor tunneling layer 160a, the first semiconductor layer 112a, and the first active layer 116, the second semiconductor layer 114a, the etching stop layer 150, and the second active layer 126, and the fourth electrode 240e is partially in the fifth via and electrically connected to the fourth semiconductor layer 124a as a positive electrode.

[0065] Figure 19 is a cross-sectional view of a micro light emitting diode according to an embodiment of the present application. In Figure 19In the micro light emitting diode 10k, the micro light emitting diode includes a first stack layer 110, a second stack layer 120, a third stack layer 130, at least one etching stop layer 150, and a plurality of electrodes 200. The first stack layer 110, the second stack layer 120, and the third stack layer 130 are semiconductor light emitting stack layers of three different light emitting colors. The first stack layer 110 is disposed above the third stack layer 130, and the second stack layer 120 is disposed between the first stack layer 110 and the third stack layer 130. The at least one etching stop layer 150 is disposed at least between the first stack layer 110 and the second stack layer 120 or at least between the second stack layer 120 and the third stack layer 130. The plurality of electrodes 200 are electrically connected to the first stack layer 110, the second stack layer 120, and the third stack layer 130, respectively, and at least one electrode 200 contacts the etching stop layer 150. In an embodiment, the interval of the active layers (for example, the interval of the first active layer 116 and the second active layer 126 and the interval of the second active layer 126 and the third active layer 136) is less than 1 micrometer, and thus the active layers can be effectively prevented from being over-etched by the etching stop layer 150. In this embodiment, the epitaxial materials of the first stack layer 110, the second stack layer 120, and the third stack layer 130 are, for example, compounds selected from the nitride semiconductor system, and the composition includes Al x In y Ga z N, but not limited thereto. That is, the first stack layer 110, the second stack layer 120, and the third stack layer 130 can be stacked in the same epitaxial process. In this embodiment, the first stack layer 110 can emit blue light, the second stack layer 120 can emit green light, and the third stack layer 130 can emit red light. The micro light emitting diodes 10h, 10i, 10j, and 10k described above are, for example, flip-chip micro light emitting diodes.

[0066] In summary, the micro light emitting diode of the present application can increase the space utilization of the display panel because three light emitting diode chips are disposed in a vertical stack. In the case where the pixel size of the display panel does not change, the space utilization and the display effect of the display panel can be increased, and the conversion efficiency problem of chip miniaturization can be avoided. In addition, because the at least one etching stop layer is disposed at least between the first active layer and the second active layer, and the at least one electrode contacts the etching stop layer, over-etching can be avoided in the process of forming the electrodes.

[0067] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A micro light emitting diode, characterized by, Comprising: An epitaxial structure, comprising: A first stack layer, comprising a first semiconductor layer, a second semiconductor layer, and a first active layer disposed between the first semiconductor layer and the second semiconductor layer; A second stack layer, comprising a third semiconductor layer, a fourth semiconductor layer, and a second active layer disposed between the third semiconductor layer and the fourth semiconductor layer; A third stack layer, comprising a fifth semiconductor layer, a sixth semiconductor layer, and a third active layer disposed between the fifth semiconductor layer and the sixth semiconductor layer, the first stack layer disposed above the third stack layer, the second stack layer disposed between the first stack layer and the third stack layer, wherein the first stack layer, the second stack layer, and the third stack layer are semiconductor light emitting stack layers of three different light emitting colors; A bonding layer disposed between the second stack layer and the third stack layer; and At least one etch stop layer disposed at least between the first active layer and the second active layer and relatively far away from the first semiconductor layer and the fourth semiconductor layer; and A plurality of electrodes electrically connected to the first stack layer, the second stack layer, and the third stack layer, respectively, wherein at least one electrode contacts the etch stop layer, wherein the etch stop layer contacts the second semiconductor layer and the third semiconductor layer.

2. The micro light emitting diode of claim 1, wherein, The epitaxial structure has a via hole through the second stack layer, the bonding layer, and the third stack layer, the via hole exposing a portion of a lower surface of the etch stop layer, wherein the at least one electrode is configured in the via hole to contact the etch stop layer.

3. The micro light emitting diode of claim 1, wherein, The at least one etch stop layer comprises a compound having a different elemental ratio than a compound comprising the second semiconductor layer or the third semiconductor layer.

4. The micro light emitting diode of claim 1, wherein, The at least one etch stop layer comprises a compound different from a compound comprising the second semiconductor layer or the third semiconductor layer.

5. The micro light emitting diode of claim 1, wherein, The at least one etch stop layer has a different doping concentration than a doping concentration of the second semiconductor layer or the third semiconductor layer.

6. The micro light emitting diode of claim 1, wherein, The at least one etch stop layer comprises two or more doping elements.

7. The micro light emitting diode of claim 1, wherein, The at least one etch stop layer has a different doping element than a doping element of the second semiconductor layer or the third semiconductor layer.

8. The micro light emitting diode of claim 1, wherein, The at least one etch stop layer is a plurality of etch stop layers disposed above the first active layer, between the first active layer and the second active layer, and between the second active layer and the third active layer, respectively, wherein part of the plurality of electrodes respectively contacts the plurality of etch stop layers.

9. The micro light emitting diode of claim 1, wherein, Further comprising a semiconductor tunneling layer disposed between the first stack layer and the second stack layer and having a first type doped region, a second type doped region, and a tunneling region between the first type doped region and the second type doped region.

10. The micro light emitting diode of claim 1, wherein, Further comprising a first Bragg reflection layer disposed between the first active layer and the second active layer and a second Bragg reflection layer disposed between the second active layer and the third active layer.

11. The micro light emitting diode of claim 10, wherein, The first Bragg reflector layer is the at least one etch stop layer.

12. The micro light emitting diode of claim 1, wherein, The bonding layer includes a conductive region.

13. The micro light emitting diode of claim 1, wherein, The third stack layer is different in material system from the first stack layer, and is different in material system from the second stack layer.

14. The micro light emitting diode of claim 13, wherein, The first and second stack layers are selected from compounds in III-V nitride semiconductors, and the third stack layer is selected from compounds in phosphide or arsenide semiconductors.

15. A micro light emitting diode, comprising: Comprising: a first stack layer; a second stack layer; a third stack layer, wherein the first, second, and third stack layers are semiconductor light emitting stack layers of three different light emitting colors, the first stack layer is disposed above the third stack layer, and the second stack layer is disposed between the first and third stack layers; at least one etch stop layer disposed between at least the first and second stack layers or between at least the second and third stack layers; and a plurality of electrodes electrically connected to the first, second, and third stack layers, respectively, wherein at least one electrode contacts the etch stop layer, wherein the etch stop layer contacts the first and second stack layers. Comprising:

16. A micro light emitting diode, comprising: a first stack layer; a second stack layer; a third stack layer, wherein the first, second, and third stack layers are semiconductor light emitting stack layers of three different light emitting colors, the first stack layer is disposed above the third stack layer, and the second stack layer is disposed above the third stack layer; at least one etch stop layer disposed between at least the first and third stack layers or between at least the second and third stack layers; and a plurality of electrodes electrically connected to the first, second, and third stack layers, respectively, wherein at least one electrode contacts the etch stop layer, wherein the etch stop layer contacts the first and second stack layers. ​ ​

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