Cameras and electronic equipment

Abstract

According to one embodiment of the present invention, an imaging device is provided with: a first semiconductor substrate, the first semiconductor substrate having a first surface and a second surface, and also including sensor pixels that perform photoelectric conversion; a second semiconductor substrate, the second semiconductor substrate having a third surface and a fourth surface, and also including a readout circuit, the readout circuit outputting pixel signals based on the charge output from the sensor pixels, and the second semiconductor substrate is stacked on the first semiconductor substrate so that the third surface and the first surface are opposite to each other; and a wiring layer, the wiring layer is arranged between the first semiconductor substrate and the second semiconductor substrate, and includes a first wiring and a second wiring electrically connected to each other, one of the first wiring and the second wiring is in an electrically floating state and the other is electrically connected to a transistor arranged on the first or second semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to an imaging device having a three-dimensional structure and an electronic device including the imaging device. Background Art

[0002] The introduction of miniaturization processes and increased packaging density have led to a reduction in the area of ​​a single pixel in two-dimensional imaging devices. In recent years, to achieve even smaller imaging devices and higher pixel density, three-dimensional imaging devices have been developed. In three-dimensional imaging devices, for example, a semiconductor substrate including multiple sensor pixels and a semiconductor substrate including a signal processing circuit are stacked (see, for example, Patent Document 1). The signal processing circuit processes the signal obtained by each sensor pixel.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2014-22561 Summary of the Invention

[0006] In addition, an image pickup device having a three-dimensional structure is expected to have an expanded dynamic range.

[0007] It is desirable to provide an imaging device and an electronic device capable of expanding the dynamic range.

[0008] According to an embodiment of the present invention, an imaging device includes: a first semiconductor substrate; a second semiconductor substrate; and a wiring layer. The first semiconductor substrate has a first surface and a second surface and includes sensor pixels that perform photoelectric conversion. The second semiconductor substrate has a third surface and a fourth surface and includes a readout circuit that outputs pixel signals based on the charge output from the sensor pixels. The second semiconductor substrate is stacked on the first semiconductor substrate, and the first surface and the fourth surface face each other. The wiring layer is provided between the first semiconductor substrate and the second semiconductor substrate and includes a first wiring and a second wiring electrically connected to each other. One of the first wiring and the second wiring is in an electrically floating state, while the other of the first wiring and the second wiring is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate.

[0009] An electronic device according to an embodiment of the present disclosure includes the imaging device according to the embodiment of the present disclosure described above.

[0010] In an imaging device according to an embodiment of the present disclosure and an electronic device according to an embodiment, the first wiring and the second wiring are arranged within the wiring layer, and the wiring layer is formed on respective opposing surfaces of a first semiconductor substrate including the pixel sensor and a second semiconductor substrate including the readout circuit. This increases wiring capacitance. One of the first wiring and the second wiring is in an electrically floating state. The other of the first wiring and the second wiring is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate. The first wiring and the second wiring are electrically connected to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 : is a schematic cross-sectional view showing the configuration of the image pickup device according to the first embodiment of the present disclosure in the vertical direction.

[0012] Figure 2 It shows Figure 1 A diagram showing an example of an equivalent circuit of an imaging device shown.

[0013] Figure 3 It shows Figure 1 FIG. 1 is a diagram showing another example of an equivalent circuit of the imaging device shown.

[0014] Figure 4 It shows Figure 1 FIG. 1 is a schematic diagram showing an example of the layout of gate wiring and lower wiring layers in the first substrate.

[0015] Figure 5 It shows Figure 1 Schematic diagram of an example of the wiring layout of the lower wiring layer and the upper wiring layer in the first substrate shown.

[0016] Figure 6 It shows Figure 1 Schematic diagram of an example of the wiring layout of the upper wiring layer and pad electrodes in the first substrate shown.

[0017] Figure 7 It shows Figure 1 FIG. 1 is a schematic diagram showing an example of the layout of gate wiring and lower wiring layers in the second substrate.

[0018] Figure 8 It shows Figure 1 Schematic diagram of an example of the wiring layout of the lower wiring layer and the first intermediate wiring layer in the second substrate shown.

[0019] Figure 9 It shows Figure 1 FIG. 1 is a schematic diagram showing an example of a wiring layout of the first intermediate wiring layer and the second intermediate wiring layer in the second substrate.

[0020] Figure 10 It shows Figure 1 FIG. 1 is a schematic diagram showing an example of a wiring layout of the second intermediate wiring layer and the upper wiring layer in the second substrate.

[0021] Figure 11 It shows Figure 1 Schematic diagram of an example of the wiring layout of the upper wiring layer and pad electrodes of the second substrate shown.

[0022] Figure 12 is a diagram showing an example of functional blocks of a logic circuit.

[0023] Figure 13 : is a schematic diagram showing an example of a wiring layout of an image pickup device according to Modification 1 of the present disclosure.

[0024] Figure 14 : is a schematic cross-sectional view showing the configuration of an image pickup device according to a second embodiment of the present disclosure in the vertical direction.

[0025] Figure 15 It shows Figure 14 2 is a diagram showing an exploded perspective configuration example of the imaging device shown in .

[0026] Figure 16 It shows Figure 15 A diagram showing an example of the functional blocks of a logic circuit.

[0027] Figure 17 : is a schematic cross-sectional view showing the configuration of an image pickup device according to Modification 2 of the present disclosure in the vertical direction.

[0028] Figure 18 : is a diagram showing an example of a schematic configuration of an imaging system including an imaging device according to any of the first and second embodiments and Modifications 1 and 2 described above.

[0029] Figure 19 It shows Figure 18 A diagram of an example of an imaging process in an imaging system in FIG.

[0030] Figure 20 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0031] Figure 21 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0032] Figure 22 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0033] Figure 23is a block diagram illustrating an example of the functional configuration of a camera head and a camera control unit (CCU). DETAILED DESCRIPTION

[0034] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. The following description provides specific examples of the present disclosure, but the present disclosure is not limited to the following modes. Furthermore, the present disclosure is not limited to the arrangement, dimensions, and dimensional ratios of the components shown in the drawings. It should be noted that the description follows the following order.

[0035] 1. First Embodiment (Example of an Image Capturing Device in Which Additional Capacitor Wiring is Provided in a First Substrate and a Second Substrate)

[0036] 1-1. Schematic Configuration of Image Capture Device

[0037] 1-2. Specific Structure of the Camera Device

[0038] 1-3. Actions and Effects

[0039] 2. Modification 1

[0040] 3. Second Embodiment (Example of Image Pickup Device in Which Three Substrates Are Stacked)

[0041] 4. Modification 2

[0042] 5. Application Examples

[0043] 6. Application Examples

[0044] <1. First embodiment>

[0045] (1-1. Schematic Configuration of Imaging Device)

[0046] Figure 1 An example of a cross-sectional configuration in the vertical direction of the image pickup device (image pickup device 1 ) according to the first embodiment of the present disclosure is schematically shown. Figure 2 Shown Figure 1 An example of an equivalent circuit of the imaging device 1 is shown. Figure 3 Shown Figure 1 Another example of an equivalent circuit of the imaging device 1 is shown. Figures 4 to 6 Each of the Figure 1 An example of a wiring layout of the image pickup device 1 on the first substrate 100 side is shown in FIG. Figures 7 to 11 Each of the Figure 1 An example of a wiring layout of the imaging device 1 on the second substrate 200 side is shown in FIG. Figure 1 The camera device 1 is shown along Figures 4 to 11The image pickup device 1 is a cross-sectional view taken along line II′. The image pickup device 1 includes two substrates (a first substrate 100 and a second substrate 200). The image pickup device 1 has a three-dimensional structure in which the first substrate 100 and the second substrate 200 are stacked.

[0047] The first substrate 100 includes a semiconductor substrate 10 and a wiring layer 30. The semiconductor substrate 10 has a first surface 10A and a second surface 10B that face each other. The wiring layer 30 is provided on the first surface 10A of the semiconductor substrate 10. The second substrate 200 includes a semiconductor substrate 20 and a wiring layer 40. The semiconductor substrate 20 has a first surface 20A and a second surface 20B that face each other. The wiring layer 40 is provided on the first surface 20A of the semiconductor substrate 20. In the imaging device 1, the first substrate 100 and the second substrate 200 are stacked with the wiring layer 30 provided on the first surface 10A of the semiconductor substrate 10 and the wiring layer 40 provided on the first surface 20A of the semiconductor substrate 20 interposed therebetween. The semiconductor substrate 10 corresponds to a specific example of the "first semiconductor substrate" according to the present disclosure. The first surface 10A corresponds to a specific example of the "first surface" according to the present disclosure, and the second surface 10B corresponds to a specific example of the "second surface" according to the present disclosure. The semiconductor substrate 20 corresponds to a specific example of the "second semiconductor substrate" according to the present disclosure. The first surface 20A corresponds to a specific example of the “third surface” according to the present disclosure, and the second surface 20B corresponds to a specific example of the “fourth surface” according to the present disclosure. The wiring layer 30 corresponds to a specific example of the “first wiring layer” according to the present disclosure, and the wiring layer 40 corresponds to a specific example of the “second wiring layer” according to the present disclosure.

[0048] The first substrate 100 includes a plurality of sensor pixels 11 on a semiconductor substrate 10. Each of the plurality of sensor pixels 11 performs photoelectric conversion. Specifically, the first substrate 100 is provided with a transfer transistor TR, a photodiode PD (light-receiving portion 12), a floating diffusion FD, and a VSS contact region 13. The second substrate 200 includes a readout circuit 21 on a semiconductor substrate 20. The readout circuit 21 outputs a pixel signal based on the charge output from the sensor pixels 11. The readout circuit 21 includes, for example, four transistors. Specifically, the readout circuit 21 includes an amplifier transistor AMP, a select transistor SEL, a reset transistor RST, and a conversion efficiency switching transistor FDG.

[0049] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD.

[0050] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the reset transistor RST resets the potential of the floating diffusion FD to the power supply line VDD.

[0051] The selection transistor SEL controls the timing of outputting the pixel signal from the readout circuit 21 .

[0052] The amplifier transistor AMP generates a pixel signal with a voltage corresponding to the charge level held by the floating diffusion FD. The amplifier transistor AMP is included in a source-follower amplifier and outputs a pixel signal with a voltage corresponding to the charge level generated in the photodiode PD. When the select transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to this potential via the vertical signal line VSL to the logic circuit 25 (described later).

[0053] The conversion efficiency switching transistor FDG is used to change the gain of the charge-voltage conversion performed by the floating diffusion FD. Generally, the pixel signal is small when shooting in a dark place (low illumination). In the case of charge-voltage conversion based on Q=CV, the floating diffusion FD with a larger capacitance (FD capacitance C) results in a smaller V obtained when converted to voltage by the amplifier transistor. At the same time, bright places (high illumination) provide a larger pixel signal. Therefore, unless the FD capacitance C is large, it is impossible for the floating diffusion FD to receive the charge of the photodiode PD. In addition, when converted to voltage by the amplifier transistor AMP, the FD capacitance C must be large to prevent V from being too large (i.e., making V smaller). If these are taken into consideration, when the conversion efficiency switching transistor FDG is turned on, the diffusion layer capacitance or the diffusion layer capacitance and wiring capacitance of the conversion efficiency switching transistor FDG increase. This increases the entire FD capacitance C. At the same time, when the conversion efficiency switching transistor FDG is turned off, the entire FD capacitance C becomes smaller. In this way, switching the conversion efficiency switching transistor FDG on and off makes the FD capacitance C variable. This makes it possible to switch the conversion efficiency.

[0054] For example, in the imaging device 1, a plurality of sensor pixels 11 are repeatedly arranged in an array in a pixel region 110 on a first substrate 100 (see, for example, FIG. Figure 15 ). Specifically, a pixel sharing unit 111 including a plurality of sensor pixels 11 is used as a repetitive unit. The pixel sharing unit 111 is repeatedly arranged in an array having a row direction and a column direction. In the present embodiment, the pixel sharing unit 111 includes four sensor pixels 11 and the four sensor pixels 11 share one floating diffusion portion FD. The pixel sharing unit 111 includes one readout circuit 21 for the four sensor pixels 11. Each sensor pixel 11 includes components that are shared with each other. In Figure 1 as well as Figures 4 to 11In order to distinguish the components of the respective sensor pixels 11 from each other, an identification number (1, 2, 3, or 4) is assigned to the end of the symbol of the component of each sensor pixel 11. In the case where it is necessary to distinguish the components of the respective sensor pixels 11 from each other, the identification number is assigned to the end of the symbol of the component of each sensor pixel 11. However, in the case where it is not necessary to distinguish the components of the respective sensor pixels 11 from each other, the identification number is omitted from the end of the symbol of the component of each sensor pixel 11.

[0055] For example, in each sensor pixel 11, the cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., a ground line). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to, for example, a vertical drive circuit 25a described later.

[0056] The floating diffusion FD, shared by the four sensor pixels 11, is electrically connected to the input of the shared readout circuit 21. Specifically, the floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the conversion efficiency switching transistor FDG. The drain of the conversion efficiency switching transistor FDG is electrically connected to the source of the reset transistor RST, and the gate of the conversion efficiency switching transistor FDG is connected to the drive signal line (FDG of wiring 43). The drain of the reset transistor RST is electrically connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line (RST of wiring 43). The gate of the amplifier transistor AMP is connected to the floating diffusion FD, the drain of the amplifier transistor AMP is coupled to the power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to the vertical signal line VSL, and the gate of the select transistor SEL is connected to the drive signal line (SEL of wiring 43).

[0057] Notice, Figure 2 An example is shown in which the conversion efficiency switching transistor FDG is connected in series to the reset transistor RST, but this is not restrictive. Figure 3 As shown, the conversion efficiency switching transistor FDG can be connected in parallel to the reset transistor RST.

[0058] In this embodiment, the additional capacitor wiring X is also connected to the drain of the conversion efficiency switching transistor FDG, for example. Although described in detail below, this additional capacitor wiring X includes wiring on the first substrate 100 side and wiring on the second substrate 200 side, which are electrically connected to each other. For example, the additional capacitor wiring X is connected to the drain of the conversion efficiency switching transistor FDG to increase capacitance. Specifically, when the conversion efficiency switching transistor FDG is turned on under high illumination, the FD capacitance increases. This reduces conversion efficiency and enables the processing of high saturation signal levels within the same pixel transistor.

[0059] The second substrate 200 may further include a logic circuit 25 on the semiconductor substrate 20. The logic circuit 25 controls each sensor pixel 11 and each readout circuit 21 and processes a pixel signal obtained from the readout circuit 21. For example, Figure 12 As shown, the logic circuit 25 includes a vertical drive circuit 25a, a column signal processing circuit 25b, a horizontal drive circuit 25c, and a system control circuit 25d. The logic circuit 25 outputs the output voltage Vout obtained for each sensor pixel 11 to the outside.

[0060] The vertical drive circuit 25a sequentially selects, for example, a plurality of sensor pixels 11 row by row. The vertical drive circuit 25a is electrically connected to, for example, a plurality of drive wirings 112 and sequentially selects, for example, a plurality of sensor pixels 11 row by row by sequentially outputting selection signals to the plurality of drive wirings 112.

[0061] The column signal processing circuit 25b performs, for example, correlated double sampling (CDS) processing on the pixel signals output from each sensor pixel 11 in the row selected by the vertical drive circuit 25a. The column signal processing circuit 25b performs, for example, CDS processing to extract the signal level of the pixel signals. The column signal processing circuit 25b stores pixel data corresponding to the amount of light received by each sensor pixel 11. The column signal processing circuit 25b is electrically connected to, for example, a plurality of vertical signal lines VSL and acquires pixel signals from each sensor pixel 11 in the row selected by the vertical drive circuit 25a via the plurality of vertical signal lines VSL. The column signal processing circuit 25b includes, for example, an ADC (analog-to-digital converter) for each vertical signal line VSL and converts the analog pixel signals acquired via the plurality of vertical signal lines VSL into digital pixel signals.

[0062] The horizontal drive circuit 25c sequentially outputs pixel data stored in, for example, the column signal processing circuit 25b to the outside as an output voltage Vout. The system control circuit 25d controls, for example, the driving of each block in the logic circuit 25 (the vertical drive circuit 25a, the column signal processing circuit 25b, and the horizontal drive circuit 25c). The boost circuit 52 generates, for example, a power supply potential VDD having a predetermined level.

[0063] (1-2. Specific Structure of the Imaging Device)

[0064] The semiconductor substrate 10 includes, for example, a silicon substrate. Semiconductor substrate 10 includes, for example, a photodiode PD (light-receiving portion 12), a floating diffusion FD, a VSS contact region 13, and a transfer transistor TR on the first surface 10A side. Furthermore, semiconductor substrate 10 includes a p-well 14, which includes a p-type semiconductor region. The light-receiving portion 12 includes a semiconductor region of a different conductivity type (specifically, n-type) from that of the p-well 14. The floating diffusion FD is configured as a semiconductor region of a different conductivity type (specifically, n-type) from that of the p-well 14. The VSS contact region 13 is configured as a semiconductor region of the same conductivity type (specifically, p-type) as the p-well 14, having a higher impurity concentration than that of the p-well 14. A portion of the VSS contact region 13 is disposed within the p-well 14. A reference potential line VSS is connected to the VSS contact region 13. Adjacent sensor pixels 11 are thus electrically isolated from each other by the p-well 14.

[0065] The semiconductor substrate 20 includes, for example, a silicon substrate. The semiconductor substrate 20 includes, for example, an n-type semiconductor region 22 on the first surface 20A side. The n-type semiconductor region 22 is included in the source / drain regions of each of the amplifier transistor AMP, the select transistor SEL, the reset transistor RST, and the conversion efficiency switching transistor FDG. Furthermore, a VSS contact region 23 including a p-type semiconductor region and a VDD contact region 24 including an n-type semiconductor region are provided on the first surface 20A side.

[0066] The wiring layer 30 has gate wiring (eg, gate wiring 35; see Figure 14 ), wiring 31 (lower wiring layer), and wiring 32 (upper wiring layer). The gate wiring serves as the gate of the transfer transistor TR. Gate wiring 35, wiring 31, and wiring 32 are sequentially arranged within the interlayer insulating layer 33 from the first surface 10A side of the semiconductor substrate 10. A plurality of pad electrodes 34 are exposed on the surface of the interlayer insulating layer 33.

[0067] For example, the wiring 31 (lower wiring layer) includes a reference potential line VSS to which a fixed potential is applied. The reference potential line VSS is electrically connected to the VSS contact region 13 via a via V1. The reference potential line VSS is formed to surround a pixel-sharing unit 111 including, for example, four sensor pixels 11. This reference potential line VSS has a shielding function that prevents inter-wiring capacitive coupling of, for example, floating diffusions FD between adjacent pixel-sharing units 111. The wiring 31 (lower wiring layer) also includes a wiring 31A. This wiring 31A is formed to surround the four transfer transistors TR1, TR2, TR3, and TR4 included in the pixel-sharing unit 111. The wiring 31A is not electrically connected to any of the light-receiving unit 12, the VSS contact region 13, and the transfer transistor FD provided in the semiconductor substrate 10. The wiring 31A exists in an electrically floating state in the first substrate 100.

[0068] For example, the wiring 32 (upper wiring layer) includes wirings TRG1, TRG2, TRG3, and TRG4 extending in the H direction (row direction). The wirings TRG1, TRG2, TRG3, and TRG4 are used to transmit drive signals to the transfer gates TG1, TG2, TR3, and TG4 of the transfer transistors TR1, TR2, TR3, and TR4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TR3, and TG4, respectively, via the wiring 31 and the vias V1 and V2.

[0069] The wiring layer 40 includes a gate wiring 41, wiring 42 (lower wiring layer), wiring 43 (first intermediate wiring layer), wiring 44 (second intermediate wiring layer), and wiring 45 (upper wiring layer) formed within an interlayer insulating layer 46. The gate wiring 41, wiring 42 (lower wiring layer), wiring 43 (first intermediate wiring layer), wiring 44 (second intermediate wiring layer), and wiring 45 (upper wiring layer) serve as gates for the amplifier transistor AMP, the select transistor SEL, the reset transistor RST, and the conversion efficiency switching transistor FDG. The gate wiring 41, wiring 42, wiring 43, wiring 44, and wiring 45 are arranged in order within the interlayer insulating layer 46 from the first surface 20A side of the semiconductor substrate 20. A plurality of pad electrodes 47 are exposed on the surface of the interlayer insulating layer 46.

[0070] For example, wiring 42 (lower wiring layer) and wiring 43 (first intermediate wiring layer) include wiring SEL, RST and FDG (drive signal lines) extending along the H direction (row direction). Wiring SEL, wiring RST and wiring FDG are used to send drive signals to the gate of the selection transistor SEL, the gate of the reset transistor RST and the gate of the conversion efficiency switching transistor FDG, respectively. Wiring SEL, RST and FDG are connected to the gates of the selection transistor SEL, the reset transistor RST and the conversion efficiency switching transistor FDG through through-holes V4 and V5, respectively. Wiring 42 (lower wiring layer) and wiring 43 (first intermediate wiring layer) also include a power supply line VDD and a reference potential line VSS. The power supply line VDD is connected to the drain of the amplifier transistor AMP through through-holes V4 and V5. The reference potential line VSS is connected to the VSS contact area 23 of the semiconductor substrate 20 through through-holes V4 and V5.

[0071] Wiring 44 (second intermediate wiring layer) includes, for example, a power supply line VDD, a reference potential line VSS, and a vertical signal line VSL extending in the V direction (column direction). The power supply line VDD is connected to the power supply line VDD of wiring 43 via a via V6 and is also connected to the drain of amplifier transistor AMP. The reference potential line VSS is connected to the reference potential line VSS of wiring 43 via a via V6 and is also connected to VSS contact region 23 of semiconductor substrate 20. The vertical signal line VSL is connected to the source (Vout) of select transistor SEL via wirings 42 and 43 and vias V4, V5, and V6.

[0072] For example, the wiring 45 (upper wiring layer) includes a reference potential line VSS. Like the reference potential line VSS of the wiring 31, the reference potential line VSS is formed so as to surround the pixel common unit 111 including, for example, four sensor pixels 11. The reference potential line VSS is connected to the reference potential line VSS of the wiring 44 through a via V7.

[0073] The first substrate 100 and the second substrate 200 have a first surface 10A of the semiconductor substrate 10 and a first surface 20A of the semiconductor substrate 20 facing each other. The first substrate 100 and the second substrate 200 are bonded together by bonding a plurality of pad electrodes 34 and a plurality of pad electrodes 47 exposed from respective surfaces of the wiring layers 30 and the wiring layers 40 provided on the respective first surfaces 10A and 20A.

[0074] The capacitor-adding wiring X is formed to include wiring 31A and wiring 32A of wiring layer 30, for example, formed above the drain of conversion efficiency switching transistor FDG, as well as wiring 42A, wiring 43A, wiring 44A, and wiring 45A of wiring layer 40. Wiring 31A and wiring 32A are connected, for example, via via V2, but each exists in a so-called floating state, not electrically connected to any components provided on first substrate 100. Wiring 42A, wiring 43A, wiring 44A, and wiring 45A are interconnected via vias V5, V6, and V7. Wiring 42 is electrically connected to n-type semiconductor region 22 via via V4. N-type semiconductor region 22 serves as the drain of conversion efficiency switching transistor FDG, for example. The wiring 31A and the wiring 32A each correspond to a specific example of “first wiring” according to the present disclosure, and the wiring 42A, the wiring 43A, the wiring 44A, and the wiring 45A each correspond to a specific example of “second wiring” according to the present disclosure.

[0075] The wiring 31A extends inside the interlayer insulating layer 33, for example, as Figure 1As shown. The wiring 31A is formed to surround the four transfer transistors TR1, TR2, TR3 and TR4 included in the pixel sharing unit 111. The wiring 31A and the wiring 32A, as well as the wiring 42A, the wiring 43A, the wiring 44A and the wiring 45A, are respectively connected to the pad electrode 34A and the pad electrode 47A through, for example, through holes V3 and V8. The pad electrode 34A and the pad electrode 47A are bonded to each other. In other words, the wiring 31A and the wiring 32A are electrically connected to the wiring 42A, the wiring 43A, the wiring 44A and the wiring 45A. Thus, when the conversion efficiency switching transistor FDG is turned on under high illumination, the capacitance of the n-type semiconductor region 22 (sub-floating diffusion SubFD) increases, and the amount of signal processed in the floating diffusion FD increases, wherein the n-type semiconductor region 22 (sub-floating diffusion SubFD) is connected to the capacitance additional wiring X and serves as, for example, the drain of the conversion efficiency switching transistor FDG.

[0076] Notice, Figure 1 While an example is shown in which adjacent sensor pixels 11 are electrically separated by a p-well 14, adjacent sensor pixels 11 may also be separated by a pixel separator, for example, including an insulating film made of silicon oxide (SiO). The pixel separator is configured to separate adjacent sensor pixels 11 from one another and may have, for example, a lattice planar shape. The pixel separator may have, for example, an FTI (Full Trench Isolation) structure, in which the pixel separator extends between the first surface 10A and the second surface 10B of the semiconductor substrate 10. The pixel separator may have, for example, a DTI (Deep Trench Isolation) structure, in which the pixel separator extends from the first surface 10A toward the second surface 10B of the semiconductor substrate 10 and has an end portion in the semiconductor substrate 10.

[0077] (1-3. Actions and Effects)

[0078] The imaging device 1 according to this embodiment includes wirings (wirings 31A and 32A) provided in the wiring layer 30 stacked on the first surface 10A of the semiconductor substrate 10 including the sensor pixels 11. These wirings are not electrically connected to any components provided on the semiconductor substrate 10. These wirings are electrically connected to wirings (wirings 42, 43, 44, and 45) provided in the wiring layer 40 stacked on the first surface 20A of the semiconductor substrate 20 including the readout circuit 21, and are also electrically connected to components provided in the semiconductor substrate 20. This increases the wiring capacitance. This will be described below.

[0079] As described above, in order to achieve smaller imaging devices and higher pixel density, imaging devices have been developed in which each imaging device has a three-dimensional structure in which a semiconductor substrate including, for example, a plurality of sensor pixels and a semiconductor substrate including a signal processing circuit that processes the signal obtained by each sensor pixel are stacked. This imaging device has a photodiode PD, a floating diffusion FD, and a transfer transistor, as well as pixel transistors other than the transfer transistor formed in a different silicon substrate. This increases the area (volume) of the photodiode to increase the saturation charge amount and quantum efficiency. This structure is more efficient for fine pixels with a high ratio of the area of ​​the pixel transistor area to the pixel size.

[0080] In addition, imaging devices each having a three-dimensional structure have been developed, in which a photodiode PD, a floating diffusion portion FD, and a transfer transistor are formed in a first substrate, pixel transistors other than the transfer transistor are formed in a second substrate, and a logic circuit is formed in a third substrate and these three substrates (first substrate, second substrate, third substrate) are stacked.

[0081] However, even with the above-described structure, the channel width and gate length of pixel transistors decrease as pixels become finer. This reduces the operating range of each pixel transistor, such as the select transistor and reset transistor, and thus reduces the amount of signal charge that can be processed. In other words, there is a problem of reduced dynamic range.

[0082] Furthermore, as pixels become finer, the wiring length of the floating diffusion FD decreases, increasing conversion efficiency. In other words, the amplitude of the FD potential increases when receiving the same amount of charge. This further reduces the amount of signal charge to be processed.

[0083] As a technology for handling high saturation signal levels, a camera device has been reported that includes a capacitance-increasing transistor, one end of which is connected to the floating diffusion FD and the other end to the reset transistor. This camera device achieves high conversion efficiency and reduces the effects of noise by turning off the capacitance-increasing transistor. Conversely, the camera device turns on the capacitance-increasing transistor in high-illuminance areas, adding wiring capacitance, diffusion layer capacitance, and oxide film capacitance to the floating diffusion capacitance, thereby reducing conversion efficiency. This enables the processing of high saturation signal levels using the same pixel transistor.

[0084] However, even when the above technology is applied to an image pickup device having a three-dimensional structure, fine pixels have a limited area for wiring for increasing wiring capacitance. This limits the capacitance to be increased, making it difficult to ensure sufficient capacitance.

[0085] In contrast, in this embodiment, wiring (wiring 31A and 32A) that is not electrically connected to any element on the semiconductor substrate 10 is provided in the wiring layer 30, which is laminated on the first surface 10A of the semiconductor substrate 10 including the sensor pixels 11. For example, these wirings are electrically connected to wiring (wiring 42, 43, 44, and 45; capacitance-adding wiring) connected to the conversion efficiency switching transistor FDG, for adding capacitance to the conversion efficiency switching transistor FDG, via pad electrodes 34A and 47A, for example. This also connects the capacitance-adding wiring X to the conversion efficiency switching transistor FDG in addition to the wiring layer 40 of the second substrate 200. The capacitance-adding wiring X is wired to the wiring layer 30 of the first substrate 100.

[0086] The above configuration enables the imaging device 1 according to this embodiment to increase the capacitance of the floating diffusion FD when the conversion efficiency switching transistor FDG is turned on. Specifically, the capacitance of the n-type semiconductor region 22 (sub-floating diffusion SubFD), which serves as, for example, the drain of the conversion efficiency switching transistor FDG, is increased, significantly reducing the conversion efficiency. The capacitance-adding wiring X is connected to the n-type semiconductor region 22 (sub-floating diffusion SubFD). This enables the floating diffusion FD to handle a larger signal volume and expand the dynamic range.

[0087] Furthermore, conventional imaging devices can only increase the capacitance of the floating diffusion FD by increasing the total number of wiring lines. This results in additional steps and increased costs. In contrast, the imaging device 1 according to this embodiment routes the capacitance-adding wiring X in the wiring layer 30 located on the first substrate 100 side (the lower wiring layer or wiring 31). This enables the capacitance of the floating diffusion FD to be increased without increasing the number of steps.

[0088] The following describes a second embodiment and modifications 1 and 2. Note that the following description denotes the same components as those of the above-described first embodiment with the same symbols, and descriptions thereof are omitted as appropriate.

[0089] <2. Modification 1>

[0090] Figure 13 Another example of the layout of the lower wiring layer (wiring 31) in the first substrate 100 of the image pickup device 1 as a modified example (modification 1) of the present disclosure is schematically shown. In the first embodiment described above, an example has been described in which the reference potential line VSS surrounds the pixel common unit 111 including four sensor pixels 11 ( Figure 4 ), but the reference potential VSS extending in the H direction (column direction) may be omitted and may be, for example, as Figure 13 The wiring 31A included in the capacitance adding wiring X is provided as shown.

[0091] For example, with further refinement of pixels, the potential reference line VSS of the wiring 31 functioning as a shield wiring and the wiring 31A included in the capacitance adding wiring X sometimes come too close to each other and the wiring 31A may be difficult to route.

[0092] In contrast, in this modification, the wiring 31A included in the capacitor additional wiring X also serves as a part of the shielding wiring (reference potential line VSS of the wiring 31). When the image pickup device 1 is driven in a high conversion efficiency mode under low illumination, the conversion efficiency switching transistor FDG is turned off and the reset transistor RST is turned on. This fixes the potential of the capacitor additional wiring X at VDD. This allows the capacitor additional wiring X (wiring 31A) having a potential fixed at VDD to shield the area between the pixel sharing units 111 adjacent in the H direction (row direction). This makes it possible to prevent inter-wiring capacitive coupling of the floating diffusion portion FD between adjacent pixel sharing units 111 as in the first embodiment described above.

[0093] Furthermore, the wiring 31A also functions as a portion of the shield wiring (reference potential line VSS of the wiring 31), thereby improving wiring layout efficiency. This allows wiring of the capacitance-added wiring X even when the pixel size is made finer. In other words, the dynamic range can be maintained.

[0094] <3. Second embodiment>

[0095] Figure 14 An example of a cross-sectional configuration in the vertical direction of an image pickup device (image pickup device 2 ) according to the second embodiment of the present disclosure is schematically shown. Figure 15 Shown Figure 14 An example of a schematic configuration of an imaging device 2 is shown in FIG. The imaging device 2 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). The imaging device 2 has a three-dimensional structure in which the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 2 according to this embodiment differs from the first embodiment described above in that a logic circuit (logic circuit 51) is provided on a substrate (the third substrate 300) different from the readout circuit 21.

[0096] The first substrate 100 includes a semiconductor substrate 10 and a wiring layer 30 disposed on a first surface 10A of the semiconductor substrate 10, similar to the first embodiment described above. The first substrate 100 includes the semiconductor substrate 10 and a plurality of sensor pixels 11, each of which performs photoelectric conversion. The plurality of sensor pixels 11 are arranged in a matrix in a pixel region 110 on the first substrate 100. The first substrate 100 includes, for example, a plurality of drive wirings 112 extending in the row direction. The plurality of drive wirings 112 are electrically connected to a vertical drive circuit 51a (described later). For example, the plurality of drive wirings 112 correspond to the wirings TRG1, TRG2, TRG3, and TRG4 described above as the wirings 32.

[0097] The second substrate 200 includes a semiconductor substrate 20 and a wiring layer 40 disposed on a first surface 20A of the semiconductor substrate 20, similar to the first embodiment described above. The semiconductor substrate 20 includes, for example, one readout circuit 21 for each of the four sensor pixels 11. The readout circuit 21 outputs a pixel signal based on the charge output from each sensor pixel 11. Multiple readout circuits 21 are arranged in a matrix in a readout circuit region 121 on the second substrate 200. The wiring layer 40 includes, for example, a plurality of drive wirings extending in the row direction and a plurality of vertical signal lines VSL extending in the column direction. These plurality of drive wirings may, for example, correspond to the wirings RST, FDG, and SEL described above as wiring 43. The plurality of drive wirings disposed in the second substrate 200 are electrically connected to the vertical drive circuit 51a described below. The plurality of vertical signal lines VSL are electrically connected to the signal processing circuit 51b.

[0098] As in the first embodiment described above, the wiring layers 30 and 40 are provided with a capacitance-adding wiring X formed to include wiring 31A and wiring 32A of the wiring layer 30 and wiring 42A, wiring 43A, wiring 44A, and wiring 45A of the wiring layer 40, over, for example, the drain of the conversion efficiency switching transistor FDG. The wiring layers 30 and 40 are connected to, for example, the drain (n-type semiconductor region 22) of the conversion efficiency switching transistor FDG.

[0099] The third substrate 300 includes a semiconductor substrate 50 and a wiring layer 60. The semiconductor substrate 50 has a first surface 50A and a second surface 50B facing each other. The wiring layer 60 is provided on the first surface 50A of the semiconductor substrate 50. The semiconductor substrate 50 includes a logic circuit 51 and a boost circuit 52. The logic circuit 51 controls each sensor pixel 11 and each readout circuit 21, and processes the pixel signal obtained from the readout circuit 21 in the same manner as the logic circuit 25 according to the first embodiment described above. The logic circuit 51 is, for example, Figure 16The logic circuit 51 includes a vertical drive circuit 51a, a column signal processing circuit 51b, a horizontal drive circuit 51c, and a system control circuit 51d. The logic circuit 51 outputs the output voltage Vout obtained for each sensor pixel 11 to the outside.

[0100] The imaging device 2 is provided with a through wiring 71A around the pixel region 110. For example, the through wiring 71A is used to extract the output voltage Vout output by the logic circuit 51 from the imaging device 2 and to provide a reference voltage for the boost circuit 52. Through wirings 71B and 71C are also provided around the pixel region 110. The through wirings 71B and 71C extend to the first substrate 100 and the second substrate 200. The through wiring 71A is electrically connected to the through wirings 71B and 71C via wiring 72 provided on the second surface 10B of the semiconductor substrate 10. The output voltage Vout extracted from the logic circuit 51 and the boosted potential are provided to the first substrate 100 and the second substrate 200, respectively, via the through wirings 71B and 71C.

[0101] As described above, in the imaging device 2 according to this embodiment, the logic circuit 51 is provided on the third substrate 300, and the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. As in the first embodiment described above, the wiring layer 30 of the first substrate 100 and the wiring layer 40 of the second substrate 200 are provided with a capacitance-adding wiring X formed by connecting wiring (wiring 31A and 32A) that is not electrically connected to any element provided on the semiconductor substrate 10 and wiring (wiring 42, 43, 44, and 45) provided in the wiring layer 40 and connected to the conversion efficiency switching transistor FDG. This makes it possible to increase the capacitance of the floating diffusion FD and expand the dynamic range without adding steps, as in the first embodiment described above.

[0102] <4. Modifications>

[0103] Figure 17 An example of a vertical cross-sectional configuration of an imaging device (imaging device 3) according to a modified example (modification 2) of the present disclosure is schematically shown. Imaging device 3 has a three-dimensional structure in which a first substrate 100, a second substrate 200, and a third substrate 300 are stacked in the same order as in the second embodiment described above.

[0104] In this variation, for example, wirings TRG1 , TRG2 , TRG3 , and TRG4 provided on the wiring 32 (upper wiring layer) of the first substrate 100 are electrically connected to wirings (for example, wirings 44A) in the wiring layer 40 of the second substrate 200 that are electrically floating.

[0105] As pixels become finer, in addition to the above-mentioned problem of reduced dynamic range, there is also a possibility that sufficient coupling capacitance cannot be provided between the FD wiring and the transfer gate wiring.

[0106] Conventional wiring layout techniques intentionally run the FD wiring and transfer gate wiring parallel to each other, increasing the coupling capacitance between the FD wiring and the transfer gate wiring. When the transfer transistor is turned on during charge transfer, the FD potential is boosted by the coupling capacitance with the transfer gate wiring, creating a potential difference between the photodiode PD and the floating diffusion FD. This facilitates charge transfer from the photodiode PD to the floating diffusion FD. As pixels become finer, the space available for routing the FD wiring and transfer gate wiring becomes limited. Consequently, sufficient coupling capacitance cannot be ensured, and charge transfer efficiency decreases.

[0107] In contrast, in this modified example, as described above, for example, the wirings TRG1, TRG2, TRG3, and TRG4 provided in the wiring 32 (upper wiring layer) of the first substrate 100 are electrically connected to the wirings (wirings 43A, 44A, and 45A) present in an electrically floating state within the wiring layer 40 of the second substrate 200. This forms wirings (e.g., wiring 31A, wiring TRG1, and wirings 43A, 44A, and 45A; transfer gate wiring Y) in the wiring layers 30 and 40 provided between the semiconductor substrates 10 and 20, and inter-wiring capacitance is formed between the FD wiring and the transfer gate wiring Y. The wiring (e.g., wiring 31A, wiring TRG1, and wiring 43A, 44A, and 45A; transfer gate wiring Y) is electrically connected to a transfer gate TG (e.g., transfer gate TG1), which extends parallel to a wiring (FD wiring) connecting a floating diffusion portion FD provided on the first surface 10A of the semiconductor substrate 10 and an amplifier transistor AMP provided on the first surface 20A of the semiconductor substrate 20.

[0108] As described above, even with increasingly fine pixels, it is possible to maintain a sufficient relative length between the FD wiring and the transfer gate wiring Y. This allows the FD potential to be boosted via the transfer gate wiring Y when transferring charge from the light-receiving unit 12 to the floating diffusion FD, thereby improving charge transfer efficiency. In other words, it is possible to improve afterimage characteristics.

[0109] <5. Application Examples>

[0110] Figure 18 An example of a schematic configuration of an imaging system 4 including an imaging apparatus (for example, imaging apparatus 1 ) according to any of the above-described first and second embodiments and Modifications 1 to 2 thereof is shown.

[0111] The imaging system 4 is an electronic device that includes, for example, an imaging device such as a digital camera or video camera, and a portable terminal device such as a smartphone or tablet terminal. The imaging system 4 includes, for example, the imaging device 1 according to any of the above-described embodiments and their variations, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 4, the imaging device 1 according to any of the above-described embodiments and their variations, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are interconnected via a bus 249.

[0112] The imaging device 1 according to any of the above-described embodiments and their variations outputs image data corresponding to incident light. The DSP circuit 243 is a signal processing circuit that processes the signal (image data) output from the imaging device 1 according to the above-described embodiments and their variations. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 in frame units. The display unit 245 includes a panel-type display unit such as a liquid crystal panel or an organic EL (electroluminescent) panel, and displays moving images or still images captured by the imaging device 1 according to the above-described embodiments and their variations. The storage unit 246 records the image data of moving images or still images captured by the imaging device 1 according to the above-described embodiments and their variations in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operational instructions for various functions of the imaging system 4 in response to user operations. The power supply unit 248 appropriately supplies various power sources for operation to the imaging device 1 according to the above-described embodiments and their variations, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247.

[0113] Next, an image capturing process in the image capturing system 4 is described.

[0114] Figure 19 The following is an example of a flowchart for an imaging operation in the imaging system 4. The user operates the operating unit 247 to issue an instruction to start imaging (step S101). The operating unit 247 then transmits the imaging instruction to the imaging device 1 (step S102). Upon receiving the imaging instruction, the imaging device 1 (specifically, the system control circuit) performs imaging using a predetermined imaging scheme (step S103).

[0115] The imaging device 1 outputs image data obtained through imaging to the DSP circuit 243. Image data refers to pixel signals for all pixels generated based on the charge temporarily held by the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction) on the image data input from the imaging device 1 (step S104). The DSP circuit 243 causes the frame memory 244 to store the processed image data, which in turn causes the storage unit 246 to store the image data (step S105). This completes imaging in the imaging system 4.

[0116] In this application example, the imaging device 1 according to any of the above-described embodiments and their modifications is applied to the imaging system 4. This allows the imaging device 1 to be more compact or to have a higher definition. This allows a compact or high-definition imaging system 4 to be provided.

[0117] <6. Application Examples>

[0118] (Application Example 1)

[0119] The technology according to the present disclosure (the present technology) can be applied to a variety of products. For example, the technology according to the present disclosure can be implemented as a device to be installed on any mobile object such as an automobile, electric vehicle, hybrid vehicle, motorcycle, bicycle, personal mobile object, aircraft, drone, ship, or robot.

[0120] Figure 20 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0121] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Figure 20 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0122] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for a drive force generating device, such as an internal combustion engine or a drive motor, that generates the vehicle's drive force; a drive force transmission mechanism that transmits the drive force to the wheels; a steering mechanism that adjusts the vehicle's steering angle; and a braking device that generates the vehicle's braking force.

[0123] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights (such as headlights, backup lights, brake lights, turn signals, and fog lights). In this case, radio waves transmitted from a mobile device that replaces a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0124] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture images of the vehicle exterior and receives the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can detect objects such as people, vehicles, obstacles, signs, and text on the road surface, or perform processing to detect their distances.

[0125] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information related to the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0126] The in-vehicle information detection unit 12040 detects information related to the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0127] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement advanced driver assistance system (ADAS) functions, including collision avoidance or impact mitigation, following driving based on following distance, cruise control, vehicle collision warning, vehicle lane departure warning, etc.

[0128] In addition, the microcomputer 12051 can perform collaborative control intended for automatic driving by controlling the driving force generating device, steering mechanism, and braking device based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, so that the vehicle can travel autonomously without relying on the driver's operation.

[0129] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to change from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030, thereby performing cooperative control to prevent glare.

[0130] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the occupants of the vehicle or the outside of the vehicle of information. Figure 20 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0131] Figure 21 This is a diagram showing an example of the installation position of the camera unit 12031.

[0132] In FIG. 1022 , the imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 , and 12105 .

[0133] Camera units 12101, 12102, 12103, 12104, and 12105 are located, for example, on the front nose, rearview mirror, rear bumper, and rear door of vehicle 12100, as well as on the upper portion of the windshield inside the vehicle. Camera unit 12101 located on the front nose and camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily capture images of the front portion of vehicle 12100. Camera units 12102 and 12103 located on the rearview mirror primarily capture images of the sides of vehicle 12100. Camera unit 12104 located on the rear bumper or rear door primarily captures images of the rear portion of vehicle 12100. Camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0134] By the way, Figure 21 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located at the rearview mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located at the rear bumper or rear door. For example, a bird's-eye view image of vehicle 12100, viewed from above, can be obtained by superimposing image data captured by imaging units 12101 to 12104.

[0135] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0136] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to vehicle 12100) based on the distance information obtained from imaging units 12101 to 12104, thereby extracting the closest three-dimensional object, particularly one located on the path of vehicle 12100 and traveling in substantially the same direction as vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h), as the leading vehicle. Furthermore, microcomputer 12051 can pre-set a following distance to be maintained ahead of the leading vehicle and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), and the like. Thus, it is possible to execute cooperative control intended for autonomous driving, which enables the vehicle to travel autonomously without relying on operations by the driver or the like.

[0137] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that the driver of the vehicle 12100 can visually identify and those that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or greater than a set value, indicating a potential collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or display unit 12062 and initiates forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 thus assists in driving to avoid collisions.

[0138] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can identify pedestrians, for example, by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from images captured by the imaging units 12101 to 12104, which are infrared cameras; and determining whether a pedestrian exists by performing pattern matching on a series of feature points representing the outline of the object. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a square outline for emphasis, superimposed on the identified pedestrian. The audio / video output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian in a desired location.

[0139] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the components described above. Specifically, the imaging device 1 according to any of the above-described embodiments and their variations can be applied to the imaging unit 12031. Applying the technology according to the present disclosure to the imaging unit 12031 enables the acquisition of high-definition captured images with less noise, thereby enabling the use of the captured images to perform high-precision control in the mobile object control system.

[0140] (Application Example 2)

[0141] Figure 22: is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (the present technology) can be applied.

[0142] exist Figure 22 , a state is shown in which a surgeon (physician) 11131 is performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various devices used for endoscopic surgery are loaded.

[0143] Endoscope 11100 includes a lens barrel 11101 having a predetermined length from its distal end for insertion into a body cavity of a patient 11132, and a camera 11102 connected to the proximal end of lens barrel 11101. In the illustrated example, endoscope 11100 is shown as a rigid endoscope having a rigid lens barrel 11101. However, endoscope 11100 may also be a flexible endoscope having a flexible lens barrel 11101.

[0144] The lens barrel 11101 has an opening at its distal end, in which an objective lens is mounted. A light source device 11203 is connected to the endoscope 11100 so that light generated by the light source device 11203 is introduced into the distal end of the lens barrel 11101 through a light guide extending inside the lens barrel 11101 and illuminates the endoscope toward an observation target in the body cavity of the patient 11132 through the objective lens. Note that the endoscope 11100 may be a forward-looking endoscope, or may be an oblique-looking endoscope or a side-looking endoscope.

[0145] An optical system and imaging element are provided within the camera head 11102, so that reflected light (observation light) from the observation target is focused onto the imaging element through the optical system. The imaging element performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is transmitted as RAW data to the CCU 11201.

[0146] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), and the like, and integrally controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera 11102 and performs various image processing such as development processing (demosaicing processing) on ​​the image signal for displaying an image based on the image signal.

[0147] The display device 11202 displays an image based on an image signal image-processed by the CCU 1121 under the control of the CCU 11201 .

[0148] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and provides irradiation light when imaging the surgical area to the endoscope 11100.

[0149] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user can input instructions to change the imaging conditions (such as the type of irradiation light, magnification, and focal length) of the endoscope 11100.

[0150] The treatment tool control device 11205 controls the driving of the energy device 11112 to perform tasks such as cauterization or cutting of tissue and sealing of blood vessels. The pneumoperitoneum device 11206 delivers gas into the patient's 11132 body cavity via the pneumoperitoneum tube 11111 to inflate the cavity, thereby ensuring the field of view of the endoscope 11100 and the surgeon's working space. The recorder 11207 is a device capable of recording various surgical information. The printer 11208 is a device capable of printing various surgical information in various formats, such as text, images, or graphics.

[0151] Note that when photographing the surgical site, the light source device 1203 that provides irradiation light to the endoscope 11100 may include a white light source, which includes, for example, an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output time can be controlled with high precision for each color (each wavelength), the light source device 11203 can perform white balance adjustment of the captured image. In addition, in this case, if the laser beams from the respective RGB laser light sources are irradiated on the observation target in a time-division manner, and the drive of the imaging element of the camera 11102 is controlled in synchronization with the irradiation timing, it is also possible to capture images corresponding to the R, G, and B colors, respectively, in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0152] Furthermore, the light source device 11203 can be controlled to change the light intensity to be output at predetermined intervals. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity, images can be acquired and synthesized in a time-division manner, thereby creating an image with a high dynamic range, free from underexposed shadows and overexposed highlights.

[0153] In addition, the light source device 11203 can be configured to provide light of a predetermined wavelength band that can be used for special light observation. In special light observation, for example, by utilizing the wavelength dependence of the absorption of light in body tissue, light with a narrower bandwidth than the irradiation light (i.e., white light) during ordinary observation is irradiated, and narrowband observation (narrowband imaging) is performed to image predetermined tissues such as blood vessels in the surface part of the mucosa with high contrast. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by irradiating fluorescence generated by excitation light. In fluorescence observation, fluorescence from human tissue can be observed by irradiating excitation light onto human tissue (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into human tissue and irradiating excitation light corresponding to the fluorescence wavelength of the reagent onto the human tissue. The light source device 11203 can be configured to provide narrowband light and / or excitation light suitable for special light observation as described above.

[0154] Figure 23 It shows Figure 22 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown in FIG.

[0155] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 for communication.

[0156] The lens unit 11401 is an optical system provided at a connection position with the lens barrel 11101. Observation light incident from the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of multiple lenses, including a zoom lens and a focus lens.

[0157] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). In the case where the imaging unit 11402 is constructed as a multi-board type, for example, image signals corresponding to R, G, and B, respectively, are generated by the imaging elements, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be constructed to have a pair of imaging elements for acquiring a right-eye image signal and a left-eye image signal for three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. It should be noted that in the case where the imaging unit 11402 is constructed as a multi-board type, multiple systems of the lens unit 11401 are provided corresponding to the respective imaging elements.

[0158] In addition, the imaging unit 11402 may not necessarily be provided on the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.

[0159] The drive unit 11403 includes an actuator and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0160] The communication unit 11404 includes a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0161] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, for example, information specifying a frame rate of an image to be captured, information specifying an exposure value when capturing an image, and / or information specifying a magnification and focus when capturing an image.

[0162] It should be noted that imaging conditions such as frame rate, exposure value, magnification, or focus may be specified by the user or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the endoscope 11100 has built-in automatic exposure (AE) function, automatic focus (AF) function, and automatic white balance (AWB) function.

[0163] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404 .

[0164] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera 11102 through the transmission cable 11400.

[0165] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted through electrical communication, optical communication, or the like.

[0166] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data transmitted from the camera 11102 .

[0167] The control unit 11413 performs various controls related to capturing images of the operation area, etc. through the endoscope 11100 and displaying captured images obtained by capturing images of the operation area, etc. For example, the control unit 11413 creates a control signal for controlling the driving of the camera head 11102 .

[0168] Furthermore, control unit 11413 controls display device 11202 to display a captured image depicting the surgical area, etc., based on the image signal processed by image processing unit 11412. Control unit 11413 can then use various image recognition technologies to identify various objects in the captured image. For example, control unit 11413 can detect the shape and color of the edges of objects in the captured image to identify surgical tools such as forceps, specific living areas, bleeding, and fog during the use of energy device 11112. When control unit 11413 controls display device 11202 to display the captured image, it can utilize the recognition results to display various surgical support information superimposed on the image of the surgical area. Displaying and providing this superimposed surgical support information to surgeon 11131 can reduce the burden on surgeon 11131, allowing surgeon 11131 to reliably perform surgery.

[0169] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable for electric signal communication, an optical fiber for optical communication, or a composite cable for both electric and optical communication.

[0170] Here, although in the illustrated example, communication is performed by wired communication using the transmission cable 11400, communication between the camera head 11102 and the CCU 11201 may be performed by wireless communication.

[0171] An example of an endoscopic surgical system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be advantageously applied to the imaging unit 11402 of the camera head 11102 of the endoscope 11100 provided in the above-described assembly. Applying the technology according to the present disclosure to the imaging unit 11402 enables miniaturization or higher definition of the imaging unit 11402, thereby enabling the provision of a compact or high-definition endoscope 11100.

[0172] Although the present disclosure has been described above with reference to the first and second embodiments and their Modifications 1 to 2, applicable examples, and application examples, the present disclosure is not limited to the above-described embodiments, etc. Various modifications are possible.

[0173] Note that the effects described herein are merely exemplary. The effects according to the present disclosure are not limited to those described herein. The present disclosure may have effects other than those described herein.

[0174] It should be noted that the present invention may also have the following configuration. According to the present technology having the following configuration, the first wiring and the second wiring are arranged within a wiring layer formed on respective opposing surfaces of a first semiconductor substrate including sensor pixels and a second semiconductor substrate including a readout circuit. This increases wiring capacitance and enables expansion of the dynamic range. One of the first wiring and the second wiring is electrically floating. The other of the first wiring and the second wiring is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate. The first wiring and the second wiring are electrically connected to each other. (1)

[0176] A camera device, comprising:

[0177] a first semiconductor substrate having a first surface and a second surface and including sensor pixels that perform photoelectric conversion;

[0178] a second semiconductor substrate having a third surface and a fourth surface and including a readout circuit that outputs pixel signals based on the charges output from the sensor pixels, the second semiconductor substrate being stacked on the first semiconductor substrate with the first surface and the third surface facing each other; and

[0179] A wiring layer is provided between the first semiconductor substrate and the second semiconductor substrate and includes a first wiring and a second wiring electrically connected to each other, one of the first wiring and the second wiring is in an electrically floating state and the other of the first wiring and the second wiring is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate. (2)

[0181] The imaging device according to (1), wherein

[0182] The wiring layer includes a first wiring layer provided on the first surface of the first semiconductor substrate and a second wiring layer provided on the third surface of the second semiconductor substrate.

[0183] The first wiring is provided in the first wiring layer and is in an electrically floating state in the first wiring layer, and

[0184] The second wiring is provided in the second wiring layer and is electrically connected to the transistor provided on the second semiconductor substrate. (3)

[0186] The imaging device according to (2), wherein the first wiring is not electrically connected to the transistor provided on the first semiconductor substrate. (4)

[0188] The imaging device according to (1), wherein

[0189] The wiring layer includes a first wiring layer provided on the first surface of the first semiconductor substrate and a second wiring layer provided on the third surface of the second semiconductor substrate.

[0190] The first wiring is provided in the second wiring layer and is in an electrically floating state in the second wiring layer, and

[0191] The second wiring is provided in the first wiring layer and is electrically connected to the transistor provided on the first semiconductor substrate. (5)

[0193] The imaging device according to (4), wherein the first wiring is not electrically connected to the transistor provided on the second semiconductor substrate. (6)

[0195] The imaging device according to any one of (1) to (5), wherein

[0196] The sensor pixel includes a light receiving portion, a transfer transistor electrically connected to the light receiving portion, and a floating diffusion portion temporarily holding charges output from the light receiving portion through the transfer transistor, and

[0197] The readout circuit includes a reset transistor, an amplifying transistor, a selecting transistor, and a conversion efficiency switching transistor. The reset transistor resets the potential of the floating diffusion to a predetermined position. The amplifying transistor generates a signal having a voltage corresponding to the level of the charge held by the floating diffusion as the pixel signal. The selecting transistor controls the timing of the pixel signal output from the amplifying transistor. The conversion efficiency switching transistor changes the charge-voltage conversion efficiency of the floating diffusion. (7)

[0199] The image pickup device according to (6), wherein the other of the first wiring and the second wiring is electrically connected to the conversion efficiency switching transistor. (8)

[0201] The image pickup device according to (6), wherein the other of the first wiring and the second wiring is electrically connected to the transfer transistor. (9)

[0203] The imaging device according to any one of (2) to (8), wherein

[0204] The first wiring layer and the second wiring layer each include a plurality of pad electrodes exposed from a surface, and

[0205] The first wiring layer and the second wiring layer are bonded together by bonding the plurality of pad electrodes to each other. (10)

[0207] The imaging device according to (9), wherein the first wiring and the second wiring are electrically connected to connection wiring provided in the first wiring layer and the second wiring layer through the pad electrodes exposed from respective surfaces of the first wiring layer and the second wiring layer. (11)

[0209] In the imaging device according to any one of (6) to (10), the first semiconductor substrate includes the light receiving portion, the transfer transistor, and the floating diffusion portion for each of the sensor pixels. (12)

[0211] The imaging device according to any one of (6) to (10), wherein the first semiconductor substrate has the light receiving portion and the transfer transistor for each sensor pixel, and the floating diffusion portion is shared among a plurality of the sensor pixels. (13)

[0213] The imaging device according to (12), wherein

[0214] The first semiconductor substrate includes a plurality of pixel sharing units, each of the pixel sharing units includes a plurality of the sensor pixels sharing one floating diffusion portion, and

[0215] The first wiring and the second wiring are arranged between adjacent pixel sharing units. (14)

[0217] The imaging device according to (13), wherein a fixed potential is applied to the first wiring and the second wiring. (15)

[0219] The imaging device according to any one of (2) to (14), further comprising a third substrate, the third substrate comprising a signal processing circuit on a third semiconductor substrate, the signal processing circuit processing the pixel signal, wherein

[0220] A first substrate, a second substrate, and the third substrate are sequentially stacked. The first substrate includes the first semiconductor substrate and the first wiring layer. The second substrate includes the second semiconductor substrate and the second wiring layer. (16)

[0222] An electronic device, comprising:

[0223] A camera device, comprising:

[0224] a first semiconductor substrate having a first surface and a second surface and including sensor pixels that perform photoelectric conversion;

[0225] a second semiconductor substrate having a third surface and a fourth surface and including a readout circuit that outputs pixel signals based on the charges output from the sensor pixels, the second semiconductor substrate being stacked on the first semiconductor substrate with the first surface and the third surface facing each other; and

[0226] A wiring layer is provided between the first semiconductor substrate and the second semiconductor substrate and includes a first wiring and a second wiring electrically connected to each other, one of the first wiring and the second wiring is in an electrically floating state and the other of the first wiring and the second wiring is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate.

[0227] This application claims the benefit of Japanese Patent Application No. 2019-216511 filed with the Japan Patent Office on November 29, 2019, which is hereby incorporated by reference into this application in its entirety.

[0228] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A camera device, comprising: a first semiconductor substrate having a first surface and a second surface and including sensor pixels that perform photoelectric conversion; a second semiconductor substrate having a third surface and a fourth surface and including a readout circuit that outputs pixel signals based on the charges output from the sensor pixels, the second semiconductor substrate being stacked on the first semiconductor substrate with the first surface and the third surface facing each other; as well as a wiring layer provided between the first semiconductor substrate and the second semiconductor substrate and including a first wiring and a second wiring electrically connected to each other, one of the first wiring and the second wiring being in an electrically floating state and the other of the first wiring and the second wiring being electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate, in, The wiring layer includes a first wiring layer provided on the first surface of the first semiconductor substrate and a second wiring layer provided on the third surface of the second semiconductor substrate. The first wiring is provided in the first wiring layer and is in an electrically floating state in the first wiring layer, and The second wiring is provided in the second wiring layer and is electrically connected to the transistor provided on the second semiconductor substrate.

2. The imaging device according to claim 1, wherein The first wiring is not electrically connected to the transistor provided on the first semiconductor substrate.

3. The imaging device according to claim 1, wherein The wiring layer includes a first wiring layer provided on the first surface of the first semiconductor substrate and a second wiring layer provided on the third surface of the second semiconductor substrate. The first wiring is provided in the second wiring layer and is in an electrically floating state in the second wiring layer, and The second wiring is provided in the first wiring layer and is electrically connected to the transistor provided on the first semiconductor substrate. The imaging device according to claim 3 , wherein: The first wiring is not electrically connected to the transistor provided on the second semiconductor substrate.

5. The imaging device according to any one of claims 1 to 4, wherein: The sensor pixel includes a light receiving portion, a transfer transistor electrically connected to the light receiving portion, and a floating diffusion portion temporarily holding charges output from the light receiving portion through the transfer transistor, and The readout circuit includes a reset transistor, an amplifying transistor, a selecting transistor, and a conversion efficiency switching transistor. The reset transistor resets the potential of the floating diffusion to a predetermined position. The amplifying transistor generates a signal having a voltage corresponding to the level of the charge held by the floating diffusion as the pixel signal. The selecting transistor controls the timing of the pixel signal output from the amplifying transistor. The conversion efficiency switching transistor changes the charge-voltage conversion efficiency of the floating diffusion. The imaging device according to claim 5 , wherein: The other of the first wiring and the second wiring is electrically connected to the conversion efficiency switching transistor.

7. The imaging device according to claim 5, wherein: The other of the first wiring and the second wiring is electrically connected to the transfer transistor.

8. The imaging device according to any one of claims 1 to 4, wherein: The first wiring layer and the second wiring layer each include a plurality of pad electrodes exposed from a surface, and The first wiring layer and the second wiring layer are bonded together by bonding the plurality of pad electrodes to each other.

9. The imaging device according to claim 8, wherein: The first wiring and the second wiring are electrically connected to connection wirings provided in the first wiring layer and the second wiring layer through the pad electrodes exposed from respective surfaces of the first wiring layer and the second wiring layer. 10 . The imaging device according to claim 5 , wherein the first semiconductor substrate includes the light receiving portion, the transfer transistor, and the floating diffusion portion for each of the sensor pixels.

11. The imaging device according to claim 5, wherein: The first semiconductor substrate includes the light receiving portion and the transfer transistor for each sensor pixel, and the floating diffusion is shared among a plurality of the sensor pixels.

12. The imaging device according to claim 11, wherein The first semiconductor substrate includes a plurality of pixel sharing units, each of the pixel sharing units includes a plurality of the sensor pixels sharing one floating diffusion portion, and The first wiring and the second wiring are arranged between adjacent pixel sharing units.

13. The imaging device according to claim 12, wherein: A fixed potential is applied to the first wiring and the second wiring.

14. The imaging device according to any one of claims 1 to 4, further comprising a third substrate, the third substrate comprising a signal processing circuit on a third semiconductor substrate, the signal processing circuit processing the pixel signal, wherein: A first substrate, a second substrate, and the third substrate are sequentially stacked. The first substrate includes the first semiconductor substrate and the first wiring layer. The second substrate includes the second semiconductor substrate and the second wiring layer.

15. An electronic device, comprising: An imaging device, wherein the imaging device is the imaging device according to any one of claims 1 to 14.

Images