Process deviation detection circuit and process deviation detection method

Abstract

The present disclosure provides a process deviation detection circuit and a process deviation detection method. The process deviation detection circuit is disposed in a chip and includes: a first ring oscillator, wherein a first number of auxiliary elements of a preset type are disposed between two adjacent inverters of the first ring oscillator; a second ring oscillator, wherein a second number of auxiliary elements of the preset type are disposed between two adjacent inverters of the second ring oscillator, the second number being greater than the first number; the number of inverters, type of transistors, and size of the first ring oscillator are the same as the number of inverters, type of transistors, and size of the second ring oscillator, and the type and connection method of the auxiliary elements correspond to the parameters of the components to be tested of the chip. The embodiments of the present disclosure can detect process deviations of various parameters in a chip.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a process deviation detection circuit and a process deviation detection method for detecting a chip. Background Art

[0002] Before a chip leaves the factory, multiple parameters need to be measured to obtain manufacturing process data, such as process deviations, to provide data support for subsequent improvements to equipment and processes while conducting quality inspections.

[0003] In related technologies, transistor delay time is typically measured to determine chip process corner data, but this fails to measure process variations in other parameters, such as transistor gate capacitance, transmission gate resistance, or the resistance of various metal layers within the chip. Therefore, a process variation detection circuit and method are needed that can measure a wider range of parameters.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a process deviation detection circuit and a process deviation detection method, which are used to at least to some extent overcome the problem that the process deviation of more chip parameters cannot be measured due to the limitations and defects of related technologies.

[0006] According to a first aspect of the present disclosure, a process deviation detection circuit is provided. The process deviation detection circuit is provided in a chip and includes:

[0007] a first ring oscillator, wherein a first number of auxiliary elements of a preset type are provided between each of two adjacent inverters of the first ring oscillator;

[0008] a second ring oscillator, wherein a second number of auxiliary elements of the preset type are provided between two adjacent inverters of the second ring oscillator, and the second number is greater than the first number;

[0009] The number of inverters, type and size of transistors of the first ring oscillator are the same as those of the second ring oscillator, and the type and connection method of the auxiliary elements correspond to the parameters of the device under test of the chip.

[0010] In an exemplary embodiment of the present disclosure, the parameters of the component to be measured include transistor gate capacitance, the preset type of auxiliary component is a load inverter, the output end of each inverter of the first ring oscillator is connected to the input ends of a first number of the load inverters, the output end of each inverter of the second ring oscillator is connected to the input ends of a second number of the load inverters, and the output end of each of the load inverters is floating.

[0011] In an exemplary embodiment of the present disclosure, the parameters of the component to be measured include the equivalent resistance of a transmission gate, the auxiliary element is a transmission gate, a first number of the transmission gates are connected in series between two adjacent inverters of the first ring oscillator, and a second number of the transmission gates are connected in series between two adjacent inverters of the second ring oscillator.

[0012] In an exemplary embodiment of the present disclosure, the type of transistor of the auxiliary element is the same as the type of transistor of the inverter.

[0013] In an exemplary embodiment of the present disclosure, the type of transistor of the auxiliary element is not completely the same as the type of transistor of the inverter.

[0014] According to a second aspect of the present disclosure, a process deviation detection circuit is provided. The process deviation detection circuit is provided in a chip and includes:

[0015] A first ring oscillator, wherein two adjacent inverters of the first ring oscillator are connected via a first wire, wherein the first wire is formed of metal of an i-th metal layer of the chip, where i≥1;

[0016] a second ring oscillator, wherein two adjacent inverters of the second ring oscillator are connected via a second wire, the second wire comprising a first portion, a second portion, and a third portion, the first portion being the first wire, the second portion being composed of a through-hole metal connecting the i-th metal layer and the i+1-th metal layer of the chip, and the third portion being composed of metal of the i+1-th metal layer;

[0017] The number of inverters, type and size of transistors of the first ring oscillator are the same as the number of inverters, type and size of transistors of the second ring oscillator.

[0018] In an exemplary embodiment of the present disclosure, a distance between inverters of the second ring oscillator is greater than a distance between inverters of the first ring oscillator.

[0019] In an exemplary embodiment of the present disclosure, the spacing between the inverters of the second ring oscillator is equal to the spacing between the inverters of the first ring oscillator.

[0020] According to a third aspect of the present disclosure, a process deviation detection method is provided, which is applied to the process deviation detection circuit described above, comprising:

[0021] Obtaining a first measured oscillation period of the first ring oscillator and a second measured oscillation period of the second ring oscillator corresponding to each of M chips, where the M chips correspond to the same wafer, the first ring oscillators in the M chips are all the same, and the second ring oscillators in the M chips are all the same, and M≥1;

[0022] determining a difference between the second measured oscillation period and the first measured oscillation period of each chip as a measured oscillation period difference value of each chip;

[0023] Determine a reference oscillation period difference according to the M measured oscillation period differences of the M chips;

[0024] A process deviation detection result of a parameter of a component to be tested of the target chip is determined according to the reference oscillation period difference and the actually measured oscillation period difference of the target chip.

[0025] In an exemplary embodiment of the present disclosure, determining a process deviation detection result of a parameter of a component under test of the target chip according to the reference oscillation period difference and the measured oscillation period difference of the target chip includes:

[0026] Obtaining a difference between the measured oscillation period difference value of the target chip and the reference oscillation period difference value;

[0027] When the difference is greater than zero, it is determined that the parameter of the component under test of the target chip is too large;

[0028] When the difference is less than zero, it is determined that the parameter of the component under test of the target chip is too small;

[0029] When the difference is equal to zero, the parameter standard of the component under test of the target chip is determined.

[0030] In an exemplary embodiment of the present disclosure, determining a reference oscillation period difference value according to the M measured oscillation period differences of the M chips includes:

[0031] The average value of the M measured oscillation period differences is set as the reference oscillation period difference.

[0032] According to a fourth aspect of the present disclosure, a process deviation detection method is provided, which is applied to the process deviation detection circuit described above, comprising:

[0033] Obtaining a first measured oscillation period of the first ring oscillator and a second measured oscillation period of the second ring oscillator corresponding to each of M chips, where the M chips correspond to the same wafer, the first ring oscillators in the M chips are all the same, and the second ring oscillators in the M chips are all the same, and M≥1;

[0034] determining a difference between the second measured oscillation period and the first measured oscillation period of each chip as a measured oscillation period difference of each chip;

[0035] Determine a reference oscillation period difference according to the M measured oscillation period differences of the M chips;

[0036] A process deviation detection result of the resistance of the through-hole metal and the metal of the (i+1)th metal layer is determined according to the reference oscillation period difference and the measured oscillation period difference of the target chip.

[0037] In an exemplary embodiment of the present disclosure, determining a process deviation detection result of resistances of the metal of the through hole and the metal of the (i+1)th metal layer according to the reference oscillation period difference and the measured oscillation period difference of the target chip includes:

[0038] Obtaining a difference between the measured oscillation period difference value of the target chip and the reference oscillation period difference value;

[0039] When the difference is greater than zero, it is determined that the resistance of the metal of the through hole and the metal of the (i+1)th metal layer of the target chip is too large;

[0040] When the difference is less than zero, it is determined that the resistance of the metal of the through hole and the metal of the (i+1)th metal layer of the target chip is relatively small;

[0041] When the difference is zero, the resistance standards of the metal of the through hole and the metal of the (i+1)th metal layer of the target chip are determined.

[0042] In an exemplary embodiment of the present disclosure, determining a reference oscillation period difference value according to the M measured oscillation period differences of the M chips includes:

[0043] The average value of the M measured oscillation period differences is set as the reference oscillation period difference.

[0044] The embodiments of the present disclosure add auxiliary elements or modify wires between adjacent inverters in a ring oscillator. By detecting the measured oscillation period of the ring oscillator, the process deviation results of the process corresponding to the auxiliary elements or wires can be determined, thereby realizing the detection of process deviations of multiple parameters in the chip.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0047] Figure 1 1 is a schematic structural diagram of a process deviation detection circuit in an exemplary embodiment of the present disclosure.

[0048] Figure 2 FIG. 1 is a schematic diagram of a process deviation detection circuit 100 for measuring transistor gate capacitance in an embodiment of the present disclosure.

[0049] Figure 3 FIG. 1 is a schematic diagram of a process deviation detection circuit 100 used to measure transmission gate resistance in an embodiment of the present disclosure.

[0050] Figure 4 FIG. 1 is a schematic diagram of a transmission gate A2 in one embodiment of the present disclosure.

[0051] Figure 5 This is a flow chart of a process deviation detection method in an embodiment of the present disclosure.

[0052] Figure 6 2 is a schematic diagram of a process deviation detection circuit in another embodiment of the present disclosure.

[0053] Figure 7A yes Figure 6 Schematic diagram of the first conductive line in the illustrated embodiment.

[0054] Figure 7B yes Figure 6 Schematic diagram of the second conductive line in the illustrated embodiment.

[0055] Figure 8 It is a top view of the actual shape of the second wire in one embodiment of the present disclosure.

[0056] Figure 9 This is a flow chart of a process deviation detection method in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, devices, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0058] The accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar components, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0059] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 FIG. 4 is a schematic diagram of a process deviation detection circuit in an exemplary embodiment of the present disclosure.

[0061] refer to Figure 1 , the process deviation detection circuit 100 provided in the chip 1 may include:

[0062] A first ring oscillator 11 , wherein a first number N1 of auxiliary elements A of a preset type are disposed between two adjacent inverters 111 of the first ring oscillator 11 ;

[0063] The second ring oscillator 12 has a second number N2 of auxiliary elements A of a predetermined type disposed between two adjacent inverters 121 of the second ring oscillator 12 , where the second number N2 is greater than the first number N1 ;

[0064] The number of inverters, type and size of transistors of the first ring oscillator 11 are the same as those of the second ring oscillator 12 , and the type and connection method of the auxiliary element A correspond to the parameters of the chip's DUT.

[0065] In some embodiments, the transistor type of the auxiliary element A is the same as the transistor type of the inverter (inverter 111 or inverter 121) in each ring oscillator; in other embodiments, the transistor type of the auxiliary element A is not completely the same as the transistor type of the inverter (inverter 111 or inverter 121) in each ring oscillator. Figure 1 The number of auxiliary elements A in the illustrated embodiment is merely an example, and the present disclosure is not limited thereto.

[0066] Below, through specific embodiments Figure 1 The circuit shown is used as an example.

[0067] Figure 2 FIG. 1 is a schematic diagram of a process deviation detection circuit 100 for measuring transistor gate capacitance in an embodiment of the present disclosure.

[0068] refer to Figure 2 When the DUT parameter includes transistor gate capacitance, the preset auxiliary element may be, for example, a load inverter, i.e., an inverter serving as a load. The output of each inverter 111 of the first ring oscillator 11 is connected to the input of a first number N1 of load inverters A1. The output of each inverter 121 of the second ring oscillator 12 is connected to the input of a second number N2 of load inverters A1. The output of each load inverter A1 is left floating.

[0069] exist Figure 2 In the illustrated embodiment, N1 = 1, and N2 = 3. In other embodiments, the values ​​of the first number N1 and the second number N2 may be other values, and the present disclosure is not limited thereto.

[0070] The gate capacitance of the load inverter adds a load to the output end of the inverter in the ring oscillator, thereby increasing the oscillation period of the ring oscillator. The more load inverters a ring oscillator is connected to and the greater the total gate capacitance, the greater the increase in the oscillation period. When the number and position of load inverters connected to two ring oscillators belonging to two different chips are exactly the same, the oscillation period of the ring oscillator is affected by both the inverter transistors and the load inverter transistors due to certain process variations in the manufacturing process of each chip. Therefore, the embodiment of the present disclosure provides two ring oscillators connected to different numbers of load inverters A1 in the same chip. By measuring the difference in the measured oscillation period of the two ring oscillators of the target chip, the process variation of the gate capacitance of the load inverter in the target chip is evaluated, thereby overcoming the impact of the process variation of the inverters in each chip on the measured oscillation period of the ring oscillator. Since the inverter is composed of N-type transistors and P-type transistors, evaluating the process variation of the gate capacitance of the load inverter can evaluate the process variation of the gate capacitance of the transistors of the target chip, that is, the process variation of the gate capacitance of the transistors of the target chip.

[0071] In order to accurately measure the process deviation of the gate capacitance, the types of the P-type transistors and the N-type transistors in the load inverter are exactly the same. In one embodiment, the types of the P-type transistors and the N-type transistors in the load inverter are exactly the same as those of the P-type transistors and the N-type transistors in the inverter to which they are connected; in another embodiment, the types of the P-type transistors and the N-type transistors in the load inverter may be different from those of the P-type transistors and the N-type transistors in the inverter to which they are connected. In addition, the ring oscillator in the embodiment of the present disclosure can be either a symmetrical ring oscillator (the types of the P-type transistors and the N-type transistors in the inverter are exactly the same) or an asymmetrical ring oscillator (the types of the P-type transistors and the N-type transistors in the inverter are different), and the present disclosure does not impose any special restrictions on this.

[0072] In other embodiments of the present disclosure, other types of auxiliary components (such as a separate P-type transistor or a separate N-type transistor) can be connected in parallel to the output of the inverter to measure the gate capacitance of the transistor, or the auxiliary components can be connected only to the output of one or more inverters with specific serial numbers in each ring oscillator. Similarly, when the parameters of the component to be measured include other types of capacitance, the corresponding type of auxiliary components can be connected to the ring oscillator. That is, the process deviation detection circuit 100 can be used to detect the process deviation of multiple capacitors in a chip.

[0073] In addition to being used to test the process variation of capacitance components, the process variation detection circuit 100 can also be used to test the process variation of resistance components in a chip.

[0074] Figure 3FIG. 1 is a schematic diagram of a process deviation detection circuit 100 used to measure transmission gate resistance in an embodiment of the present disclosure.

[0075] refer to Figure 3 When the parameter of the device under test includes the equivalent resistance of a transmission gate, the auxiliary element may be, for example, a transmission gate. A first number N1 of transmission gates A2 are connected in series between two adjacent inverters 111 of the first ring oscillator 11, and a second number N2 of transmission gates A2 are connected in series between two adjacent inverters 121 of the second ring oscillator 12.

[0076] exist Figure 3 In the illustrated embodiment, N1=1, N2=3. In other embodiments, the difference between N2 and N1 may be increased to improve measurement accuracy, or the values ​​of N1 and N2 may be increased simultaneously.

[0077] Figure 4 FIG. 1 is a schematic diagram of a transmission gate A2 in one embodiment of the present disclosure.

[0078] refer to Figure 4 Transmission gate A2 is composed of an N-type transistor 41 and a P-type transistor 42 connected in parallel. N-type transistor 41 and P-type transistor 42 are of identical types. The source of N-type transistor 41 is connected to the drain of P-type transistor 42, and the drain of N-type transistor 41 is connected to the source of P-type transistor 42. The gate of N-type transistor 41 is connected to a first control signal Ctrl1, which is used to turn N-type transistor 41 on or off. The gate of P-type transistor 42 is connected to a second control signal Ctrl2, which is used to turn P-type transistor 42 on or off. The second control signal Ctrl2 is inversely proportional to the first control signal Ctrl1. During testing, the first control signal Ctrl1 is high and the second control signal Ctrl2 is low, respectively turning on N-type transistor 41 and P-type transistor 42.

[0079] exist Figure 4 In the illustrated embodiment, the N-type transistor 41 is an NMOS, and the P-type transistor 42 is a PMOS; in other embodiments, the N-type transistor 41 may be an NPN transistor, and the P-type transistor 42 may be a PNP transistor.

[0080] When a transmission gate (each transmission gate is in the on state) is connected in series between two adjacent inverters in a ring oscillator, the measured oscillation period of the ring oscillator increases due to the on-resistance of the transmission gate. The more transmission gates a ring oscillator has in series, the greater the increase in the measured oscillation period. When the number and position of transmission gates connected to two ring oscillators belonging to two different chips are exactly the same, the oscillation period of the ring oscillator is affected by both the inverter transistors and the transmission gate transistors due to certain process variations in the manufacturing process of each chip. Therefore, the embodiment of the present disclosure provides two ring oscillators connected to different numbers of transmission gates A2 in the same chip. By measuring the difference in the measured oscillation period of the two ring oscillators of the target chip, the resistance of the transmission gates in the target chip, i.e., the process variation of the resistance of the transmission gates of the target chip, is evaluated, thereby overcoming the impact of the process variation of the inverters in each chip on the measured oscillation period of the ring oscillator.

[0081] In one embodiment, the P-type transistors and N-type transistors in the transmission gate are of exactly the same type as the P-type transistors and N-type transistors in the inverter to which they are connected; in another embodiment, the P-type transistors and N-type transistors in the transmission gate are of different types than the P-type transistors and N-type transistors in the inverter to which they are connected. Furthermore, the ring oscillator in the embodiments of the present disclosure may be either a symmetric ring oscillator (the P-type transistors and N-type transistors in the inverter are of exactly the same type) or an asymmetric ring oscillator (the P-type transistors and N-type transistors in the inverter are of different types), and this disclosure does not impose any particular limitation on this.

[0082] In other embodiments of the present disclosure, other transmission gate connection methods can also be used to measure transmission gate resistance. For example, multiple transmission gates can be connected to a ring oscillator using a variety of connection methods, including both series and parallel connections, or transmission gates can be connected only between two or more adjacent inverters of a specific sequence number in the ring oscillator. Similarly, when the component parameters to be measured include other types of resistors, auxiliary components of corresponding types can be connected to the ring oscillator. In other words, the process variation detection circuit 100 can be used to detect process variation of multiple resistors in a chip.

[0083] It is understandable that when testing the process deviation of multiple parameters of the components under test, multiple groups of the above-mentioned detection circuits can be set in the same chip, each group of detection circuits corresponds to an auxiliary component, and each group of detection circuits is used to detect the process deviation of a parameter of the component under test.

[0084] Figure 5 This is a flow chart of a process deviation detection method in an embodiment of the present disclosure. Figure 5 The detection method shown can be performed by Figures 1 to 3 The circuit implementation shown in any embodiment.

[0085] refer to Figure 5 , the process deviation detection method 500 may include:

[0086] Step S51, obtaining a first measured oscillation period of a first ring oscillator and a second measured oscillation period of a second ring oscillator corresponding to each chip in M ​​chips, where the M chips correspond to the same wafer, the first ring oscillators in the M chips are all the same, and the second ring oscillators are all the same, and M≥1;

[0087] Step S52, determining the difference between the second measured oscillation period and the first measured oscillation period of each chip as the measured oscillation period difference of each chip;

[0088] Step S53, determining a reference oscillation period difference according to the M measured oscillation period differences of the M chips;

[0089] Step S54 , determining a process deviation detection result of the component under test parameter of the target chip according to the reference oscillation period difference and the measured oscillation period difference of the target chip.

[0090] In step S51 and step S52, in order to avoid the influence of the process deviation of the inverter in the ring oscillator of different chips on the test results of the auxiliary element, the embodiment of the present disclosure performs difference calculation on the measured oscillation period of the ring oscillator of the same chip to determine the parameters in one chip that are only related to the process parameters to be measured of the auxiliary element.

[0091] In the embodiment of the present disclosure, M chips belong to the same wafer and have exactly the same structure. Therefore, the process deviation of a wafer can be tested by detecting the process deviation of one or several component parameters of each chip in the M chips in a wafer, and then the process or equipment can be improved based on the process deviation of multiple wafers.

[0092] In step S53, the average of the M measured oscillation period differences can be set as the reference oscillation period difference. In other embodiments, the median or mode of the M measured oscillation period differences can be set as the reference oscillation period difference, or the M measured oscillation period differences can be substituted into other preset formulas to determine the reference oscillation period difference, and this disclosure does not impose any particular limitation on this.

[0093] In step S54, the difference between the actual oscillation period difference of the target chip and the reference oscillation period difference can be obtained. When the difference is greater than zero, it is judged that the parameters of the target chip's component under test are too large; when the difference is less than zero, it is judged that the parameters of the target chip's component under test are too small; when the difference is equal to zero, it is judged that the parameters of the target chip's component under test are standard.

[0094] When the device parameter under test is transistor gate capacitance, the auxiliary element can be, for example, a load inverter. In this case, if the target chip's measured oscillation period difference is smaller than the reference difference, it indicates that the target chip's transistor gate capacitance is too small. If the target chip's measured oscillation period difference is larger than the reference difference, it indicates that the target chip's transistor gate capacitance is too large. If the target chip's measured oscillation period difference is equal to the reference difference, it indicates that the target chip's transistor gate capacitance is standard.

[0095] When the component parameter under test is the transmission gate resistance, the auxiliary component can be, for example, a transmission gate. In this case, if the target chip's measured oscillation period difference is smaller than the reference difference, it indicates that the target chip's transmission gate resistance is too small. If the target chip's measured oscillation period difference is larger than the reference difference, it indicates that the target chip's transmission gate resistance is too large. If the target chip's measured oscillation period difference is equal to the reference difference, it indicates that the target chip's transmission gate resistance is standard.

[0096] In addition to obtaining the above-mentioned comparison results of being too large, too small, and standard, the process deviation statistics of the M chips can also be obtained based on the distribution of the measured oscillation period difference corresponding to each chip in the M chips. For example, the process deviation of the parameters of a component under test of the wafer corresponding to the M chips can be determined based on the variance or standard deviation of the M measured oscillation period differences of the M chips. In addition, multiple groups of ring oscillators corresponding to different types of auxiliary components can be set on the chip to evaluate the parameters of multiple components under test, and then the process deviation of a wafer can be comprehensively evaluated from multiple dimensions through the parameters of multiple components under test of the M chips.

[0097] In addition to measuring component parameters, embodiments of the present disclosure provide a process deviation detection circuit for measuring process deviation of semiconductor process layer parameters.

[0098] Figure 6 2 is a schematic diagram of a process deviation detection circuit in another embodiment of the present disclosure.

[0099] refer to Figure 6 , the process deviation detection circuit 600 may include:

[0100] A first ring oscillator 61 , wherein two adjacent inverters 611 of the first ring oscillator 61 are connected via a first wire L1 , wherein the first wire L1 is formed of metal of the i-th metal layer of the chip, where i≥1;

[0101] A second ring oscillator 62, wherein two adjacent inverters 621 of the second ring oscillator 62 are connected via a second wire L2. The second wire L2 includes a first portion, a second portion, and a third portion. The first portion is a first wire, the second portion is formed by a through-hole metal connecting the i-th metal layer and the i+1-th metal layer of the chip, and the third portion is formed by metal of the i+1-th metal layer.

[0102] The number of the inverters 621 , the type and size of the transistors of the first ring oscillator 61 are exactly the same as the number of the inverters 622 , the type and size of the transistors of the second ring oscillator 62 .

[0103] Figure 7A yes Figure 6 Schematic diagram of the first conductive line in the illustrated embodiment.

[0104] Since the structure of the inverter is well known in the art, in the embodiment of the present disclosure, only a box is used to represent the inverter for the convenience of illustration.

[0105] The first wire L1 is used to connect the inverter of the first ring oscillator 61. Figure 7A From the cross-sectional view of the chip, the first end of the first wire L1 is connected to the output end (transistor drain) of the first inverter 611a in the first ring oscillator 61, and the second end is connected to the input end (transistor gate) of the second inverter 611b in the first ring oscillator 61. The first inverter 611a and the second inverter 611b can be any two adjacent inverters in the first ring oscillator 61, and the numbers are for reference only.

[0106] The first inverter 611a and the second inverter 611b have the same structure and transistor type, and are both composed of an N-type transistor and a P-type transistor. A first metal layer M1 and a second metal layer M2 are sequentially disposed above the first inverter 611a and the second inverter 611b.

[0107] The first wire L1 is located in the first metal layer M1, with its first end connected to the output of the first inverter 611a (transistor drain), and its second end connected to the input of the second inverter 611b (transistor gate). The distance between the first inverter 611a and the second inverter 611b is W1.

[0108] Figure 7B yes Figure 6 Schematic diagram of the second conductive line in the illustrated embodiment.

[0109] The second wire L2 is used to connect the inverter of the second ring oscillator 62. Figure 7BFrom the cross-sectional view of the chip, the first end of the second wire L2 is connected to the output end of the first inverter 621a of the second ring oscillator 62, and the second end is connected to the input end of the second inverter 621b of the second ring oscillator 62, where the first inverter 621a and the second inverter 621b can be any two adjacent inverters in the second ring oscillator 62.

[0110] exist Figure 7B In the embodiment shown, the second wire L2 is composed of the first wire L1, the first through-hole V1, the second through-hole V2, and the third wire L3. The first wire L1 is composed of two parts that are not directly in contact, and the two parts are respectively connected to the output end of the first inverter 621a and the input end of the second inverter 621b. The first end of the third wire L3 is connected to the left part of the first wire L1 through the first through-hole V1, and the second end is connected to the right part of the first wire L1 through the second through-hole V2. It should be noted that although the first wire L1 is divided into two parts, the width of the two parts is equal and equal to Figure 7A The width of the first conductor L1 is equal to the total length of Figure 7A The length of the first conductor L1. Figure 7B In the illustrated embodiment, the length of the left portion of the first wire L1 is greater than the length of the right portion. However, in other embodiments of the present disclosure, the lengths of the left and right portions of the first wire L1 in the second ring oscillator may also be proportional, as long as the total length of the left and right portions is equal to the length of the first wire L1 in the first ring oscillator corresponding to the second ring oscillator.

[0111] and Figure 7A Correspondingly, in Figure 7B The output end of the first inverter 621a is connected to the first end of the left part of the first wire L1 located in the first metal layer M1, the second end of the left part of the first wire L1 is connected to the first end of the third wire L3 through the first through-hole V1 set between the first metal layer M1 and the second metal layer M2, the third wire L3 is located in the second metal layer M2, the second end of the third wire L3 is connected to the second through-hole V2 set between the first metal layer and the second metal layer, and the second through-hole V2 is connected to the input end of the second inverter 621b through the right part of the first wire L1.

[0112] The distance between the first inverter 621a and the second inverter 621b is W2. In one embodiment, W2>W1. Since the first wire L1 is the same in both ring oscillators, the second wire L2 can be a straight line when viewed from above. In another embodiment, W2=W1. Since the first wire L1 is the same in both ring oscillators, the second wire L2 can be a curved line when viewed from above.

[0113] Figure 8FIG. 1 is a top view of the actual shape of the second wire L2 in one embodiment of the present disclosure.

[0114] refer to Figure 8 When the pitch W2 of the inverters of the second ring oscillator is equal to the pitch W1 of the inverters of the first ring oscillator, the third wire L3 of the second wire L2 is a curved line. In other embodiments of the present disclosure, the third wire L3 may also have other shapes and lengths, as long as the remaining portion of the second wire L2, except for the portion to be tested (e.g., the third wire L3 formed by the second metal layer M2, the first through hole V1, and the second through hole V2), is consistent with the first wire L1. For example, Figure 7B The second conductor L2 and Figure 7A The difference between the first wire L1.

[0115] Figure 7A 、 Figure 7B 、 Figure 8 In the illustrated embodiment, the first conductor L1 is located in the first metal layer M1. In other embodiments, the first conductor L1 may be located in other metal layers, or may be composed of multiple portions located in multiple metal layers, or may be composed of multiple portions located in multiple metal layers that are not directly connected to each other. Since the first conductor L1 is primarily used to assist in calculating the resistance of the third conductor L3 and the through-hole metal, the specific arrangement of the first conductor L1 is not critical and can be designed by those skilled in the art based on actual circumstances.

[0116] It should be noted that, regardless of the actual arrangement of the first wire L1, the third wire L3 is always arranged on a different metal layer from the first wire L1, and one end of the third wire L3 is always directly connected to the first wire L1 through a metal via. Due to the diversity of transistor processes, in addition to planar transistors (where the gate, drain, and source are arranged side by side in a top view of the chip), vertical transistors (where the source, gate, and drain are arranged sequentially from top to bottom in a cross-sectional view of the chip) are also included. Therefore, the specific forms of the third wire L3 are diverse and are not specifically limited in this disclosure.

[0117] Figure 9 This is a flowchart of a process deviation detection method provided by another embodiment of the present disclosure. Figure 9 The method shown can be Figure 6 The process deviation detection circuit shown is implemented.

[0118] refer to Figure 9 , the process deviation detection method 900 may include:

[0119] Step S91, obtaining a first measured oscillation period of the first ring oscillator and a second measured oscillation period of the second ring oscillator corresponding to each of M chips, wherein the M chips correspond to the same wafer, the first ring oscillators in the M chips are all the same, and the second ring oscillators in the M chips are all the same, and M≥1;

[0120] Step S92, determining the difference between the second measured oscillation period and the first measured oscillation period of each chip as a measured oscillation period difference value of each chip;

[0121] Step S93, determining a reference oscillation period difference according to the M measured oscillation period differences of the M chips;

[0122] Step S94 , determining a process deviation detection result of the resistance of the through-hole metal and the metal of the (i+1)th metal layer according to the reference oscillation period difference and the measured oscillation period difference of the target chip.

[0123] In steps S81 and S92, the second wire L2, comprised of the first wire L1, the third wire L3, and the metal via, has a greater resistance than the first wire L1. Therefore, the measured oscillation period of the second ring oscillator 62 on the same chip is greater than the measured oscillation period of the first ring oscillator 61. To eliminate the influence of the first wire L1 and other structures on the measured resistance of the third wire L3 and the metal via in the target chip, the present embodiment uses the difference between the second ring oscillator 62 and the first ring oscillator 61 to represent parameters related to the resistance of the third wire L3, comprised solely of the metal of the (i+1)th metal layer, and the resistance of the metal via connected to the third wire L3 in a chip.

[0124] In the embodiment of the present disclosure, M chips belong to the same wafer and have exactly the same structure. Therefore, the process deviation of a wafer can be tested by detecting the process deviation of the resistance of a specific metal layer of each chip in the M chips in a wafer, and then the process or equipment can be improved based on the process deviation of multiple wafers.

[0125] In step S93, the average of the M measured oscillation period differences may be set as the reference oscillation period difference. In other embodiments, the median or mode of the M measured oscillation period differences may be set as the reference oscillation period difference, or the M measured oscillation period differences may be substituted into another preset formula to determine the reference oscillation period difference, and this disclosure does not impose any particular limitation on this.

[0126] In step S94, the difference between the actual oscillation period difference of the target chip and the reference oscillation period difference is obtained. If the difference is greater than zero, the target chip's resistance to be measured is determined to be too high. If the difference is less than zero, the target chip's resistance to be measured is determined to be too low. If the difference is zero, the target chip's resistance to be measured is determined to be within the standard. The resistance to be measured is the resistance of the metal in the through-hole and the metal in the (i+1)th metal layer of the target chip.

[0127] The above embodiment can be used not only to measure the process deviation of the resistance of a metal layer and its connected through-hole metal, but also to measure the process deviation of the resistance of multiple metal layers and their connected through-hole metals. In some embodiments, multiple groups such as Figure 6 In the ring oscillators shown, each group of ring oscillators measures the process variation of the resistance of a metal layer and its connected via metal. Multiple groups of ring oscillators can share one or more ring oscillators. For example, the first group of ring oscillators in a chip may include ring oscillators A and B, and the second group of ring oscillators may include ring oscillators B and C. Ring oscillators A, B, and C do not need to be physically grouped. During testing, simply obtain the measured oscillation periods of ring oscillators A, B, and C, and repeat the above calculation twice using the measured oscillation period of ring oscillator B to obtain the process variation corresponding to the two groups of ring oscillators.

[0128] In addition to obtaining the above-mentioned comparison results of being too large, too small, and standard, the process deviation statistics of the M chips can also be obtained based on the distribution of the measured oscillation period difference corresponding to each chip in the M chips. For example, the process deviation of the wafer corresponding to the M chips in a metal layer can be determined based on the variance or standard deviation of the M measured oscillation period difference of the M chips. In addition, multiple groups of ring oscillators corresponding to different process layers (including metal layers or non-metal layers) can also be set on the chip (one or more ring oscillators can also be shared between the multiple groups of ring oscillators) to evaluate the resistance of multiple process layers, and then the process deviation of multiple process layers of a wafer can be comprehensively evaluated through the resistance evaluation of multiple process layers of the M chips.

[0129] In summary, the embodiment of the present disclosure, by modifying the connection between two adjacent inverters of the ring oscillator, can detect the difference in the measured oscillation period of the same type of ring oscillator on the same chip, and then compare the difference in chips produced on the same wafer, or directly count the measured oscillation period difference corresponding to the same wafer, to obtain multiple process deviation results corresponding to one wafer. When multiple groups of ring oscillators such as those provided in the embodiment of the present disclosure are respectively set on a chip, it is possible to simultaneously measure multiple parameters in the wafer (including parameters of the component to be measured or process layer parameters), and accurately evaluate the process deviation in detail, providing strong data support for improving integrated circuit manufacturing processes or equipment.

[0130] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0131] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A process deviation detection circuit, characterized in that: The process deviation detection circuit is provided in the chip, and includes: a first ring oscillator, wherein a first number of auxiliary elements of a preset type are provided between each of two adjacent inverters of the first ring oscillator; a second ring oscillator, wherein a second number of auxiliary elements of the preset type are provided between two adjacent inverters of the second ring oscillator, and the second number is greater than the first number; The number of inverters, type and size of transistors of the first ring oscillator are the same as the number of inverters, type and size of transistors of the second ring oscillator, and the type and connection method of the auxiliary element correspond to the parameters of the device under test of the chip; The parameters of the component to be tested include the gate capacitance of the transistor. The preset type of auxiliary component is a load inverter. The output end of each inverter of the first ring oscillator is connected to the input ends of a first number of the load inverters. The output end of each inverter of the second ring oscillator is connected to the input ends of a second number of the load inverters. The output end of each load inverter is floating.

2. A process deviation detection circuit, characterized in that: The process deviation detection circuit is provided in the chip, and includes: a first ring oscillator, wherein a first number of auxiliary elements of a preset type are provided between each of two adjacent inverters of the first ring oscillator; a second ring oscillator, wherein a second number of auxiliary elements of the preset type are provided between two adjacent inverters of the second ring oscillator, and the second number is greater than the first number; The number of inverters, type and size of transistors of the first ring oscillator are the same as the number of inverters, type and size of transistors of the second ring oscillator, and the type and connection method of the auxiliary element correspond to the parameters of the device under test of the chip; The parameter of the device under test includes an equivalent resistance of a transmission gate, the auxiliary element is a transmission gate, a first number of the transmission gates are connected in series between two adjacent inverters of the first ring oscillator, and a second number of the transmission gates are connected in series between two adjacent inverters of the second ring oscillator; The transmission gate is formed by connecting an N-type transistor and a P-type transistor in parallel. The N-type transistor and the P-type transistor are of exactly the same type. When testing, the transmission gate is turned on.

3. A process deviation detection circuit, characterized in that: The process deviation detection circuit is provided in the chip and includes: A first ring oscillator, wherein two adjacent inverters of the first ring oscillator are connected via a first wire, wherein the first wire is formed of metal of an i-th metal layer of the chip, where i≥1; a second ring oscillator, wherein two adjacent inverters of the second ring oscillator are connected via a second wire, the second wire comprising a first portion, a second portion, and a third portion, the first portion being the first wire, the second portion being composed of a through-hole metal connecting the i-th metal layer and the i+1-th metal layer of the chip, and the third portion being composed of metal of the i+1-th metal layer; The number of inverters, type and size of transistors of the first ring oscillator are the same as the number of inverters, type and size of transistors of the second ring oscillator; The spacing between the inverters of the second ring oscillator is greater than the spacing between the inverters of the first ring oscillator; the second wire appears as a straight line in a top view; and a first portion of the second wire is divided into two segments, and the sum of the widths of the two segments is equal to the width of the first wire connected to the first ring oscillator.

4. A process deviation detection circuit, characterized in that: The process deviation detection circuit is provided in the chip and includes: A first ring oscillator, wherein two adjacent inverters of the first ring oscillator are connected via a first wire, wherein the first wire is formed of metal of an i-th metal layer of the chip, where i≥1; a second ring oscillator, wherein two adjacent inverters of the second ring oscillator are connected via a second wire, the second wire comprising a first portion, a second portion, and a third portion, the first portion being the first wire, the second portion being composed of a through-hole metal connecting the i-th metal layer and the i+1-th metal layer of the chip, and the third portion being composed of metal of the i+1-th metal layer; The number of inverters, type and size of transistors of the first ring oscillator are the same as the number of inverters, type and size of transistors of the second ring oscillator; The distance between the inverters of the second ring oscillator is equal to the distance between the inverters of the first ring oscillator; and the third portion of the second conductive line is a curved line.

5. A process deviation detection method, characterized in that: The process deviation detection circuit as claimed in claim 1 comprises: Obtaining a first measured oscillation period of the first ring oscillator and a second measured oscillation period of the second ring oscillator corresponding to each of M chips, where the M chips correspond to the same wafer, the first ring oscillators in the M chips are all the same, and the second ring oscillators in the M chips are all the same, and M≥1; determining a difference between the second measured oscillation period and the first measured oscillation period of each chip as a measured oscillation period difference value of each chip; Determine a reference oscillation period difference according to the M measured oscillation period differences of the M chips; Determine a process deviation detection result of a parameter of a component under test of the target chip according to the reference oscillation period difference and the measured oscillation period difference of the target chip; Determining a reference oscillation period difference according to the M measured oscillation period differences of the M chips includes: The average value of the M measured oscillation period differences is set as the reference oscillation period difference.

6. The process deviation detection method according to claim 5, characterized in that: The process deviation detection result of determining the parameter of the component under test of the target chip according to the reference oscillation period difference and the measured oscillation period difference of the target chip includes: Obtaining a difference between the measured oscillation period difference value of the target chip and the reference oscillation period difference value; When the difference is greater than zero, it is determined that the parameter of the component under test of the target chip is too large; When the difference is less than zero, it is determined that the parameter of the component under test of the target chip is too small; When the difference is equal to zero, the parameter standard of the component under test of the target chip is determined.

7. A process deviation detection method, characterized in that: The process deviation detection circuit as claimed in claim 2 comprises: Obtaining a first measured oscillation period of the first ring oscillator and a second measured oscillation period of the second ring oscillator corresponding to each of M chips, where the M chips correspond to the same wafer, the first ring oscillators in the M chips are all the same, and the second ring oscillators in the M chips are all the same, and M≥1; determining a difference between the second measured oscillation period and the first measured oscillation period of each chip as a measured oscillation period difference value of each chip; Determine a reference oscillation period difference according to the M measured oscillation period differences of the M chips; Determine a process deviation detection result of a parameter of a component under test of the target chip according to the reference oscillation period difference and the measured oscillation period difference of the target chip; Determining a reference oscillation period difference according to the M measured oscillation period differences of the M chips includes: The average value of the M measured oscillation period differences is set as the reference oscillation period difference.

8. The process deviation detection method according to claim 7, wherein: The process deviation detection result of determining the parameter of the component under test of the target chip according to the reference oscillation period difference and the measured oscillation period difference of the target chip includes: Obtaining a difference between the measured oscillation period difference value of the target chip and the reference oscillation period difference value; When the difference is greater than zero, it is determined that the parameter of the component under test of the target chip is too large; When the difference is less than zero, it is determined that the parameter of the component under test of the target chip is too small; When the difference is equal to zero, the parameter standard of the component under test of the target chip is determined.

9. A process deviation detection method, characterized in that: The process deviation detection circuit as claimed in claim 3 comprises: Obtaining a first measured oscillation period of the first ring oscillator and a second measured oscillation period of the second ring oscillator corresponding to each of M chips, where the M chips correspond to the same wafer, the first ring oscillators in the M chips are all the same, and the second ring oscillators in the M chips are all the same, and M≥1; determining a difference between the second measured oscillation period and the first measured oscillation period of each chip as a measured oscillation period difference of each chip; Determine a reference oscillation period difference according to the M measured oscillation period differences of the M chips; Determine a process deviation detection result of the resistance of the through-hole metal and the metal of the (i+1)th metal layer according to the reference oscillation period difference and the measured oscillation period difference of the target chip; Determining a reference oscillation period difference according to the M measured oscillation period differences of the M chips includes: The average value of the M measured oscillation period differences is set as the reference oscillation period difference.

10. The process deviation detection method according to claim 9, wherein: The process deviation detection result of determining the resistance of the through-hole metal and the metal of the (i+1)th metal layer according to the reference oscillation period difference and the measured oscillation period difference of the target chip includes: Obtaining a difference between the measured oscillation period difference value of the target chip and the reference oscillation period difference value; When the difference is greater than zero, it is determined that the resistance of the through-hole metal and the metal of the (i+1)th metal layer of the target chip is too large; When the difference is less than zero, it is determined that the resistance of the through-hole metal and the metal of the (i+1)th metal layer of the target chip is too small; When the difference is zero, the resistance standards of the through-hole metal and the metal of the (i+1)th metal layer of the target chip are determined.

11. A process deviation detection method, characterized in that: The process deviation detection circuit as claimed in claim 4 comprises: Obtaining a first measured oscillation period of the first ring oscillator and a second measured oscillation period of the second ring oscillator corresponding to each of M chips, where the M chips correspond to the same wafer, the first ring oscillators in the M chips are all the same, and the second ring oscillators in the M chips are all the same, and M≥1; determining a difference between the second measured oscillation period and the first measured oscillation period of each chip as a measured oscillation period difference of each chip; Determine a reference oscillation period difference according to the M measured oscillation period differences of the M chips; Determine a process deviation detection result of the resistance of the through-hole metal and the metal of the (i+1)th metal layer according to the reference oscillation period difference and the measured oscillation period difference of the target chip; Determining a reference oscillation period difference according to the M measured oscillation period differences of the M chips includes: The average value of the M measured oscillation period differences is set as the reference oscillation period difference.

12. The process deviation detection method according to claim 11, wherein: The process deviation detection result of determining the resistance of the through-hole metal and the metal of the (i+1)th metal layer according to the reference oscillation period difference and the measured oscillation period difference of the target chip includes: Obtaining a difference between the measured oscillation period difference value of the target chip and the reference oscillation period difference value; When the difference is greater than zero, it is determined that the resistance of the through-hole metal and the metal of the (i+1)th metal layer of the target chip is too large; When the difference is less than zero, it is determined that the resistance of the through-hole metal and the metal of the (i+1)th metal layer of the target chip is too small; When the difference is zero, the resistance standards of the through-hole metal and the metal of the (i+1)th metal layer of the target chip are determined.

Images