FinFET device, fin cutting method and electronic device thereof

Abstract

The present invention provides a fin cutting method for a FinFET device, and a FinFET device and electronic device formed thereby. The fin cutting method for a FinFET device provided by the present invention forms multiple filling regions filled with a silicon-iron compound in a pseudo-fin structure region on the upper surface of a substrate before cutting; then forms multiple fin structures on the substrate containing the multiple filling regions; and finally removes the pseudo-fin structure containing the filling region material at the bottom. Because the filling region material has a high etching selectivity for silicon, the pseudo-fin structure can be removed from the bottom. Furthermore, because the process is self-aligned, there is no risk of residual or lost fin structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a fin cutting method for a FinFET device and a FinFET device and an electronic device formed thereby. Background Art

[0002] In the field of semiconductor integrated circuit devices, field effect transistors (FET) have always been the main semiconductor devices used to manufacture products such as application-specific integrated circuit chips and static random access memory (SRAM) chips.

[0003] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component or line that can be created using manufacturing processes) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs, and to achieve such advancements, similar developments in semiconductor manufacturing are needed.

[0004] For example, as the semiconductor industry has progressed to nanotechnology processing nodes that pursue higher device density, higher performance and lower cost, challenges from both manufacturing and design have led to the development of fin field effect transistor (FinFET) devices. FinFET devices typically include semiconductor fins with a high aspect ratio and a channel and source / drain regions formed therein. A gate is formed above the fin structure and along (e.g., wrapping) the side of the fin structure, taking advantage of the increased surface area of the channel, to produce a faster, more reliable and more controllable semiconductor transistor device. Cutting is an important step in the formation process of FinFET devices. Fin cutting typically includes longitudinal cutting and lateral cutting. As the fin pitch decreases, longitudinal cutting becomes more challenging. In the hard mask stage, there are two methods of fin cutting: cutting the fins first and cutting the fins later.

[0005] The fin-first method involves epitaxially growing silicon material on a substrate and forming a mask over the epitaxial material; removing the mask for the dummy fin structure; and directly etching the active fin structure. Because the mask for the dummy fin structure is removed, no dummy fin structure is formed. However, due to the uneven distribution of active fin structures within the device, the fin-first method can result in deep etching in some areas and shallow etching in others (a loading effect).

[0006] Therefore, the fin-first method introduces a fin etch loading effect. For example, due to the uneven distribution of multiple fin structures at different intervals, the etching depth of the fin structure in high-density areas is likely to be higher than that in low-density areas. Fin-later cutting, on the other hand, involves forming multiple fin structures at equal intervals above the substrate, and then removing the excess pseudo-fin structures through masking and etching, while retaining the required fin structures. Due to mask position offset or incomplete etching of the fin structure, fin etching residues or missing fins are likely to occur. Summary of the Invention

[0007] The object of the present invention is to provide a fin cutting method for a FinFET device and a FinFET device and an electronic device formed thereby.

[0008] The technical solution adopted by the present invention is to construct a fin cutting method for FinFET devices, comprising the following steps:

[0009] Providing a substrate including a dummy fin structure region and an active fin structure region;

[0010] forming a plurality of filling regions in the dummy fin structure region on the upper surface of the substrate;

[0011] forming a plurality of fin structures on the substrate including the filling region, wherein the fin structures include dummy fin structures and active fin structures;

[0012] The dummy fin structure including the fill region material is removed.

[0013] In the fin cutting method for a FinFET device provided by the present invention, the filling region is filled with a silicon-iron compound.

[0014] In the fin cutting method for a FinFET device provided by the present invention, the step of forming a plurality of filling regions in the dummy fin structure region on the upper surface of the substrate includes:

[0015] forming an etching mask layer in the active fin structure region on the substrate;

[0016] Using the etching mask layer, etching the area on the substrate that is not covered by the etching mask layer to form a plurality of exposed areas;

[0017] Filling a plurality of exposed areas and performing chemical mechanical polishing so that the height of the filled exposed areas is the same as the height of the etching mask layer;

[0018] The etching mask layer is removed and chemical mechanical polishing is performed to form the plurality of filling regions on the upper surface of the substrate.

[0019] In the fin cutting method for a FinFET device provided by the present invention, the step of forming a plurality of filling regions in the dummy fin structure region on the upper surface of the substrate includes:

[0020] forming an etching mask layer in the active fin structure region on the substrate;

[0021] Filling the dummy fin structure area on the substrate and performing chemical mechanical polishing to form a filling area and making the height of the filling area the same as the height of the etching mask layer;

[0022] removing the etching mask layer;

[0023] Sidewall protection spacers are formed on both sides of the filling region.

[0024] In the fin cutting method for a FinFET device provided by the present invention, the filling region is formed by epitaxially growing a semiconductor material in the exposed region.

[0025] In the fin cutting method for a FinFET device provided by the present invention, the step of forming a plurality of fin structures on the substrate includes:

[0026] growing a silicon layer above the substrate;

[0027] forming a plurality of patterned masks over the silicon layer;

[0028] The substrate including the multiple filling regions and the silicon layer are etched through multiple patterned masks to form multiple fin structures.

[0029] In the fin cutting method for FinFET devices provided by the present invention, the material of the filling region is a silicon-based compound containing a dopant, wherein the dopant is selected from one of boron, phosphorus or arsenic, and the doping concentration is 1e 16 ~1e 20 cm -3 .

[0030] In the fin cutting method for a FinFET device provided by the present invention, dry etching is used to form a plurality of fin structures on the substrate; and wet etching is used to remove the dummy fin structure containing the filling region material.

[0031] According to another aspect of the present invention, a FinFET device formed by the method described above is also provided.

[0032] According to yet another aspect of the present invention, a sub-device is provided, comprising the FinFET device described above.

[0033] The fin cutting method for FinFET devices of the present invention has the following beneficial effects: before cutting, the fin cutting method for FinFET devices provided by the present invention forms multiple filling areas filled with silicon-iron compounds in the pseudo fin structure area on the upper surface of the substrate; then forms multiple fin structures on the substrate including the multiple filling areas; and finally removes the pseudo fin structure including the filling area material on the bottom.

[0034] The overall effect of the present invention is as follows: the present invention forms a plurality of dummy fin structures and active fin structures above the substrate, and then forms a preset FinFET device by removing the dummy fin structure, thereby avoiding the load effect in the process of first cutting the fin; in addition, the present invention provides a filling area material at the bottom of the dummy fin structure, and utilizes the high etching selectivity of the filling area material to silicon, so that the dummy fin structure can be removed from the bottom; in addition, since self-alignment is achieved through the filler, the risk of residual and lost fin structure is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. Those skilled in the art can also derive other drawings based on the provided drawings without inventive work.

[0036] Figure 1 1 is a flow chart of a fin cutting method for a FinFET device provided in accordance with a first embodiment of the present invention;

[0037] Figure 2-Figure 10 1 is a schematic cross-sectional view of various stages of a fin cutting method for a FinFET device according to a first embodiment of the present invention;

[0038] Figure 11-14 1 is a schematic cross-sectional view of various stages of a fin cutting method for a FinFET device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0039] The following discloses many different implementation methods or examples to implement the different features of the embodiments of the present invention. The following describes specific embodiments of components and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration and should not be used to limit the scope of the embodiments of the present invention. For example, when the specification mentions that a first feature is formed on a second feature, it includes an embodiment in which the first feature and the second feature are in direct contact, and also includes an embodiment in which there are other features between the first feature and the second feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the embodiments of the present invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0040] In addition, spatial terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used to describe the relationship between one element or feature and another element or feature in the drawings. These spatial terms include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used therein will also be interpreted based on the orientation.

[0041] Although the steps in some embodiments are described as being performed in a specific order, these steps may be performed in any other logical order. In different embodiments, some of the steps described may be replaced or omitted, and other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. The semiconductor device structures in the embodiments of the present invention may include additional features. In different embodiments, some features may be replaced or omitted.

[0042] Example 1

[0043] Figure 1 FIG2 is a flow chart of a fin cutting method for a FinFET device provided in accordance with a first embodiment of the present invention; Figure 2-Figure 10 1 is a cross-sectional schematic diagram of each stage of the fin cutting method for FinFET devices according to the first embodiment of the present invention. Figure 1 Flowchart with Figures 2 to 10 The schematic diagram of the embodiment 1 of the present invention is shown in FIG.

[0044] like Figure 1 and Figure 2-6 As shown, a plurality of filling regions 204 are formed in the dummy fin structure region on the upper surface of the substrate 201. Figure 2 As shown, the method 10 begins with step 101 , providing a substrate including a dummy fin structure region and an active fin structure region, and performing ion implantation on the substrate 201 ;

[0045] Specifically, as will be appreciated by those skilled in the art after a complete reading of this application, the illustrative FinFET device 200 described herein may be comprised of an N-type FinFET device, a P-type FinFET device, or any combination of such N- and P-type devices. The FinFET device 200 shown herein will be formed on a substrate 201 comprised of a semiconductor material, such as a bulk semiconductor substrate. The device 200 may also be formed on a so-called SOI (semiconductor-on-insulator) substrate, where the substrate 201 will be the active layer of such an SOI substrate. Additionally, the substrate 201 may be comprised of any semiconductor material, such as silicon, silicon germanium, germanium, or a combination of so-called III-V materials. Therefore, it should be understood that the terms "substrate," "semiconductor substrate," or "semiconducting substrate" encompass all semiconductor materials, regardless of their physical form.

[0046] In some embodiments, Figure 2 The substrate 201 in the embodiment may be a semiconductor substrate, which may include elemental semiconductors such as silicon (Si), germanium (Ge), etc.; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc.; alloy semiconductors such as silicon-germanium alloy (SiGe), gallium arsenic phosphide alloy (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), gallium indium arsenide alloy (GaInAs), gallium indium phosphide alloy (GaInP), gallium indium arsenide phosphide alloy (GaInAsP), or combinations of the above materials.

[0047] like Figure 1 and Figure 3 As shown, the method 10 then proceeds to step 102 to form an etching mask layer 202 on the active fin structure region of the substrate 201. The etching mask layer is a hard mask layer.

[0048] Specifically, in some embodiments, the initial patterned hardmask layer 202 is comprised of a plurality of linear features extending across the upper surface of the substrate 201. The material comprising the patterned hardmask layer 202 may vary depending on the specific application, as it may be comprised of various materials, such as silicon oxide, silicon nitride, and silicon oxynitride. The patterned hardmask layer 202 may be formed by depositing a plurality of layers of material comprising the hardmask layer 202 and then directly patterning the hardmask layer 202 using known photolithography and etching techniques. Alternatively, the patterned hardmask layer 202 may be formed using known sidewall image transfer techniques. Therefore, the specific form and composition of the patterned hardmask layer 202, as well as its application method, should not be considered limiting of the present invention.

[0049] like Figure 1 and Figure 4 As shown, the method 10 then proceeds to step 103 , where the hard mask layer 202 is used to etch the areas of the substrate 201 not covered by the hard mask layer 202 to form a plurality of exposed areas 203 .

[0050] Specifically, in some embodiments, the etching process may include a dry etching process (e.g., reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination thereof. In some embodiments, the dry etching process may be performed using an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasma, and / or a combination thereof. In some embodiments, the wet etching process may include etching in dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, a hydrofluoric acid (HF) solution, nitric acid (HNO3), and / or acetic acid (CH3COOH), or other suitable wet etchants.

[0051] like Figure 1 and Figure 5 As shown, the method 10 then proceeds to step 104 , filling the plurality of exposed regions 203 and performing chemical mechanical polishing, so that the height of the filled exposed regions is the same as the height of the surrounding hard mask layer.

[0052] Specifically, in some embodiments, silicon x Ge y ) compound or fill multiple etched areas by in-situ boron doping. It should be understood by those skilled in the art that the "filling" here is not a simple deposition, but can be to maintain a single crystal structure through epitaxial growth technology.

[0053] like Figure 1 and Figure 6 As shown, the method 10 then proceeds to step 105 , removing the hard mask layer 202 and performing chemical mechanical polishing to make the height of the exposed area the same as that of the surrounding substrate 201 , thereby forming a plurality of filling regions 204 on the upper surface of the substrate 201 .

[0054] like Figure 1 and Figure 7-9As shown, the method 10 then proceeds to steps 106 - 108 to form a plurality of fin structures on the substrate 201 including the plurality of filling regions 204 , the fin structures including dummy fin structures 205 and active fin structures 208 :

[0055] Specifically, if Figure 7 As shown, first, in step 106, a silicon layer 206 is epitaxially grown on the substrate 201;

[0056] Then, if Figure 8 As shown, in step 107, a plurality of patterned masks 207 are formed over the silicon layer 206. In some embodiments, the patterned masks 207 may include polysilicon, silicon-rich oxide, oxynitride, aluminum oxide, or a combination thereof. In some embodiments, three mask layers may be formed over the silicon layer 206 using chemical vapor deposition (e.g., high-density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, or plasma-assisted chemical vapor deposition), atomic layer deposition, physical vapor deposition, electroplating, spin-on coating, other suitable techniques, or a combination thereof.

[0057] Then, if Figure 9 As shown, in step 108, the substrate 201 including the multiple filling regions 204 and the silicon layer 206 are etched through multiple patterned masks 207 to form multiple fin structures; in some embodiments, the etching process may include a dry etching process (e.g., reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination thereof; in some embodiments, the dry etching process may be performed using an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or a combination thereof.

[0058] like Figure 1 and Figure 10 As shown, the method 10 then proceeds to step 109 to cut the dummy fin structure 205 including the material of the filling region 204. x Ge y ) has a high etching selectivity to silicon, so the pseudo-fin structure can be removed from the bottom; in addition, since it is a self-aligned process, there is no risk of fin structure residue and loss.

[0059] Preferably, a dry etching process is used to form the plurality of fin structures, including the dummy fin structure 205 and the active fin structure 208. Because the etching process involves silicon in the silicon layer 206, the boron-doped silicon-germanium compound in the filling region, and silicon in the substrate 201, and because the selectivity ratio between the silicon-germanium compound and silicon is close during dry etching, the dry etching process can form dummy fin structures and active fin structures with precise dimensions.

[0060] The dummy fin structure 205 including the filling material is removed by wet etching. Because the selectivity of the germanium-silicon compound and silicon is significantly different in wet etching, the filling material (ie, the germanium-silicon compound) at the bottom of the dummy fin structure is removed by wet etching, thereby removing the entire dummy fin structure.

[0061] Preferably, the material of the filling region is a germanium-silicon compound containing a dopant, wherein the dopant is selected from one of boron, phosphorus or arsenic, and the doping concentration is 1e 16 ~1e 20 cm -3 . This is because the epitaxial growth characteristics of the filling material in the filling area are consistent with the substrate silicon material; the filling material and silicon have a high selectivity in wet etching, thereby realizing the removal of the pseudo fin structure using the filling area material. Based on the above two reasons, germanium silicon compound is selected. In addition, on the one hand, in the wet etching removal of the pseudo fin structure containing the filling area material, boron is doped into the germanium silicon compound, which can improve the etching selectivity of the germanium silicon compound and silicon, and improve the etching efficiency. On the other hand, the boron doped in the filling area is easy to penetrate into the substrate, and the filling area material will be removed in the process of removing the pseudo fin structure. At this time, the residual boron can be used as a means of detecting or verifying the preparation process and effect.

[0062] Example 2

[0063] Figure 11-14 1 is a cross-sectional schematic diagram of each stage of the fin cutting method for FinFET device according to the second embodiment of the present invention. The difference from the first embodiment is that, Figure 11-14 As shown, the steps of forming a plurality of filling regions 303 in the dummy fin structure region on the upper surface of the substrate 301 are different from those in the first embodiment:

[0064] First, ion implantation is performed on the substrate 301;

[0065] like Figure 11 As shown, a hard mask layer 302 is formed on the active fin structure region of the substrate 301 ; the method of forming the hard mask layer 302 is the same as that of the first embodiment, and will not be repeated here;

[0066] like Figure 12FIG. 3 shows a method of filling the dummy fin structure region on the substrate and performing chemical mechanical polishing so that the height of the filling region 303 is the same as the height of the hard mask layer 302. Specifically, in some embodiments, silicon nitride (Si nitride) is used. x Ge y ) compound or fill multiple etched areas by in-situ boron doping;

[0067] like Figure 13 As shown, the hard mask layer 302 is removed;

[0068] like Figure 14 Sidewall protection spacers 304 are shown formed on both sides of the fill region. Sidewall protection spacers 304 may be an oxide, a nitride, an oxynitride, a high-k dielectric material, a low-k dielectric material, or a combination thereof. Precursor materials or reactant gases used to form sidewall protection spacers 304 may include triethoxysilane (TRIES), tetraethoxysilane (TEOS), bis-tertbutylaminosilane (BTBAS), O2, N2O, NO, other gases or materials, or a combination thereof. In some embodiments, the spacer material may be conformally deposited on the substrate using chemical vapor deposition (e.g., high-density plasma chemical vapor deposition (HDPCVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-assisted chemical vapor deposition (PACVD), atomic layer deposition (ALD), other suitable techniques, or a combination thereof.

[0069] Furthermore, the process steps after forming the filling region are similar to those in the first embodiment. Figure 7-10 The steps are the same as those in the present invention, and will not be repeated here.

[0070] The present invention also provides an electronic device comprising a FinFET device manufactured according to a method according to an exemplary embodiment of the present invention. The electronic device can be any electronic product or device, such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigation system, camera, camcorder, voice recorder, MP3 player, MP4 player, or PSP, or any intermediate product comprising the FinFET device. The electronic device, due to the use of the FinFET device, exhibits improved performance.

[0071] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A fin cutting method for a FinFET device, characterized in that: The following steps are involved: Providing a substrate including a dummy fin structure region and an active fin structure region; forming a plurality of filling regions in the dummy fin structure region on the upper surface of the substrate; forming a plurality of fin structures on the substrate including the filling region, wherein the fin structures include dummy fin structures and active fin structures; Using a self-aligned technique to remove only the filling area material at the bottom of the dummy fin structure, thereby removing the entire dummy fin structure; The step of forming a plurality of fin structures includes: growing a silicon layer above the substrate; forming a plurality of patterned masks over the silicon layer; The substrate including the multiple filling regions and the silicon layer are etched through multiple patterned masks to form multiple fin structures.

2. The fin cutting method for FinFET device according to claim 1, characterized in that: The filling area is filled with a silicon-carbon compound.

3. The fin cutting method for FinFET device according to claim 2, characterized in that: The step of forming a plurality of filling regions in the dummy fin structure region on the upper surface of the substrate includes: forming an etching mask layer in the active fin structure region on the substrate; Using the etching mask layer, etching the area on the substrate that is not covered by the etching mask layer to form a plurality of exposed areas; Filling a plurality of exposed areas and performing chemical mechanical polishing so that the height of the filled exposed areas is the same as the height of the etching mask layer; The etching mask layer is removed and chemical mechanical polishing is performed to form the plurality of filling regions on the upper surface of the substrate.

4. The fin cutting method for FinFET device according to claim 2, characterized in that: The step of forming a plurality of filling regions in the dummy fin structure region on the upper surface of the substrate includes: forming an etching mask layer in the active fin structure region on the substrate; Filling the dummy fin structure area on the substrate and performing chemical mechanical polishing to form a filling area and making the height of the filling area the same as the height of the etching mask layer; removing the etching mask layer; Sidewall protection spacers are formed on both sides of the filling region.

5. The fin cutting method for FinFET device according to claim 3 or 4, characterized in that: The filling region is formed by epitaxially growing semiconductor material in the exposed region.

6. The fin cutting method for FinFET device according to claim 2, characterized in that: The material of the filling region is a silicon-based compound containing a dopant, wherein the dopant is selected from one of boron, phosphorus or arsenic, and the doping concentration is 1e 16 ~1e 20 cm -3 .

7. The fin cutting method for a FinFET device according to claim 2, wherein: A plurality of fin structures are formed on the substrate by dry etching; and the dummy fin structure including the filling region material is removed by wet etching.

8. A FinFET device formed according to the method of any one of claims 1-6.

9. An electronic device, characterized in that: The invention comprises a FinFET device formed according to the method of any one of claims 1 to 6.

Images