Array substrate and preparation method thereof, and display panel

Abstract

The present application discloses an array substrate and a manufacturing method thereof, and a display panel, wherein the array substrate has a display area and a non-display area; wherein in the non-display area, the array substrate comprises a base substrate, a first metal layer, a first insulating layer, and a second metal layer stacked in sequence, and the first metal layer is electrically connected to the second metal layer. The metal wiring in the non-display area is arranged in multiple layers, which can reduce the width of the common electrode wiring while ensuring the normal operation of the capacitance and resistance of the common electrode wiring.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel including the array substrate. Background Art

[0002] With the development of LCD (Liquid Crystal Display), ultra-narrow bezel design has gradually become a mainstream product, but ultra-narrow bezels have higher requirements for panel design and manufacturing. The display area is closer to the edge of the glass, which leads to a smaller requirement for the width of the black matrix outside the display area. Currently, the main factors affecting the width of the black matrix are the GOA (Gate Driven on array) area and the common electrode wiring around the outermost periphery of the display panel. Reducing the width of the common electrode wiring can reduce the width of the black matrix outside the display area, but reducing the width of the black matrix outside the display area will increase the resistance and capacitance of the common electrode wiring, making the voltage distribution on the opposite color film substrate uneven, thereby affecting the display effect of the display panel.

[0003] Therefore, it is urgent to improve the defects in the prior art. Summary of the invention

[0004] The purpose of the present application is to provide an array substrate and a method for preparing the same, and a display panel, so as to solve the problem of the current display panel having a frame that is too wide.

[0005] An embodiment of the present application provides an array substrate, which has a display area and a non-display area located outside the display area; wherein in the non-display area, the array substrate includes: a base substrate; a first metal layer, arranged on one side of the base substrate; a first insulating layer, arranged on a side of the first metal layer away from the base substrate; a second metal layer, arranged on a side of the first insulating layer away from the first metal layer; wherein the first metal layer is electrically connected to the second metal layer.

[0006] Optionally, in some embodiments of the present application, the non-display area includes: a GOA circuit area and a common electrode wiring area; wherein in the common electrode wiring area, the first metal layer is electrically connected to the second metal layer.

[0007] Optionally, in some embodiments of the present application, the array substrate also includes: a second insulating layer, arranged on a side of the second metal layer that is close to the first insulating layer; a first via hole, penetrating the second insulating layer, the second metal layer and the first insulating layer, exposing a portion of the first metal layer; a second via hole, penetrating the second insulating layer, exposing a portion of the second metal layer; and a conductive layer, arranged on a side of the second insulating layer away from the first metal layer, and covering the first via hole and the second via hole, so as to electrically connect the first metal layer with the second metal layer.

[0008] Optionally, in some embodiments of the present application, the array substrate further includes: a third via hole, penetrating the second metal layer and the first insulating layer, exposing a portion of the first metal layer; wherein the second metal layer is electrically connected to the second metal layer through the third via hole.

[0009] Optionally, in some embodiments of the present application, the array substrate further includes: a conductive connection layer, disposed on a side of the second metal layer away from the first metal layer and covering the first via hole to electrically connect the first metal layer with the second metal layer.

[0010] Optionally, in some embodiments of the present application, the thickness of the second metal layer is less than or equal to the thickness of the first metal layer; and the projection of the second metal layer on the base substrate is located within the projection of the first metal layer on the base substrate.

[0011] Optionally, in some embodiments of the present application, the orthographic projection shapes of the first via hole and the second via hole on the base substrate include at least one of a circle, a square, a trapezoid, an ellipse and a regular polygon.

[0012] Correspondingly, an embodiment of the present application also provides a method for preparing an array substrate, comprising the following steps: step S1: providing a base substrate; step S2: depositing a metal material on the base substrate, and patterning to form a first metal layer; step S3: depositing an insulating material on the first metal layer, and patterning to form a first insulating layer, and exposing a portion of the first metal layer; step S4: depositing a metal material on the first insulating layer, and patterning to form a second metal layer, and exposing a portion of the first metal layer; step S5: depositing an insulating material on the second metal layer, and patterning to form a second insulating layer, and exposing a portion of the first metal layer to form a first via, and exposing a portion of the second metal layer to form a second via; step S6: depositing a conductive material on the second insulating layer, and patterning to form a conductive layer, wherein the conductive layer covers the first via and the second via to electrically connect the first metal layer and the second metal layer.

[0013] Correspondingly, an embodiment of the present application further provides a display panel, comprising the array substrate described in any of the above embodiments; a color film substrate, arranged opposite to the array substrate; and a frame sealant, wherein the frame sealant is located between the array substrate and the color film substrate; wherein a portion of the frame sealant is located in the non-display area of ​​the array substrate, and conductive gold balls are arranged in the frame sealant, and the conductive gold balls are used to electrically connect the array substrate and the color film substrate.

[0014] Optionally, in some embodiments of the present application, in the array substrate, the first metal layer, the second metal layer and the conductive layer together constitute a first common electrode; the color film substrate includes a color film base substrate and a second common electrode arranged on the color film base substrate; wherein the conductive gold ball is used to electrically connect the first common electrode with the second common electrode.

[0015] In summary, the present application discloses an array substrate and a preparation method thereof, and a display panel, wherein the array substrate has a display area, a GOA circuit area, and a common electrode wiring area, wherein the GOA circuit area is located on both sides of the display area, and the common electrode wiring area surrounds the display area and the GOA circuit area; wherein in the common electrode wiring area, the array substrate includes a base substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a conductive layer stacked in sequence; wherein the conductive layer is electrically connected to the first metal layer and the second metal layer through a first via hole and a second via hole. The metal wiring in the common electrode wiring area is arranged in multiple layers, which can reduce the width of the common electrode wiring while ensuring the normal operation of the capacitance and resistance of the common electrode wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a planar schematic diagram of the array substrate described in the embodiment of the present application;

[0018] Figure 2 The three-dimensional structure of the array substrate in the embodiment of the present application is shown in FIG. Figure 1 ;

[0019] Figure 3 The three-dimensional structure of the array substrate in the embodiment of the present application is shown in FIG. Figure 2 ;

[0020] Figure 4The three-dimensional structure of the array substrate in the embodiment of the present application is shown in FIG. Figure 3 ;

[0021] Figure 5 is a schematic diagram of the preparation process of the array substrate described in the embodiment of the present application;

[0022] Figure 6 It is a three-dimensional schematic diagram of a part of the structure of the array substrate described in the embodiment of the present application. Figure 1 ;

[0023] Figure 7 It is a three-dimensional schematic diagram of a part of the structure of the array substrate described in the embodiment of the present application. Figure 2 ;

[0024] Figure 8 It is a three-dimensional schematic diagram of a part of the structure of the array substrate described in the embodiment of the present application. Figure 3 ;

[0025] Fig. 9 It is a three-dimensional schematic diagram of a part of the structure of the array substrate described in the embodiment of the present application. Figure 4 ;

[0026] Fig.10 It is a three-dimensional schematic diagram of a part of the structure of the array substrate described in the embodiment of the present application. Figure 5 ;

[0027] Fig.11 is a partial enlarged plan view of the display panel described in the embodiment of the present application;

[0028] Fig.12 yes Fig.11 Schematic diagram of the three-dimensional structure of the AA' section of the display panel.

[0029] Description of main reference numerals:

[0030] DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "up", "down", "left" and "right", can be the direction of the actual use or working state of the device, can also be the direction of the drawing with reference to the accompanying drawings, and can also refer to two relative directions; while "inside" and "outside" refer to the outline of the device.

[0032] Please refer to Figure 1 and Figure 2 Specifically, the embodiment of the present application provides an array substrate 100, the array substrate 100 having a display area 101 and a non-display area 102; the non-display area 102 includes: a GOA circuit area 1021 and a common electrode wiring area 1022, the GOA circuit area 1021 is located on both sides of the display area 101, and the common electrode wiring area 1022 surrounds the display area 101 and the GOA circuit area 1021; wherein, in the common electrode wiring area 1022, the array substrate 100 includes a base substrate 110, a first metal layer 120, a first insulating layer 130, a second metal layer 140, a second insulating layer 150 and a conductive layer 160 which are stacked in sequence, and the conductive layer 160 electrically connects the first metal layer 120 with the second metal layer 140 through a first via hole 170 and a second via hole 180. Specifically, the first metal layer 120 is arranged on one side of the base substrate 110; the first insulating layer 130 is arranged on the side of the first metal layer 120 away from the base substrate 110; the second metal layer 140 is arranged on the side of the first insulating layer 130 away from the first metal layer 120; the second insulating layer 150 is arranged on the side of the second metal layer 140 away from the first insulating layer 130; the first via 170 penetrates the second insulating layer 150, the second metal layer 140 and the first insulating layer 130, exposing a portion of the first metal layer 120; the second via 180 penetrates the second insulating layer 150, exposing a portion of the second metal layer 140; the conductive layer 160 is arranged on the side of the second insulating layer 150 away from the first metal layer 120, and covers the first via 170 and the second via 180, so as to electrically connect the first metal layer 120 with the second metal layer 140.

[0033] In the array substrate 100, the first metal layer 120, the second metal layer 140 and the conductive layer 160 together constitute the first common electrode 104. Since the first common electrode 104 includes two metal layers, it is equivalent to reducing the width of the current common electrode routing by half, thereby reducing the width of the black matrix and realizing a narrow frame design. It is understandable that the first common electrode 104 in the present application can include multiple metal layers, not limited to the two metal layers in the present embodiment. For example, when the first common electrode 104 includes multiple metal layers, the conductive layer 160 is also overlapped with multiple metal layers through corresponding layers of vias, thereby reducing the width of the current common electrode routing to be smaller. It is understandable that the first common electrode 104 of this structure can ensure that the resistance and capacitance in the common electrode routing area 1022 remain unchanged, avoiding the influence on the voltage distribution on the color filter substrate arranged opposite to the array substrate 100, so that the display quality of the display panel remains unchanged, and the ultra-narrow frame design is realized. It can be understood that the first metal layer 120 , the first insulating layer 130 , the second metal layer 140 and the second insulating layer 150 can be prepared simultaneously with the inner film layer of the display area 101 .

[0034] Please refer to Figure 1 and Figure 3 In some embodiments of the present application, the array substrate 100 further includes a third via hole 190, the third via hole 190 penetrates the second metal layer 140 and the first insulating layer 130, and exposes a portion of the first metal layer 120; wherein the second metal layer 140 is electrically connected to the second metal layer 140 through the third via hole 190. Further, as Figure 4 As shown, in some embodiments of the present application, the array substrate 100 also includes: a conductive connection layer 161, which is arranged on the side of the second metal layer 140 away from the first metal layer 120 and covers the third via 190 to electrically connect the first metal layer 120 with the second metal layer 140.

[0035] Optionally, in some embodiments of the present application, the thickness of the second metal layer 140 (the vertical distance between the side of the second metal layer 140 close to the base substrate 110 and the side of the second metal layer 140 away from the base substrate 110) is less than or equal to the thickness of the first metal layer 120 (the vertical distance between the side of the first metal layer 120 close to the base substrate 110 and the side of the first metal layer 120 away from the base substrate 110). The width of the second metal layer 140 is less than or equal to the width of the first metal layer 120. The width of the second metal layer 140 and the first metal layer 120 can be substantially the same as the width of the common electrode wiring area 1022. The thickness of the first metal layer 120 is 0.04 μm to 0.5 μm, for example, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, etc.; the width of the first metal layer 120 is 25 μm to 1200 μm; For example: 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm, 800μm, 850μm, 900μm, 950μm, 1000μm, 1050μm, 1100μm, 1150μm. The thickness of the second metal layer 140 is 0.04μm to 0.5μm. The thickness of the second metal layer 140 is 0.04 μm to 0.5 μm, for example, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, etc.; the width of the second metal layer 140 is 25 μm to 1200 μm; For example: 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm m, 650μm, 700μm, 750μm, 800μm, 850μm, 900μm, 950μm, 1000μm, 1050μm, 1100μm, 1150μm.

[0036] In some embodiments of the present application, the first via 170 and the second via 180 have the same size and the same number. The first via 170 is used to provide a connection channel between the conductive layer 160 and the first metal layer 120, and the second via 180 is used to provide a connection channel between the conductive layer 160 and the second metal layer 140. The same size and equal number of the first via 170 and the second via 180 can ensure a more balanced overlap between the first metal layer 120 and the second metal layer 140, and prevent the occurrence of voltage instability caused by excessive or insufficient resistance at a certain point. Furthermore, the provision of the first via 170 and the second via 180 can also increase the area of ​​the first common electrode 104, thereby further reducing the width of the second metal layer 140 and the first metal layer 120 to achieve an ultra-narrow frame. The orthographic projection shapes of the first via hole 170 and the second via hole 180 on the base substrate 110 include, but are not limited to, a circle, a square, a trapezoid, an ellipse and a regular polygon, as long as the total cross-sectional area of ​​the first via hole 170 is roughly equal to the total cross-sectional area of ​​the second via hole 180.

[0037] The first via holes 170 and the second via holes 180 are evenly distributed corresponding to the first metal layer 120 and the second metal layer 140 respectively. That is, the first metal layer 120 exposed by the first via holes 170 is regularly arranged, and the second metal layer 140 exposed by the second via holes 180 is regularly arranged.

[0038] Optionally, in some embodiments of the present application, the conductive layer 160 is a transparent conductive layer, and its material includes indium tin oxide (ITO).

[0039] Please refer to Figures 2 to 10 In an embodiment of the present application, a method for preparing the array substrate 100 is also provided, comprising the following steps:

[0040] See also Figure 5 and Figure 6 Step S1: Provide a base substrate 110, wherein the base substrate 110 has a display area 101, a GOA circuit area 1021 and a common electrode wiring area 1022, wherein the GOA circuit area 1021 is located on both sides of the display area 101, and the common electrode wiring area 1022 surrounds the display area 101 and the GOA circuit area 1021.

[0041] See also Figure 5 and Figure 7 , step S2: depositing a metal material on the base substrate 110 and patterning to form a first metal layer 120 .

[0042] See also Figure 5 and Figure 8 , step S3: depositing an insulating material on the first metal layer 120 , patterning to form a first insulating layer 130 , and exposing a portion of the first metal layer 120 .

[0043] See also Figure 5 and Fig. 9 , step S4: depositing a metal material on the first insulating layer 130 , patterning to form a second metal layer 140 , and exposing a portion of the first metal layer 120 .

[0044] See also Figure 5 and Fig.10 , step S5: depositing an insulating material on the second metal layer 140 , patterning to form a second insulating layer 150 , and exposing a portion of the first metal layer 120 to form a first via 170 , and exposing a portion of the second metal layer 140 to form a second via 180 .

[0045] See also Figure 5 and Figure 2 , step S6: depositing a conductive material on the second insulating layer 150 and patterning to form a conductive layer 160 , wherein the conductive layer 160 covers the first via hole 170 and the second via hole 180 to electrically connect the first metal layer 120 and the second metal layer 140 .

[0046] In this embodiment, the first metal layer 120, the first insulating layer 130, the second metal layer 140, the second insulating layer 150, the conductive layer 160, the first via hole 170, and the second via hole 180 are all located in the common electrode wiring area 1022. The specific preparation of the first metal layer 120, the first insulating layer 130, the second metal layer 140, the second insulating layer 150, the conductive layer 160, the first via hole 170, and the second via hole 180 can be carried out by conventional technical means in the art. In this embodiment, it is sufficient to ensure that the first metal layer 120 and the second metal layer 140 located in the common electrode wiring area 1022 are double-layer designs.

[0047] See also Figure 11 to Figure 12The embodiment of the present application also provides a display panel 10, comprising the array substrate 100 described in any of the above embodiments; a color film substrate 200, arranged opposite to the array substrate; and a sealant 300, wherein the sealant 300 is located between the array substrate 100 and the color film substrate 200; wherein a portion of the sealant 300 is located in the common electrode wiring area 1022 of the array substrate 100, and a conductive gold ball 400 is arranged in the sealant 300, and the conductive gold ball 400 is used to electrically connect the array substrate 100 with the color film substrate 200. Specifically, in the array substrate 100, the first metal layer 120, the second metal layer 140 and the conductive layer 160 together constitute a first common electrode 104; the color film substrate 200 comprises a color film base substrate 210 and a second common electrode 201 arranged on the color film base substrate 210; wherein the conductive gold ball 400 is used to electrically connect the first common electrode 104 with the second common electrode 201. Among them, one end of the conductive gold ball 400 is connected to the second metal layer 140 to achieve connection with the first common electrode 104; the other end of the conductive gold ball 400 is directly connected to the second common electrode 201 to electrically connect the array substrate 100 with the color filter substrate 200.

[0048] The array substrate 100 and the color film substrate 200 described in the embodiment of the present application can be conventional structures in the field, and this application does not limit them. The display panel 10 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. The other essential components of the display panel 10 should be understood by ordinary technicians in the field, and will not be repeated here, nor should they be used as limitations on this application. The implementation of the display panel 10 can refer to the embodiment of the array substrate 100, and the repeated parts will not be repeated.

[0049] In summary, the present application discloses an array substrate 100 and a manufacturing method thereof, and a display panel 10. The array substrate 100 has a display area 101, a GOA circuit area 1021, and a common electrode wiring area 1022. The GOA circuit area 1021 is located on both sides of the display area 101, and the common electrode wiring area 1022 surrounds the display area 101 and the GOA circuit area 1021. In the common electrode wiring area 1022, the array substrate 100 includes a base substrate 110, a first metal layer 120, a first insulating layer 130, a second metal layer 140, a second insulating layer 150, and a conductive layer 160, which are stacked in sequence. The conductive layer 160 electrically connects the first metal layer 120 and the second metal layer 140 through a first via 170 and a second via 180. The metal wiring in the common electrode wiring area 1022 is arranged in multiple layers, which can reduce the width of the common electrode wiring while ensuring the normal operation of the capacitance and resistance of the common electrode wiring. Moreover, the first common electrode 104 of this structure can ensure that the resistance and capacitance in the common electrode wiring area 1022 remain unchanged, thereby avoiding affecting the voltage distribution on the color filter substrate arranged opposite to the array substrate 100, thereby achieving an ultra-narrow frame design while maintaining the display quality of the display panel.

[0050] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0051] The above is a detailed introduction to an array substrate 100 and a preparation method thereof, and a display panel 10 provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises a display area and a non-display area located outside the display area, wherein the non-display area comprises a GOA circuit area and a common electrode wiring area; in In the common electrode wiring area, the array substrate includes: substrate substrate; A first metal layer is disposed on one side of the substrate; A first insulating layer is disposed on a side of the first metal layer away from the substrate; A second metal layer is disposed on a side of the first insulating layer away from the first metal layer; A second insulating layer is disposed on a side of the second metal layer away from the first insulating layer; a first via hole, penetrating the second insulating layer, the second metal layer and the first insulating layer, exposing a portion of the first metal layer; a second via hole, penetrating through the second insulating layer and exposing a portion of the second metal layer; The conductive layer is disposed on a side of the second insulating layer away from the first metal layer and covers the first via hole and the second via hole to electrically connect the first metal layer and the second metal layer.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes: A third via hole penetrates the second metal layer and the first insulating layer to expose a portion of the first metal layer; The second metal layer is electrically connected to the second metal layer through the third via hole.

3. The array substrate according to claim 2, characterized in that: The array substrate further includes: The conductive connection layer is disposed on a side of the second metal layer away from the first metal layer and covers the first via hole to electrically connect the first metal layer with the second metal layer.

4. The array substrate according to claim 1, wherein: The thickness of the second metal layer is less than or equal to the thickness of the first metal layer; The projection of the second metal layer on the base substrate is located within the projection of the first metal layer on the base substrate.

5. The array substrate according to claim 1, wherein: The orthographic projection shapes of the first via hole and the second via hole on the base substrate include at least one of a circle, a square, a trapezoid, an ellipse and a regular polygon.

6. A method for preparing an array substrate, characterized in that: The steps include: Step S1: providing a base substrate, wherein the array substrate has a display area and a non-display area located outside the display area, wherein the non-display area includes a GOA circuit area and a common electrode wiring area; Step S2: depositing a metal material on the substrate and patterning to form a first metal layer; Step S3: depositing an insulating material on the first metal layer, patterning to form a first insulating layer, and exposing a portion of the first metal layer; Step S4: depositing a metal material on the first insulating layer, patterning to form a second metal layer, and exposing a portion of the first metal layer; Step S5: depositing an insulating material on the second metal layer, patterning to form a second insulating layer, and exposing a portion of the first metal layer to form a first via hole, and exposing a portion of the second metal layer to form a second via hole; Step S6: depositing a conductive material on the second insulating layer and patterning to form a conductive layer, wherein the conductive layer covers the first via hole and the second via hole to electrically connect the first metal layer and the second metal layer; wherein the first metal layer, the first insulating layer, the second metal layer, the first via hole, the second via hole and the conductive layer are all located in the common electrode routing area.

7. A display panel, characterized in that: comprising an array substrate as claimed in any one of claims 1 to 5; a color filter substrate, arranged opposite to the array substrate; and Frame sealing glue, the frame sealing glue is located between the array substrate and the color filter substrate; in Part of the frame sealant is located in the non-display area of ​​the array substrate. Conductive gold balls are arranged in the frame sealant. The conductive gold balls are used to electrically connect the array substrate with the color filter substrate.

8. The display panel according to claim 7, wherein: In the array substrate, the first metal layer, the second metal layer and the conductive layer together form a first common electrode; The color filter substrate comprises a color filter substrate and a second common electrode disposed on the color filter substrate; in The conductive gold ball is used to electrically connect the first common electrode and the second common electrode.

Images