An asynchronous master-slave self-clocked data change detector

Abstract

The present invention relates to an asynchronous master-slave self-clocked data change detector, and relates to the technical field of clock detection. In the asynchronous master-slave self-clocked data change detector, the output ends of the master latch are respectively connected to the input ends of the slave latch and the multi-input exclusive-OR gate, the enable input end of the master latch is connected to the enable output end of the multi-input exclusive-OR gate, the output end of the slave latch is connected to the input end of the multi-input exclusive-OR gate, and the enable input end of the slave latch is connected to the enable output end of the multi-input exclusive-OR gate. The self-clocked data change detector of the present invention has a simple and fixed structure, does not generate glitches and is insensitive to the glitches of the input data, thereby improving the correctness of the state machine function, and does not require a narrow pulse generation module to generate a self-clocked signal, thereby reducing the hardware overhead.

Description

Technical Field

[0001] The present invention relates to the technical field of clock detection, and particularly to an asynchronous master-slave self-clocking data change detector. Background Art

[0002] At present, the self-clocking module of the existing self-clocking state machine generates a self-clocking signal by determining the change of input data. The circuit logic structure is generated by the state transition table of the corresponding state machine specific function. The circuit structure is not fixed, the design is not universal, and it is sensitive to the glitches of the input data, resulting in mis-triggering of state transitions, and further affecting the functional correctness of the state machine. And for the existing input change detection circuit, although it realizes the detection of input data changes, the detection point of the input data is the input of the register. Therefore, a narrow pulse generation module is required to reset the self-clocking output signal that has become high level. However, the narrow pulse generation module cannot be described at the behavioral level by HDL, and it increases the additional hardware overhead. Summary of the Invention

[0003] The purpose of the present invention is to provide an asynchronous master-slave self-clocking data change detector, which has a simple and fixed structure, does not generate glitches and is not sensitive to the glitches of input data, thereby improving the functional correctness of the state machine, and does not require a narrow pulse generation module to generate a self-clocking signal, thereby reducing the hardware overhead.

[0004] To achieve the above purpose, the present invention provides the following solutions:

[0005] An asynchronous master-slave self-clocking data change detector includes:

[0006] A master latch, a slave latch and a multi-input exclusive-OR gate; the output end of the master latch is respectively connected to the input end of the slave latch and the input end of the multi-input exclusive-OR gate, the enable input end of the master latch is connected to the enable output end of the multi-input exclusive-OR gate, the output end of the slave latch is connected to the input end of the multi-input exclusive-OR gate, and the enable input end of the slave latch is connected to the enable output end of the multi-input exclusive-OR gate.

[0007] Optionally, the bit width of the multi-input exclusive-OR gate is N bits.

[0008] Optionally, the multi-input exclusive-OR gate includes: N two-input exclusive-OR gates and one N-input OR gate; the input ends of the N two-input exclusive-OR gates are the input ends of the multi-input exclusive-OR gate, the output ends of the N two-input exclusive-OR gates are all connected to the input end of the N-input OR gate, and the output end of the N-input OR gate is the enable output end of the multi-input exclusive-OR gate.

[0009] According to the specific embodiments provided by the present invention, the following technical effects are disclosed: The asynchronous master-slave self-clocked data change detector of the present invention includes: a master latch, a slave latch, and a multi-input XOR gate; the output terminal of the master latch is respectively connected to the input terminal of the slave latch and the input terminal of the multi-input XOR gate, the enable input terminal of the master latch is connected to the enable output terminal of the multi-input XOR gate, the output terminal of the slave latch is connected to the input terminal of the multi-input XOR gate, and the enable input terminal of the slave latch is connected to the enable output terminal of the multi-input XOR gate. Based on the master-slave latches and XOR gate, the asynchronous self-clocked generator generated based on the state transition table method has the advantages of simple and fixed structure, no glitches generated, fast response speed, and insensitivity to input data glitches, improving the correctness of the state machine function. Compared with the input change detection circuit, a master-slave structure is added, so there is no need to generate a self-clocked signal through a narrow pulse generation module circuit, which can reduce the hardware overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0011] Figure 1 FIG. is a schematic structural diagram of an asynchronous master-slave self-clocked data change detector provided by an embodiment of the present invention;

[0012] Figure 2 FIG. is a schematic structural diagram of a multi-input XOR gate provided by an embodiment of the present invention.

[0013] Symbol Description:

[0014] Phase-1 - master latch, Phase-2 - slave latch, Fire - multi-input XOR gate, DI - input terminal of the master latch, D - output terminal of the master latch, DO - output terminal of the slave latch, E - enable output terminal of the multi-input XOR gate. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0016] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0017] The present invention discloses a data change detector based on master-slave latches and exclusive-OR gates that can generate asynchronous self-clocking signals, as Figure 1 shown, which includes a master latch Phase-1, a slave latch Phase-2, and a multi-input exclusive-OR gate Fire; the input end of the master latch is the input end of the asynchronous master-slave self-clocking data change detector, the output end D of the master latch is respectively connected to the input end of the slave latch Phase-2 and the input end of the multi-input exclusive-OR gate Fire, the enable input end of the master latch Phase-1 is connected to the enable output end E of the multi-input exclusive-OR gate, the output end DO of the slave latch is connected to the input end of the multi-input exclusive-OR gate Fire, the enable input end of the slave latch Phase-2 is connected to the enable output end E of the multi-input exclusive-OR gate, and the enable output end E of the multi-input exclusive-OR gate is the output end of the asynchronous master-slave self-clocking data change detector. Specifically: for the master latch Phase-1, the data input is connected to the input end DI of the latch, D is connected to the data input end of the slave latch Phase-2 and the data input end of the multi-input exclusive-OR gate Fire, and the enable input is connected to the enable output end E of the multi-input exclusive-OR gate. For the slave latch Phase-2, the data input is connected to D, the data output is connected to DO and the data input of the multi-input exclusive-OR gate Fire, and the enable input is connected to the enable output end E of the multi-input exclusive-OR gate. For the multi-input exclusive-OR gate Fire, the data input is connected to D and DO, and E is connected to the enable input of the master latch Phase-1 and the enable input of the slave latch Phase-2.

[0018] In practical applications, the bit width of the multi-input exclusive-OR gate Fire is N bits.

[0019] In practical applications, as Figure 2 shown, the multi-input exclusive-OR gate Fire includes: N two-input exclusive-OR gates and one N-input OR gate; the input ends of the N two-input exclusive-OR gates are the input ends of the multi-input exclusive-OR gate Fire, the output ends of the N two-input exclusive-OR gates are all connected to the input end of the N-input OR gate, the output end of the N-input OR gate is the enable output end E of the multi-input exclusive-OR gate, and the N two-input exclusive-OR gates respectively compare whether there are differences between the corresponding-bit input data D and output data DO, and the comparison results generate the self-clocking enable output E through the N-input OR gate.

[0020] The present invention discloses an asynchronous master-slave self-clocked data change detector, which is mainly used for generating self-clocked signals of an asynchronous state machine, detecting input data changes and filtering out glitches. The specific functions are as follows. When the DI and DO of the asynchronous master-slave self-clocked data change detector provided by the present invention are the same, the asynchronous master-slave self-clocked data change detector provided by the present invention is in the loading state (phase 1). At this time, the master latch Phase-1 is in the conducting state, and the slave latch Phase-2 is in the latching state. When DI changes and is different from the current output data, the input data reaches its output D through the master latch Phase-1. At this time, the enable output terminal E of the multi-input XOR gate generates a high level to latch the master latch Phase-1, and the slave latch Phase-2 conducts. The asynchronous master-slave self-clocked data change detector provided by the present invention enters the firing state (phase 2). When the data is transmitted to DO through the conduction of the slave latch Phase-2, the enable output terminal E of the multi-input XOR gate generates a low level to make the master latch Phase-1 conduct and the slave latch Phase-2 latch. The asynchronous master-slave self-clocked data change detector provided by the present invention returns to the loading state again. The pulse output generated by the enable output terminal E of the multi-input XOR gate in the above process is the self-clocked signal bundled with the changing data.

[0021] Since there are delays in the data input to output when the master latch Phase-1 conducts, the data input to output when the slave latch Phase-2 conducts, and the data input to the enable output of the multi-input XOR gate Fire, by adjusting the delay magnitude on the enable output terminal E of the multi-input XOR gate, glitches in the data input can be filtered out, and the detector can be insensitive to glitch data below a certain width, thereby also playing a role in low-pass filtering of the input data.

[0022] Since the path lengths from each input to output of the multi-input XOR gate Fire are equal, the self-clocked signal output of the multi-input XOR gate Fire will not generate glitches.

[0023] The present invention has the following technical effects:

[0024] Compared with the asynchronous self-clocked generator generated based on the state transition table method, it has the advantages of simple and fixed structure, no generation of glitches, fast response speed and insensitivity to input data glitches, improving the correctness of the state machine function. Compared with the input change detection circuit, it adds a master-slave structure, so there is no need to generate a self-clocked signal through a narrow pulse generation module circuit, reducing the hardware overhead.

[0025] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0026] In this text, specific examples are used to illustrate the principles and implementation modes of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation modes and application scopes. To sum up, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An asynchronous master-slave self-clocked data change detector, Characterized in that, Comprising: A master latch, a slave latch and a multi-input exclusive-OR gate; the output end of the master latch is respectively connected to the input end of the slave latch and the input end of the multi-input exclusive-OR gate, the enable input end of the master latch is connected to the enable output end of the multi-input exclusive-OR gate, the output end of the slave latch is connected to the input end of the multi-input exclusive-OR gate, and the enable input end of the slave latch is connected to the enable output end of the multi-input exclusive-OR gate; when the input end of the master latch changes and is different from the current output data, the input data reaches the output end of the master latch through the master latch, at this time the enable output end of the multi-input exclusive-OR gate generates a high level to lock the master latch and turn on the slave latch; when the input data is transmitted to the output end of the slave latch through the conduction of the slave latch, the enable output end of the multi-input exclusive-OR gate generates a low level to turn on the master latch and lock the slave latch.

2. The asynchronous master-slave self-clocked data change detector according to claim 1, Characterized in that, The bit width of the multi-input exclusive-OR gate is N bits.

3. The asynchronous master-slave self-clocked data change detector according to claim 2, Characterized in that, The multi-input exclusive-OR gate includes: N two-input exclusive-OR gates and one N-input OR gate; the input ends of the N two-input exclusive-OR gates are the input ends of the multi-input exclusive-OR gate, the output ends of the N two-input exclusive-OR gates are all connected to the input end of the N-input OR gate, and the output end of the N-input OR gate is the enable output end of the multi-input exclusive-OR gate.

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