A low-voltage transformer area topology generation method and system

Abstract

The application provides a low-voltage transformer area topology generation method and system, obtains current values of all circuit breakers at the same time point; according to the principle that the upper layer current is equal to the sum of the lower layer currents, recursively processes all circuit breaker data, generates all possible topology relations, and records the occurrence probability of the topology relations; the above calculation is repeated at the next time point, and after a preset time, the topology relation with the maximum occurrence probability is the final topology relation; the application uses the recursive calling method, repeatedly calls, uses less calculation logic, and can quickly calculate all topology relations of different levels under the premise of ensuring the accuracy of topology generation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of transformer area topology calculation, and particularly relates to a low-voltage transformer area topology generation method and system. BACKGROUND

[0002] The statements in this section merely provide background technology related to the present application and do not necessarily constitute prior art.

[0003] There is an increasingly urgent demand for transformer area topology. With the progress of technology, new equipment already has the function of topology identification, but there is also a demand for topology calculation for previous equipment.

[0004] The inventor found that the wiring of the previously existing equipment mostly experienced multiple improvements or changes, and the topology structure is complex, so it is difficult to obtain accurate topology relationship in an artificial way; the existing automatic topology generation method is mostly committed to setting the optimization of the model in the scene to obtain accurate results, and often cannot efficiently and accurately identify the topology of the equipment in various application scenarios. SUMMARY

[0005] In order to solve the problems of the prior art, the present application provides a low-voltage transformer area topology generation method and system, which uses a recursive calling method, repeatedly calls, and only uses less calculation logic, so that the topology relationship of different levels can be quickly calculated under the premise of ensuring the accuracy of topology generation.

[0006] In order to achieve the above purpose, the present application adopts the following technical scheme:

[0007] The first aspect of the present application provides a low-voltage transformer area topology generation method.

[0008] A low-voltage transformer area topology generation method comprises the following processes:

[0009] Obtain the current value of all circuit breakers at the same time point;

[0010] According to the principle that the current of the upper layer is equal to the sum of the currents of the lower layers, recursively process all circuit breaker data to generate all possible topology relationships, and record the occurrence probability of the topology relationship;

[0011] Repeat the above calculation at the next time point, and after a preset time, the topology relationship with the largest occurrence probability is the final topology relationship.

[0012] The second aspect of the present application provides a low-voltage transformer area topology generation system.

[0013] A low-voltage transformer area topology generation system comprises:

[0014] A data acquisition module is configured to acquire current values of all circuit breakers at the same time point.

[0015] A topology calculation module is configured to recursively process all circuit breaker data according to the principle that the upper-layer current is equal to the sum of the lower-layer currents, generate all possible topology relations, and record the occurrence probability of the topology relations.

[0016] A topology generation module is configured to repeat the above calculation at the next time point, and after a preset time, the topology relation with the maximum occurrence probability is the final topology relation.

[0017] The third aspect of the present application provides a computer readable storage medium having a program stored thereon, which, when executed by a processor, implements the steps of the low-voltage area topology generation method according to the first aspect of the present application.

[0018] The fourth aspect of the present application provides an electronic device comprising a memory, a processor, and a program stored on the memory and executable on the processor, wherein the processor implements the steps of the low-voltage area topology generation method according to the first aspect of the present application when executing the program.

[0019] Compared with the prior art, the present application has the following advantages:

[0020] 1. The low-voltage area topology generation method and system according to the present application use recursive calling method, and through repeated calling, only a small amount of calculation logic is used to quickly calculate all topology relations of different levels under the premise of ensuring the accuracy of topology generation.

[0021] 2. The low-voltage area topology generation method and system according to the present application recursively process all circuit breaker data according to the principle that the upper-layer current is equal to the sum of the lower-layer currents, generate all possible topology relations, and record the occurrence probability of the topology relations, and after a preset time, the topology relation with the maximum occurrence probability is the final topology relation, thereby improving the accuracy of the topology result.

[0022] 3. The low-voltage area topology generation method and system according to the present application consider the case that the first node is empty, remove the first node of the current child node set as a leaf set, and repeat the judgment step of whether there is a leaf node set; all leaf nodes of the lowest layer of the current topology structure are acquired as a leaf node set, and the judgment step of whether there is a leaf node set is repeated, thereby further improving the accuracy and comprehensiveness of the topology result. BRIEF DESCRIPTION OF DRAWINGS

[0023] The drawings accompanying the specification of the present application form a part thereof, serve to provide further understanding of the present application, and together with the exemplary embodiments of the present application and their description, serve to explain the present application, and do not constitute improper limitations on the present application.

[0024] Figure 1 The flowchart of the low-voltage transformer area topology generation method provided by the embodiment 1 of the present application is shown. DETAILED DESCRIPTION

[0025] The present application is further described below in conjunction with the accompanying drawings and embodiments.

[0026] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0027] It should be noted that the terms used herein are only intended to describe specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and it should be further understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of the features, steps, operations, devices, components and / or combinations thereof.

[0028] The embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0029] Embodiment 1

[0030] As shown in Figure 1 The embodiment 1 of the present application provides a low-voltage transformer area topology generation method, which includes the following processes:

[0031] Obtain the current values of all circuit breakers at the same time point;

[0032] According to the principle that the upper-layer current is equal to the sum of the lower-layer currents, recursively process all circuit breaker data to generate all possible topology relationships, and record the occurrence probability of the topology relationship;

[0033] Repeat the above calculation at the next time point, and after a preset time, the topology relationship with the largest occurrence probability is the final topology relationship.

[0034] Specifically, it includes the following processes:

[0035] A1: Collect all circuit breaker current values at the moment.

[0036] A2: Sort all current values from large to small.

[0037] A3: The largest one is the root node.

[0038] A4: From the remaining short-circuiters, calculate the sum of one, two,... n currents equal to the sum of the current of the previous level, and record each possibility as a leaf node set.

[0039] A5: If there is a leaf node set, there is a possibility of forming a topological relationship under this node, and each leaf node set is taken for the next step of calculation; if not, exit the calculation.

[0040] A6: Take the leaf node set as the child node of the previous level, generate a topological relationship, and remove the data in the topological relationship from the entire set as a child set.

[0041] A7: From the remaining short-circuiters, calculate the sum of one, two,... n currents equal to the sum of the current of the previous level, and record each possibility as a leaf node set.

[0042] A8: If there is a leaf node set, process the leaf node set respectively, take each leaf node set as a leaf node, generate a topological relationship, and remove the data in the topological relationship from the remaining set as a remaining set. If there is no leaf node set, it means that it is impossible to generate a topological relationship. Then go to A5 for processing.

[0043] A9: If the remaining set is empty, it means that the data has been fully used, and the topological relationship is the possible topological relationship, and the topological relationship is recorded.

[0044] A10: Take the next node of the child node for calculation.

[0045] A11: If there is no next child node, it means that the level calculation is complete.

[0046] A12: The first node should also be considered empty. Remove the first node of the current child node set as a leaf set and repeat the operation of A5.

[0047] A13: Take all the leaf nodes of the lowest level of the current topological structure as a leaf node set and repeat the operation of A5.

[0048] A14: After all the processing is completed, compare the newly generated topological relationship with the historical topological relationship. If the topological relationship exists, the count of the historical topological relationship is increased. If it does not exist, the topological relationship is added to the historical topological relationship.

[0049] A15: Repeat the operation at the next time period.

[0050] A16: With the passage of time, the most probable one is the actual topological relationship.

[0051] Example 2:

[0052] The embodiment 2 of the present application provides a low-voltage area topology generation system, comprising:

[0053] The data acquisition module is configured to acquire current values of all circuit breakers at the same time point.

[0054] The topology calculation module is configured to recursively process all circuit breaker data according to the principle that the upper-layer current is equal to the sum of the lower-layer currents, generate all possible topology relations, and record the occurrence probability of the topology relations.

[0055] The topology generation module is configured to repeat the above calculation at the next time point, and after a preset time, the topology relation with the largest occurrence probability is the final topology relation.

[0056] The topology calculation module specifically comprises:

[0057] All current values are sorted in descending order.

[0058] The largest one is the root node.

[0059] From the remaining circuit breakers, the sum of one, two, …, n currents equal to the sum of the upper-level currents is calculated, and each possibility is recorded as a leaf node set.

[0060] If there is a leaf node set, the node may form a topology relation, and each leaf node set is taken for the next step of calculation; if not, the calculation is exited.

[0061] The leaf node set is taken as the child node of the upper level, a topology relation is generated, and the data in the topology relation is removed from the whole set as a child set.

[0062] From the remaining circuit breakers, the sum of one, two, …, n currents equal to the sum of the upper-level currents is calculated, and each possibility is recorded as a leaf node set.

[0063] If there is a leaf node set, the leaf node set is processed respectively, taken as the leaf node of the leaf node, a topology relation is generated, and the remaining set removes the data in the topology relation as the remaining set; if there is no leaf node set, it indicates that the topology relation cannot be generated; then it is judged whether there is a leaf node set.

[0064] If the remaining set is empty, it indicates that the data has been used up, the topology relation is taken as the possible topology relation, and the topology relation is recorded.

[0065] The next node of the child node is taken for calculation.

[0066] If there is no next child node, it indicates that the level calculation is completed.

[0067] Also consider the case that the first node is empty, remove the first node of the current sub-node set as a leaf set, repeat the judging step of whether there is a leaf node set.

[0068] Get all the lowest level leaf nodes of the current topology structure as a leaf node set, repeat the judging step of whether there is a leaf node set.

[0069] After all the processing is completed, compare the newly generated topology relationship with the historical topology relationship, if the topology relationship exists, the historical topology relationship count is increased. If it does not exist, the topology relationship is added in the historical topology relationship.

[0070] Embodiment 3

[0071] Embodiment 3 of the present application provides a computer readable storage medium, which stores a program, the program is executed by a processor to realize the following steps:

[0072] B1: collect all short-circuit current values at the moment.

[0073] B2: sort all current values in descending order.

[0074] B3: the largest one is the root node.

[0075] B4: from the remaining short-circuiters, respectively calculate one, two…n current sum equal to the current sum of the previous level, each possibility is recorded as a leaf node set.

[0076] B5: if there is a leaf node set, the node may form a topology relationship, respectively take each leaf node set to calculate the next step. If not, exit the calculation.

[0077] B6: take the leaf node set as the sub-node of the previous level to generate a topology relationship, remove the data in the topology relationship from the entire set as a sub-set.

[0078] B7: from the remaining short-circuiters, respectively calculate one, two…n current sum equal to the current sum of the previous level, each possibility is recorded as a leaf node set.

[0079] B8: if there is a leaf node set, respectively process the leaf node set, respectively as a leaf node, generate a topology relationship, remove the data in the topology relationship from the remaining set as a remaining set. If there is no leaf node set, it means that the topology relationship cannot be generated. Then go to B5 for processing.

[0080] B9: if the remaining set is empty, it means that the data has been used up, change the topology relationship to the possible topology relationship, and record the topology relationship.

[0081] B10: take the next node of the sub-node to calculate.

[0082] B11: if there is no next sub-node, it means that the level calculation is completed.

[0083] B12: the first node is also considered to be empty, the first node of the current sub-node set is removed as a leaf set, and the operation of B5 is repeated.

[0084] B13: all the leaf nodes of the lowest layer of the current topology structure are obtained as a leaf node set, and the operation of B5 is repeated.

[0085] B14: after all the processing is completed, the newly generated topology relationship is compared with the historical topology relationship, if the topology relationship exists, the historical topology relationship count is increased. If it does not exist, the topology relationship is added in the historical topology relationship.

[0086] B15: wait for the next time period to repeat the operation.

[0087] B16: over time, the probability of the largest is the actual topology relationship.

[0088] Embodiment 4:

[0089] Embodiment 4 of the application: an electronic device is provided, comprising a memory, a processor and a program stored in the memory and executable on the processor, when the processor executes the program, the following steps are implemented:

[0090] C1: collect all short-circuit current values at this moment.

[0091] C2: sort all current values in descending order.

[0092] C3: the largest one is the root node.

[0093] C4: from the remaining short-circuiters, calculate the sum of one, two, …, n currents equal to the sum of the current of the previous level, and record each possibility as a leaf node set.

[0094] C5: if there is a leaf node set, there is a possibility of forming a topology relationship under the node, and each leaf node set is taken for further calculation. If not, exit the calculation.

[0095] C6: take the leaf node set as the sub-node of the previous level to generate a topology relationship, and remove the data in the topology relationship from the entire set as a sub-set.

[0096] C7: from the remaining short-circuiters, calculate the sum of one, two, …, n currents equal to the sum of the current of the previous level, and record each possibility as a leaf node set.

[0097] C8: If there is a leaf node set, process the leaf node set respectively, generate a topology relationship as a leaf node, and remove the data in the topology relationship from the remaining set as a remaining set. If there is no leaf node set, it indicates that the topology relationship cannot be generated. Then, go to C5 for processing.

[0098] C9: If the remaining set is empty, it indicates that the data has been used up. Change the topology relationship to a possible topology relationship, and record the topology relationship.

[0099] C10: Take the next node of the child node for calculation.

[0100] C11: If there is no next child node, it indicates that the level calculation is completed.

[0101] C12: The first node should also be considered to be empty. Remove the first node of the current child node set as a leaf set, and repeat the operation of C5.

[0102] C13: Take all the leaf nodes of the lowest level of the current topology structure as a leaf node set, and repeat the operation of C5.

[0103] C14: After all the processing is completed, compare the newly generated topology relationship with the historical topology relationship. If the topology relationship exists, the historical topology relationship count is increased. If the topology relationship does not exist, the topology relationship is added to the historical topology relationship.

[0104] C15: Wait for the next time period to repeat the operation.

[0105] C16: With the passage of time, the most probable one is the actual topology relationship.

[0106] Those skilled in the art will understand that embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0107] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0108] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0109] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0110] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0111] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for generating a low-voltage distribution area topology, characterized in that: The process includes the following: Obtain the current values ​​of all circuit breakers at the same point in time; Based on the principle that the current in the upper layer is equal to the sum of the currents in the lower layer, all circuit breaker data are processed recursively to generate all possible topological relationships and record the probability of occurrence of the topological relationships. Repeat the above calculation at the next time point. After the preset time, the topological relationship with the highest probability of occurrence will be the final topological relationship. Recursively process all circuit breaker data to generate all possible topology relationships, including: Sort all current values ​​from largest to smallest. The circuit breaker with the largest current value is the root node. From the remaining circuit breakers, calculate the possibilities where the sum of multiple currents equals the sum of the currents of the previous level. Record each possibility as a leaf node set. If there is a leaf node set, then the nodes may form a topological relationship. Take each leaf node set for the next step of calculation; otherwise, exit the calculation. When the first node of a current leaf node set is empty, remove the first node of the current child node set and use it as the leaf set, and repeat the step of determining whether there is a leaf node set.

2. The low-voltage distribution area topology generation method as described in claim 1, characterized in that: The set of leaf nodes is used as the child nodes of the parent level to generate a topological relationship. Data in this topological relationship is removed from the entire set and used as a subset. From the remaining circuit breakers, calculate the possibilities that the sum of 1, 2, ... n currents equals the sum of the currents in the previous stage, and record each possibility as a set of leaf nodes; If there is a set of leaf nodes, process the leaf node combinations separately, and use them as leaf nodes of leaf nodes to generate a topological relationship. Remove the data in the topological relationship from the remaining set and use it as the remaining set. If there is no set of leaf nodes, it means that a topological relationship cannot be generated. Then return to the step of determining whether there is a set of leaf nodes.

3. The low-voltage distribution area topology generation method as described in claim 2, characterized in that: If the remaining set is empty, it means that all the data has been used. This topological relationship is a possible topological relationship, and this topological relationship should be recorded. Calculate the next node of the child node. If there is no next child node, it means that the calculation of this level is complete.

4. The low-voltage distribution area topology generation method as described in claim 1, characterized in that: Obtain all leaf nodes of the lowest level of the current topology as a leaf node set, and repeat the step of determining whether there is a leaf node set. After all processing is complete, the newly generated topological relation is compared with the historical topological relation. If the topological relation exists, the count of the historical topological relation is increased; if it does not exist, the topological relation is added to the historical topological relation list.

5. A low-voltage distribution area topology generation system, characterized in that: include: The data acquisition module is configured to acquire the current values ​​of all circuit breakers at the same time point. The topology calculation module is configured to recursively process all circuit breaker data based on the principle that the upper-level current equals the sum of the lower-level currents, generate all possible topological relationships, and record the probability of occurrence of the topological relationships. The topology generation module is configured to repeat the above calculation at the next time point, and after a preset time, the topology relationship with the highest probability of occurrence is the final topology relationship. In the topology calculation module, all circuit breaker data is processed recursively to generate all possible topology relationships, including: Sort all current values ​​from largest to smallest. The circuit breaker with the largest current value is the root node. From the remaining circuit breakers, calculate the possibilities where the sum of multiple currents equals the sum of the currents of the previous level. Record each possibility as a leaf node set. If there is a leaf node set, then the nodes may form a topological relationship. Take each leaf node set for the next step of calculation; otherwise, exit the calculation. When the first node of a current leaf node set is empty, remove the first node of the current child node set and use it as the leaf set, and repeat the step of determining whether there is a leaf node set.

6. The low-voltage distribution area topology generation system as described in claim 5, characterized in that: The topology calculation module is also configured as follows: The set of leaf nodes is used as the child nodes of the next higher level to generate a topological relationship. Data in this topological relationship is removed from the entire set and used as a subset. From the remaining circuit breakers, calculate the possibilities that the sum of 1, 2, ... n currents equals the sum of the currents in the previous stage, and record each possibility as a set of leaf nodes; If there is a set of leaf nodes, process the leaf node combinations separately, and use them as leaf nodes of leaf nodes to generate a topological relationship. Remove the data in the topological relationship from the remaining set and use it as the remaining set. If there is no set of leaf nodes, it means that a topological relationship cannot be generated. Then return to the step of determining whether there is a set of leaf nodes. If the remaining set is empty, it means that all the data has been used. Change the topological relationship to the possible topological relationship and record the changed topological relationship. Take the next node of the child node for calculation. If there is no next child node, it means that the calculation of this level is complete. Obtain all leaf nodes of the lowest level of the current topology as a leaf node set, and repeat the step of determining whether there is a leaf node set. After all processing is complete, the newly generated topological relation is compared with the historical topological relation. If the topological relation exists, the count of the historical topological relation is increased; if it does not exist, the topological relation is added to the historical topological relation list.

7. A computer-readable storage medium having a program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the low-voltage distribution area topology generation method as described in any one of claims 1-4.

8. An electronic device comprising a memory, a processor, and a program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the low-voltage substation topology generation as described in any one of claims 1-4.

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