Semiconductor circuit layout method and preparation method

Abstract

The present invention provides a layout method and a preparation method for a semiconductor circuit. In the layout method, the process parameters of a first isolation groove on the first side of a contact hole are adjusted according to the process parameters of the contact hole, so that the first isolation groove is expanded laterally from the contact hole to outside the contact hole, so that the isolation range of the first isolation groove can better cover the top corner position of the contact hole, avoiding the problem of short circuit between the contact plug in the contact hole and the adjacent interconnection line, and effectively improving the process window for the circuit layout.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a layout method and a preparation method of a semiconductor circuit. Background Art

[0002] In the semiconductor field, the number of components in high-efficiency, high-density integrated circuits has risen to tens of millions, and the signal integration and transmission of these huge numbers of components need to be realized through semiconductor circuits. With the continuous development of semiconductor technology, the miniaturization of integrated circuits has also become a trend, requiring smaller size and higher density circuit layout, and small size and high density circuit design also has higher requirements for processing accuracy to ensure that the formed semiconductor circuit meets the requirements.

[0003] However, in the actual processing, process errors are still inevitable, which will more easily cause defects (for example, circuit short circuits and other problems) for small-sized and high-density circuits. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor circuit layout method to solve the problem of a small process window of circuit layout.

[0005] In order to solve the above technical problems, the present invention provides a layout method for semiconductor circuits, including: providing a circuit layout, the circuit layout including: a gate circuit, a contact hole connected to the gate circuit, a conductive material layer filling the contact hole and covering the gate circuit, and a plurality of isolation grooves distributed in the conductive material layer, used to divide the conductive material layer into a first interconnection line connected to the contact plug and a plurality of second interconnections of uniform size; and confirming the process parameters of the contact hole, and confirming the process parameters of the isolation groove according to the process parameters of the contact hole, so that the sizes of the plurality of isolation grooves and the plurality of interconnections are unevenly distributed. Wherein, confirming the process parameters of the isolation groove includes: adjusting the first isolation groove located on the first side of the contact hole according to the position of the contact hole, so that the first isolation groove located on the first side of the contact hole is set at the edge of the contact hole and extends outside the contact hole, so as to separate the contact plug in the contact hole and the adjacent second interconnection line at the edge of the contact hole.

[0006] Optionally, confirming the process parameters of the isolation trench further includes: adjusting a first isolation trench on a first side of the contact hole according to a size of the contact hole.

[0007] Optionally, confirming the process parameters of the isolation trench further includes: adjusting the size and position of the first isolation trench on the first side of the contact hole.

[0008] Optionally, the position of the first isolation trench on the first side of the contact hole is adjusted so that half of the size of the first isolation trench exceeds the contact hole.

[0009] Optionally, according to the width of the contact hole, the width of the first isolation groove on the first side of the contact hole is adjusted to be smaller than the width of the contact hole.

[0010] Optionally, confirming the process parameters of the isolation trench also includes: adjusting the width of the first isolation trench on the first side of the contact hole according to the lateral width of the top expansion of the contact hole, so that the width of the first isolation trench is greater than the lateral width of the top expansion of the contact hole.

[0011] Optionally, confirming the process parameters of the isolation trench also includes: adjusting the depth of the first isolation trench on the first side of the contact hole according to the longitudinal depth of the outward expansion portion at the top of the contact hole, so that the depth of the first isolation trench is lower than the longitudinal depth of the outward expansion portion of the contact hole.

[0012] Optionally, a first interconnection line connected to the contact plug extends from a second side of the contact hole, and the first side and the second side are two opposite sides of the contact hole respectively.

[0013] Optionally, confirming the process parameters of the isolation trench further includes: adjusting the size of the second isolation trench according to the design sizes of the first interconnection line and the second interconnection line, the second isolation trench being used to separate adjacent second interconnection lines.

[0014] Optionally, the width of the first isolation trench is adjusted to be greater than the width of the second isolation trench.

[0015] The present invention also provides a method for preparing a semiconductor circuit, comprising: obtaining a semiconductor circuit layout using the layout method described above, and forming a semiconductor circuit on a substrate based on the semiconductor circuit layout. The method for preparing a semiconductor circuit based on the semiconductor circuit layout comprises: forming a dielectric layer on a substrate, and forming a contact hole in the dielectric layer; forming a conductive material layer, the conductive material layer filling the contact hole and covering the top surface of the dielectric layer; and forming a plurality of isolation grooves in the conductive material layer to divide the conductive material layer into a first interconnection line connected to a contact plug and a plurality of second interconnections of uniform size; wherein the plurality of isolation grooves include a first isolation groove located above the edge of the first side of the contact hole, the first isolation groove also extending laterally into the dielectric layer, and used to separate the contact plug in the contact hole and the adjacent interconnection line at the edge of the first side of the contact hole.

[0016] Optionally, the method for preparing a semiconductor circuit further includes: filling an insulating material layer into the isolation groove.

[0017] In the layout method of the semiconductor circuit provided by the present invention, a first isolation groove is provided on one side (i.e., the first side) of the contact hole to separate the contact plug in the contact hole and the adjacent interconnection line. In addition, for the first isolation groove on the first side of the contact hole, the process parameters of the first isolation groove are also adjusted according to the process parameters of the contact hole to optimize the isolation performance of the first isolation groove. Among them, the adjustment method for the first isolation groove on the first side of the contact hole includes: expanding the first isolation groove from the contact hole to the outside of the contact hole laterally, so that the isolation range of the first isolation groove can better cover the top corner position of the contact hole. At this time, even if there is a process deviation in the preparation process adopted, there is still enough margin to ensure that the first isolation groove can cover the top corner position of the contact hole, so that the conductive material at the top corner position of the contact hole can be fully removed, avoiding the problem of short circuit between the contact plug in the contact hole and the adjacent interconnection line. Therefore, through the layout method of the semiconductor circuit provided by the present invention, the process window for the circuit layout can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a circuit layout.

[0019] Figure 2 is based on Figure 1 The schematic diagram of the semiconductor circuit formed by the circuit layout processing shown.

[0020] Figure 3 It is a schematic diagram of the structure of the semiconductor circuit after layout adjustment in one embodiment of the present invention.

[0021] Figure 4-Figure 5 is based on Figure 3 The circuit layout shown is a schematic diagram of a semiconductor circuit.

[0022] The reference numerals are as follows:

[0023] 10 / 100-substrate;

[0024] 20 / 200-medium layer;

[0025] 30 / 300-conductive material layer;

[0026] 400 / 400'-isolation tank;

[0027] 41 / 410 / 410'-first isolation groove;

[0028] 42 / 420 / 420'-second isolation slot;

[0029] 500-interconnection wires;

[0030] 51 / 510-first interconnection line;

[0031] 52 / 520 - second interconnection line;

[0032] 60-Insulating material layer. DETAILED DESCRIPTION

[0033] As described in the background art, as circuit designs become smaller and denser, the requirements for manufacturing processes become higher, and it is still difficult to avoid some defects based on the processing accuracy of current processes.

[0034] For example Figure 1 The circuit layout shown in FIG. 1 specifically includes: a gate circuit, a contact hole connected to the gate circuit, a conductive material layer 300 filling the contact hole and covering the gate circuit, and a plurality of isolation grooves 400 distributed in the conductive material layer 300 for dividing the conductive material layer 300 into a plurality of interconnection lines 500. However, based on Figure 1 When the circuit layout shown is processed and manufactured, it is easy for the formed structure to have defects due to process drift, such as reference Figure 2 As shown, when there is an alignment deviation in the photolithography process or a deviation in the etching process, the formed partial isolation groove (eg Figure 2 The first isolation trench 41 shown will have difficulty in completely separating adjacent interconnection lines.

[0035] In particular, when the top corner of the contact hole is expanded, the isolation groove formed by etching in the contact hole will be difficult to completely separate the conductive material in the contact hole, resulting in a short circuit between the conductive material in the contact hole and the adjacent interconnection line, that is, Figure 2 There is residual conductive material in the area shown in the middle dashed box, resulting in a short circuit, that is, the first interconnection line 51 and the second interconnection line 42 on both sides of the first isolation trench 41 are short-circuited to each other.

[0036] To this end, the present invention provides a layout method for a semiconductor circuit, which is used to optimize and adjust the circuit layout so that the adjusted circuit layout has a larger process window, so that the defects formed can still be effectively improved when the existing processing technology is used. Among them, the layout method of the semiconductor circuit includes: providing a circuit layout, and confirming the process parameters of the contact hole in the circuit, so that the process parameters of the isolation groove in the circuit can be confirmed according to the process parameters of the contact hole, so that the adjusted isolation groove can correspond to a larger process window, and improve the isolation performance of the prepared isolation groove. Specifically, confirming the process parameters of the isolation groove includes: adjusting the first isolation groove located on the first side of the contact hole according to the position of the contact hole, so that the first isolation groove located on the first side of the contact hole is set at the edge of the contact hole and extends outside the contact hole, so that the first isolation groove on the first side of the contact hole can effectively separate the contact plug in the contact hole and the adjacent interconnection line.

[0037] The following is a further detailed description of the layout method of the semiconductor circuit proposed in the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as being "above" another element will now be below the element.

[0038] The semiconductor circuit layout method provided in this embodiment includes providing a circuit layout, such as Figure 1 As shown, the circuit layout includes: a gate circuit formed on a substrate 100; a contact hole connected to the gate circuit; and a conductive material layer 300 filling the contact hole and covering the gate circuit. Specifically, a dielectric layer 200 may be formed on the substrate 100, the dielectric layer 200 covers the gate circuit, and the contact hole is formed in the dielectric layer 200 and extends to the gate circuit. Furthermore, the portion of the conductive material layer 300 filling the contact hole is used to form a contact plug to connect to the gate circuit, and the portion of the conductive material layer 300 covering the top surface of the dielectric layer 200 is also used to form an interconnection line 500.

[0039] Furthermore, the circuit layout further includes a plurality of isolation grooves 400 distributed in the conductive material layer 300. Specifically, the plurality of isolation grooves 400 are used to separate the conductive material layer 300 into a first interconnection line 510 connected to the contact plug and a plurality of second interconnections 520 of uniform size. Figure 1 As shown, the plurality of isolation trenches 400 include a first isolation trench 410 and a second isolation trench 420. The first isolation trench 410 is located at the periphery of the first interconnection line 510 and is used to separate the first interconnection line 510 connected to the contact plug and the surrounding second interconnection line 520 from each other. The second isolation trench 420 is arranged between adjacent second interconnection lines 520 so as to be separated from each other by the second isolation trench 420.

[0040] In the semiconductor circuit layout method provided in this embodiment, for the provided circuit layout (for example Figure 1 The layout is adjusted as shown in FIG. 1 , specifically including: confirming the process parameters of the contact hole, and confirming the process parameters of the isolation trench according to the process parameters of the contact hole, so that the sizes of the plurality of isolation trenches and the plurality of interconnection lines are unevenly distributed.

[0041] Specific reference Figure 3 As shown, the method for confirming the process parameters of the isolation trench may include: adjusting the first isolation trench located at the first side of the contact hole according to the position of the contact hole, so that the first isolation trench 410' located at the first side of the contact hole is arranged at the edge of the contact hole and extends outside the contact hole (that is, the adjusted first isolation trench 410' located at the first side of the contact hole extends outside the contact hole at the edge of the contact hole), and the first isolation trench 410' is used to separate the contact plug in the contact hole and the adjacent interconnection line (that is, the adjacent second interconnection line 520) at the edge of the contact hole. It can be considered that Figure 3 The first isolation trench 410' is shown for Figure 1 The first isolation trench 410 is shown as an adjusted structure.

[0042] In this embodiment, the first isolation trench 410' located on the first side of the contact hole is used to separate the contact plug and the adjacent second interconnection line 520, and the first isolation trench 410' located on the second side of the contact hole is used to separate the first interconnection line 510 connected to the contact plug and the second interconnection line 520. The first isolation trench 410' located on the second side of the contact hole is disposed on the top of the dielectric layer 200, and the first interconnection line 510 connected to the contact plug extends from the second side of the contact hole to the dielectric layer 200.

[0043] It should be noted that the first side and the second side are two opposite sides of the contact hole. In this embodiment, they are not limited to a specific side of the contact hole, as long as they are any two opposite sides. For different contact holes, the first isolation groove on the corresponding side can be selected for adjustment, as long as the first isolation groove on one side is set according to the "first isolation groove located on the first side of the contact hole" as described above. For example Figure 3 In the figure, the first side of the contact hole located on the left side corresponds to the right side of the contact hole; and the first side of the contact hole located on the right side corresponds to the left side of the contact hole.

[0044] In a further solution, the method for confirming the process parameters of the isolation trench further includes: adjusting the first isolation trench 410' on the first side of the contact hole according to the size of the contact hole. Specifically, the size of the first isolation trench 410' on the first side of the contact hole can be adjusted according to the size of the contact hole, for example, the width of the first isolation trench 410' on the first side of the contact hole can be adjusted to be smaller than the width of the contact hole.

[0045] Furthermore, the method for adjusting the first isolation trench also includes: adjusting the position of the first isolation trench 410' on the first side of the contact hole so that half of the size of the first isolation trench 410' exceeds the contact hole, so that the first isolation trench 410' can completely cover the top corner area of ​​the contact hole, ensuring that the first isolation trench 410' can completely separate the contact plug and the adjacent second interconnect line 520.

[0046] Continue to refer Figure 3 As shown, the contact hole also has an outward expansion portion that expands outward at the top. Specifically, the width of the outward expansion portion of the contact hole is greater than the width of the bottom of the contact hole. In this embodiment, the width of the outward expansion portion of the contact hole increases from bottom to top. For example, the top angle of the contact hole is an arc-shaped top angle. For the contact hole with an outward expansion at the top, when preparing the first isolation groove for separating the contact plug in the contact hole, when there is a slight deviation in the preparation process of the isolation groove (for example, there is an alignment deviation in the photolithography process or an etching deviation in the etching process), it will easily cause the bottom of the formed first isolation groove to stay in the outward expansion area of ​​the top of the contact hole, and it is difficult to completely disconnect the contact plug in the contact hole and the adjacent second interconnect line.

[0047] To this end, in an optional scheme, the process flow of adjusting the isolation trench also includes: adjusting the width of the first isolation trench according to the lateral width of the outward expansion of the top of the contact hole, so that the adjusted width of the first isolation trench 410' is greater than the lateral width of the outward expansion of the top of the contact hole, so that the area of ​​the first isolation trench 410' can completely cover the top corner position of the first side of the contact hole (that is, the position of the outward expansion of the top of the first side of the contact hole).

[0048] Furthermore, the process flow of adjusting the isolation trench also includes: adjusting the depth of the first isolation trench according to the longitudinal depth of the outward expansion portion at the top of the contact hole, so that the depth of the adjusted first isolation trench 410' is lower than the longitudinal depth of the outward expansion portion of the contact hole. That is, the bottom of the adjusted first isolation trench 410' is lower than the bottom of the outward expansion portion of the contact hole. At this time, it can be further ensured that the adjusted first isolation trench 410' can completely cover the outward expansion area at the top of the first side of the contact hole, thereby ensuring that the first isolation trench formed by processing can completely separate the contact plug in the contact hole and the adjacent second interconnect line 520.

[0049] Continue to refer Figure 3 As shown, the process flow of the isolation trench also includes: optimizing and adjusting the second isolation trench according to the design dimensions of the first interconnection line 510 and the second interconnection line 520. That is, on the basis of keeping the design dimensions of the first interconnection line 510 and the second interconnection line 520 meeting the requirements, adjusting the width of the second isolation trench, for example, the width of the adjusted second isolation trench 420' can be smaller than the width of the first isolation trench 410'.

[0050] Furthermore, the depth of the second isolation trench 420' may also be greater than the thickness of the conductive material layer 300, so that the bottom of the second isolation trench 420' extends into the dielectric layer 200. In this embodiment, the depths of the first isolation trench 410' and the second isolation trench 420' may be uniformly set, and both extend to a position below the top surface of the dielectric layer 200. In this embodiment, the first isolation trench 410' located at the second side of the contact hole and used to separate the first interconnection line 510 and the second interconnection line 520 connected to the contact plug may have the same width and depth as the second isolation trench 420'.

[0051] Based on the layout method of the semiconductor circuit as described above, the following is an explanation of the method of processing and manufacturing based on the circuit layout. Figure 4 and Figure 5 As shown, the method for preparing a semiconductor circuit provided in this embodiment includes the following steps.

[0052] Step 1: Form a dielectric layer 20 on a substrate 10, and form a contact hole in the dielectric layer 20. In this embodiment, a gate circuit is formed on the substrate 10, and when the dielectric layer 20 is formed, the dielectric layer 20 covers the gate circuit. Furthermore, the contact hole penetrates the dielectric layer 20 to extend to the gate circuit.

[0053] Step 2: forming a conductive material layer 30, the conductive material layer 30 filling the contact hole and covering the top surface of the dielectric layer 20. The portion of the conductive material layer 30 filling the contact hole is used to form a contact plug, and the portion of the conductive material layer 30 covering the top surface of the dielectric layer 20 is used to form an interconnection line.

[0054] Step three, forming a plurality of isolation grooves in the conductive material layer 30 to divide the conductive material layer into a plurality of interconnection lines. The method for preparing the isolation grooves includes: etching the conductive material layer 30 into the dielectric layer 20 to form the isolation grooves.

[0055] For details, please refer to Figure 4 As shown, a plurality of isolation grooves divide the conductive material layer 30 into a first interconnection line 51 and a second interconnection line 52 . The first interconnection line 51 is connected to the contact plug in the contact hole and extends to the top surface of the dielectric layer 20 . The second interconnection line 52 is located on the top surface of the dielectric layer 20 .

[0056] The plurality of isolation grooves include a first isolation groove 41 located above the edge of the first side of the contact hole, and the first isolation groove 41 is also extended laterally into the dielectric layer 20, and is used to separate the contact plug in the contact hole and the adjacent interconnection line (i.e., the second interconnection line 52) at the edge of the first side of the contact hole, and accordingly separate the first interconnection line 51 and the second interconnection line 52 from each other. In this embodiment, the first isolation groove 41 is extended laterally from the inside of the contact hole to the outside of the contact hole, so that the conductive material at the top corner of the contact hole can be fully removed, thereby improving the isolation performance between the first interconnection line 51 and the second interconnection line 52 on both sides of the first isolation groove 41, and avoiding short circuit.

[0057] Furthermore, the plurality of isolation grooves further include a first isolation groove 41 located above the edge of the second side of the contact hole. It can be considered that the first isolation groove 41 is arranged at the periphery of the first interconnection line 51 connected to the contact plug, wherein the first isolation groove 41 located above the edge of the first side of the contact hole diffuses from the inside of the contact hole to the outside of the contact hole, and the first isolation groove 41 located above the edge of the second side of the contact hole penetrates the conductive material layer on the top surface of the dielectric layer and extends to the dielectric layer 20 below.

[0058] Continue to refer Figure 4 As shown, the plurality of isolation trenches further include second isolation trenches 42, and the second isolation trenches 42 are used to separate adjacent second interconnection lines 52. Specifically, the second interconnection lines 52 penetrate the conductive material layer on the top surface of the dielectric layer and extend to the dielectric layer 20 below.

[0059] In an optional solution, for the first isolation trench 41 located above the edge of the first side of the contact hole, at least half of its size may extend beyond the contact hole. Also, for the contact hole with a top expansion, the width of the corresponding first isolation trench 41 may be greater than the lateral width of the top expansion of the contact hole, and the depth of the first isolation trench 41 may be lower than the longitudinal depth of the expansion portion of the contact hole. In this way, it is ensured that the first isolation trench 41 above the edge of the first side of the contact hole can completely cut off the conductive material at the top corner of the contact hole.

[0060] In this embodiment, the bottoms of the first isolation trench 41 and the second isolation trench 42 both extend downward into the dielectric layer 20, wherein the first isolation trench 41 located on the first side of the contact hole is embedded in the dielectric layer 20 at its bottom corner away from the contact hole, and the bottoms of the first isolation trench 41 and the second isolation trench 42 located on the second side of the contact hole both extend downward into the dielectric layer 20. Specifically, the conductive material layer 30 and the dielectric layer 20 may be etched in sequence by an etching process to form the first isolation trench 41 and the second isolation trench 42.

[0061] For further solutions, please refer to Figure 5As shown, the method for preparing the semiconductor circuit further includes: filling an insulating material layer 60 into the isolation groove.

[0062] In summary, in the layout method of the semiconductor circuit provided in this embodiment, a first isolation groove is provided on one side (i.e., the first side) of the contact hole to separate the contact plug in the contact hole and the adjacent interconnection line. Moreover, for the first isolation groove on the first side of the contact hole, the first isolation groove is also expanded laterally from the contact hole to the outside of the contact hole, so that the isolation range of the first isolation groove can better cover the top corner position of the contact hole. At this time, even if there is a process deviation in the preparation process adopted, there is still enough margin to ensure that the first isolation groove can cover the top corner position of the contact hole, so that the conductive material at the top corner position of the contact hole can be fully removed, avoiding the problem of short circuit between the contact plug in the contact hole and the adjacent interconnection line.

[0063] It should be noted that the above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0064] It should also be noted that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc. It should also be understood that the terms described herein are only used to describe specific embodiments, rather than to limit the scope of the present invention. It must be noted that the singular forms "one", "a kind of", and "the" used herein and in the appended claims include plural references unless the context clearly indicates the opposite. For example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or" definition, unless the context clearly indicates the opposite.

Claims

1. A semiconductor circuit layout method, characterized in that: include: A circuit layout is provided, the circuit layout comprising: a gate circuit, a contact hole connecting the gate circuit and located between adjacent gate circuits, a conductive material layer filling the contact hole and covering the gate circuit, wherein a portion of the conductive material layer filling the contact hole is used to form a contact plug, a plurality of isolation grooves distributed in the conductive material layer, the isolation grooves are used to divide the conductive material layer into a first interconnection line and a plurality of second interconnections of uniform size, wherein the first interconnection line is connected to the contact plug, and the isolation grooves include a first isolation groove and a second isolation groove; Confirming the process parameters of the contact hole, and confirming the process parameters of the isolation trench based on the process parameters of the contact hole, so that the sizes of the plurality of isolation trenches and the plurality of interconnection lines are not evenly distributed; wherein confirming the process parameters of the isolation trench comprises: adjusting the first isolation trench located on the first side of the contact hole according to the position of the contact hole, so that the first isolation trench located on the first side of the contact hole is arranged at the edge of the contact hole and extends outside the contact hole, so as to separate the contact plug in the contact hole and the second interconnection line adjacent to the first isolation trench at the edge of the contact hole.

2. The semiconductor circuit layout method according to claim 1, characterized in that: Confirming the process parameters of the isolation trench further includes: adjusting the first isolation trench on the first side of the contact hole according to the size of the contact hole.

3. The semiconductor circuit layout method according to claim 1, characterized in that: Confirming the process parameters of the isolation trench further includes: adjusting the size and position of the first isolation trench on the first side of the contact hole.

4. The semiconductor circuit layout method according to claim 3, characterized in that: The position of the first isolation trench on the first side of the contact hole is adjusted so that half of the size of the first isolation trench is beyond the contact hole.

5. The semiconductor circuit layout method according to claim 3, characterized in that: According to the width of the contact hole, the width of the first isolation trench on the first side of the contact hole is adjusted to be smaller than the width of the contact hole.

6. The semiconductor circuit layout method according to claim 1, characterized in that: Confirming the process parameters of the isolation trench also includes: adjusting the width of the first isolation trench on the first side of the contact hole according to the lateral width of the top expansion of the contact hole, so that the width of the first isolation trench is greater than the lateral width of the top expansion of the contact hole.

7. The semiconductor circuit layout method according to claim 6, characterized in that: Confirming the process parameters of the isolation trench also includes: adjusting the depth of the first isolation trench on the first side of the contact hole according to the longitudinal depth of the outward expansion portion at the top of the contact hole so that the depth of the first isolation trench is lower than the longitudinal depth of the outward expansion portion of the contact hole.

8. The semiconductor circuit layout method according to claim 1, wherein: The first interconnection line connected to the contact plug extends from a second side of the contact hole, and the first side and the second side are opposite sides of the contact hole, respectively.

9. The semiconductor circuit layout method according to claim 1, characterized in that: Confirming the process parameters of the isolation trench further includes: adjusting the size of the second isolation trench according to the design sizes of the first interconnection line and the second interconnection line, wherein the second isolation trench is used to separate adjacent second interconnection lines.

10. The semiconductor circuit layout method according to claim 1, characterized in that: The width of the first isolation trench is adjusted to be greater than the width of the second isolation trench.

11. A method for preparing a semiconductor circuit, characterized in that: include: Obtaining a semiconductor circuit layout by using the layout method according to any one of claims 1 to 10, and forming a semiconductor circuit on a substrate based on the semiconductor circuit layout; Wherein, the method for preparing a semiconductor circuit based on the semiconductor circuit layout includes: Forming a dielectric layer on a substrate, and forming a contact hole in the dielectric layer, wherein the contact hole is located between adjacent gate circuits in the semiconductor circuit; forming a conductive material layer, the conductive material layer filling the contact hole and covering the top surface of the dielectric layer, and forming a contact plug with the portion of the conductive material layer filling the contact hole; and, A plurality of isolation grooves are formed in the conductive material layer to divide the conductive material layer into a first interconnection line and a plurality of second interconnections of uniform size; wherein the first interconnection line is connected to the contact plug, and the plurality of isolation grooves include a first isolation groove and a second isolation groove, wherein the first isolation groove is located above the edge of the first side of the contact hole, and the first isolation groove also extends laterally into the dielectric layer to separate the contact plug in the contact hole and the second interconnection line adjacent to the first isolation groove at the edge of the first side of the contact hole.

12. The method for preparing a semiconductor circuit according to claim 11, characterized in that: Also includes: An insulating material layer is filled into the isolation trench.

Images