A vacuum transistor based on suspended graphene / boron nitride heterojunction and its preparation method and application

Abstract

The present invention discloses a vacuum transistor based on a suspended graphene / boron nitride heterojunction and a preparation method and application thereof. The preparation method includes three steps of preparing a metal electrode, etching a channel, and transferring a hexagonal boron nitride-graphene composite structure. The silicon substrate is directly used as a collector, which greatly simplifies the preparation process. The vacuum transistor device structure designed in the present invention is highly innovative, making full use of the bonding force between boron nitride and graphene, suspending the graphene / boron nitride heterojunction as a whole above the channel, effectively reducing the probability of graphene fracture, collapse, curling and wrinkling, overcoming the difficulty of the extremely low success rate of traditional preparation of suspended graphene devices, greatly improving the success rate of preparation of suspended graphene devices, and the prepared vacuum transistor structure is more stable. The use of a new transfer method avoids the contact of graphene with other media such as solutions, effectively solving the problem of existing doping.

Description

Technical Field

[0001] The present invention relates to the field of micro-nano processing technology, and in particular to a vacuum transistor based on a suspended graphene / boron nitride heterojunction and a preparation method and application thereof. Background Art

[0002] The vacuum transistor combines traditional vacuum tube technology with modern semiconductor micro-nano processing technology, giving full play to the advantages of both, reducing the volume of traditional vacuum tubes, transistorizing vacuum tubes, significantly reducing operating voltage, greatly reducing device size, and allowing the device to operate under standard atmospheric pressure, which is more conducive to integration.

[0003] However, there are still some problems in the device structure and preparation process of vacuum transistors: First, the field electron emission method is used. If it is to work at a lower voltage, there are certain requirements for the structure of the collector and emitter. Usually, a sharp or rounded structure is used, but long-term operation will cause the surface of this structure to be damaged, affecting the performance of the device. Second, impurities are easily introduced during the preparation process, which reduces the performance of the device and makes it less consistent. Third, the suspended structure is very easy to break, collapse, curl or wrinkle during the preparation process, and the success rate of preparation is low. Summary of the invention

[0004] The present invention provides a vacuum transistor based on a suspended graphene / boron nitride heterojunction and a preparation method and application thereof, which are used to overcome the defects of the prior art such as poor working stability, easy doping, and low preparation success rate.

[0005] To achieve the above object, the present invention proposes a method for preparing a vacuum transistor based on a suspended graphene / boron nitride heterojunction, comprising the following steps:

[0006] S1: Metal electrodes and alignment marks are prepared on silicon dioxide / silicon wafers using electron beam exposure and electron beam thermal evaporation;

[0007] S2: using an inductively coupled plasma etcher to completely etch the silicon dioxide in the area between the metal electrodes to obtain an etched channel;

[0008] S3: Graphene is adsorbed on hexagonal boron nitride, and the graphene / boron nitride heterojunction is suspended above the channel using a two-dimensional material transfer platform to obtain a vacuum transistor based on the suspended graphene / boron nitride heterojunction.

[0009] To achieve the above objectives, the present invention also proposes a vacuum transistor based on a suspended graphene / boron nitride heterojunction, which is prepared by the above-mentioned preparation method; the channel depth of the vacuum transistor is equal to the SiO2 thickness in the silicon wafer + the metal electrode thickness.

[0010] To achieve the above objectives, the present invention also proposes an application of a vacuum transistor based on a suspended graphene / boron nitride heterojunction, and the vacuum transistor prepared by the above preparation method or the above vacuum transistor is applied to the detection of harmful substances, safe high-speed communications, microprocessors and micro electronic transmitters.

[0011] Compared with the prior art, the present invention has the following beneficial effects:

[0012] 1. The preparation method of the vacuum transistor based on the suspended graphene / boron nitride heterojunction provided by the present invention includes three steps: preparing a metal electrode, etching a channel, and transferring the graphene / boron nitride heterojunction. The silicon substrate is directly used as the hot electron collection end, which greatly simplifies the preparation process. The vacuum transistor designed in the present invention has a novel structure, fully utilizes the bonding force between boron nitride and graphene, effectively reduces the probability of graphene fracture, collapse, curling or wrinkling, greatly improves the success rate of the preparation of suspended graphene devices, and the prepared vacuum transistor has a stronger structural stability. The use of a new transfer method avoids the contact between graphene and other media such as solutions, effectively solving the existing doping problem.

[0013] 2. The vacuum transistor based on the suspended graphene / boron nitride heterojunction provided by the present invention uses graphene as the emitter and Si under the channel as the collector. It utilizes the phonon-assisted electron emission mechanism unique to graphene strips and can work at a relatively low voltage. The gas in the electric field will not be ionized, thus avoiding many problems faced by previous field emission vacuum transistors. The vacuum channel serves as an electron transmission medium, thus avoiding the lattice vibration scattering problem encountered in carrier transmission in traditional transistors, and can work in the terahertz band, and can be used for applications such as secure high-speed communications or in microprocessors and micro electronic transmitters. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0015] Figure 1 A flow chart of a method for preparing a vacuum transistor based on suspended graphene provided by the present invention;

[0016] Figure 2a A structural diagram of a vacuum transistor prepared in an embodiment;

[0017] Figure 2b A working principle diagram of a vacuum transistor prepared in an embodiment;

[0018] Figure 3 Schematic diagram of the PDMS+PC composite film used for transfer;

[0019] Figure 4 This is a graphene field effect test curve of the vacuum transistor prepared in the example.

[0020] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0023] Unless otherwise specified, all drugs / reagents used were commercially available.

[0024] The present invention provides a method for preparing a vacuum transistor based on a suspended graphene / boron nitride heterojunction, comprising the following steps:

[0025] S1: Electron beam exposure and electron beam thermal evaporation are used to prepare metal electrodes and alignment marks on both sides of the channel area on the silicon wafer.

[0026] Preferably, step S1 specifically includes:

[0027] S11: Spin-coat electron beam photoresist on the surface of the silicon wafer and dry it.

[0028] Preferably, the silicon wafer is a SiO2 / Si silicon wafer with a SiO2 thickness of 80 to 300 nm, which is the SiO2 thickness range of common silicon wafers.

[0029] Preferably, the electron beam photoresist is a polymethyl methacrylate (PMMA) solution, preferably PMMA 950K.

[0030] Preferably, the drying temperature is 160-180°C.

[0031] S12: Design an electrode pattern, obtain an exposure area according to the electrode pattern, wash away the electron beam photoresist in the exposure area, expose the exposure area using an electron beam exposure machine to depict an electrode and a marking pattern in the exposure area, develop for 1 minute after the exposure is completed, and fix for 30 seconds.

[0032] S13: sequentially evaporating a chromium layer and a gold layer in the exposure area containing the electrode and the marking pattern.

[0033] Preferably, the thickness of the chromium layer is 5 nm, and the thickness of the gold layer is 50 nm.

[0034] S14: using an acetone solution to dissolve the electron beam photoresist on the silicon wafer, and then washing away the acetone solution with isopropyl alcohol to obtain metal electrodes and alignment marks on both sides of the channel region.

[0035] S2: Using an inductively coupled plasma etcher to completely etch the silicon dioxide in the area between the metal electrodes to obtain an etched channel.

[0036] Preferably, step S2 specifically includes:

[0037] S21: Spin-coat electron beam photoresist on the surface of the silicon wafer with metal electrodes and alignment marks, and dry.

[0038] Preferably, the electron beam photoresist is a polymethyl methacrylate (PMMA) solution, preferably PMMA 950K.

[0039] Preferably, the drying temperature is 160-180°C.

[0040] S22: Wash away the electron beam photoresist in the area between the metal electrodes, use an electron beam exposure machine to expose the area between the metal electrodes to depict a channel pattern, develop for 1 minute after the exposure is completed, and fix for 30 seconds.

[0041] S23: using an inductively coupled plasma etcher to completely etch the silicon dioxide containing the channel pattern.

[0042] Preferably, the specific parameters of the etching are: etching gas is CF4, CF4 flow rate: 30 sccm; upper RF power is 400 W, lower RF power is 100 W; vacuum degree is 5 Torr; etching time is 40 s.

[0043] S24: dissolving the electron beam photoresist on the silicon wafer using an acetone solution, and then washing away the acetone solution with isopropyl alcohol to obtain an etched channel structure.

[0044] S3: Graphene is adsorbed on hexagonal boron nitride, and the graphene / boron nitride heterojunction is suspended above the channel using a two-dimensional material transfer platform to obtain a vacuum transistor based on the suspended graphene / boron nitride heterojunction.

[0045] Preferably, step S3 is specifically:

[0046] S31: Place a drop of polydimethylsiloxane (PDMS) on a glass slide and dry it.

[0047] Preferably, the drying temperature is 160-180°C.

[0048] S32: Drop a drop of polycarbonate (PC) solution on another glass slide, cover the glass slide with the PC solution with a clean glass slide to diffuse the PC solution to all overlapping parts, and then separate the two glass slides in a tangential direction to obtain two PC films.

[0049] S33: Take a tape, punch holes in the tape, and use the perforated tape to stick a piece of polycarbonate film to the PDMS in step S31 to obtain a dome-shaped PDMS+PC composite film.

[0050] S34: Under the condition of 70-100° C., using a two-dimensional material transfer platform, using the composite film to adsorb hexagonal boron nitride, and then using the hexagonal boron nitride to adsorb graphene to obtain a graphene / boron nitride heterojunction.

[0051] S35: suspending the graphene / boron nitride heterojunction as a whole above the channel, heating it to 160-200° C., washing away the PC, and obtaining a vacuum transistor based on the suspended graphene / boron nitride heterojunction.

[0052] The present invention also proposes a vacuum transistor based on a suspended graphene / boron nitride heterojunction, which is prepared by the above-mentioned preparation method; the channel depth of the vacuum transistor is equal to the thickness of SiO2 in the silicon wafer + the thickness of the metal electrode.

[0053] The present invention also proposes an application of a vacuum transistor based on a suspended graphene / boron nitride heterojunction, and the vacuum transistor prepared by the above-mentioned preparation method or the above-mentioned vacuum transistor is applied to the detection of harmful substances, safe high-speed communications, microprocessors and microelectronic transmitters.

[0054] Example

[0055] This embodiment provides a method for preparing a vacuum transistor based on a suspended graphene / boron nitride heterojunction, such as Figure 1 As shown, the following steps are included:

[0056] (1) A polymethyl methacrylate solution layer was spin-coated on the surface of a silicon wafer and dried at 175°C.

[0057] (2) Designing an electrode pattern, obtaining an exposure area according to the electrode pattern, washing away the electron beam photoresist in the exposure area, and exposing the exposure area using an electron beam exposure machine to depict an electrode and a marking pattern in the exposure area. The exposure area is determined by a layout designed by the electron beam exposure machine and input coordinates, and the layout depicts the electrode and marking pattern. After the exposure is completed, the electrode is developed for 1 minute and fixed for 30 seconds.

[0058] (3) Depositing a chromium layer and a gold layer on the silicon wafer containing the electrode and marking pattern obtained in step (2) by electron beam thermal evaporation; wherein the thickness of the chromium layer is 5 nm, and the thickness of the gold layer is 50 nm.

[0059] (4) Stripping is performed using an acetone solution, and then the acetone solution is washed off with isopropyl alcohol to obtain metal electrodes and alignment marks on both sides of the channel area on the surface of the silicon wafer.

[0060] (5) A polymethyl methacrylate solution layer is spin-coated on the surface of the silicon wafer on which the electrodes and alignment marks have been prepared, and then dried at 175°C.

[0061] (6) Washing away the electron beam photoresist in the area between the metal electrodes, exposing the area between the metal electrodes using an electron beam exposure machine to depict a channel pattern, developing for 1 minute after the exposure is completed, and fixing for 30 seconds.

[0062] (7) The silicon dioxide containing the channel pattern is completely etched using an inductively coupled plasma etcher. The specific etching parameters are: etching gas is CF4, CF4 flow rate: 30 sccm; upper RF power is 400 W, lower RF power is 100 W; vacuum degree is 5 Torr; etching time is 40 s.

[0063] (8) The polymethyl methacrylate solution layer on the silicon wafer is dissolved using an acetone solution, and then the acetone solution is washed away with isopropyl alcohol to obtain an etched channel structure.

[0064] (9) Place a drop of polydimethylsiloxane (PDMS) solution on a glass slide and dry it at 175 °C.

[0065] (10) A drop of polycarbonate (PC) solution is dropped on another glass slide, and a clean glass slide is placed on the glass slide with the PC solution so that the PC solution spreads to all overlapping parts. The two glass slides are then separated in a tangential direction to obtain two PC films.

[0066] (11) Take a tape, punch holes in the tape, and use the perforated tape to stick the PC film to the PDMS in step (9) to obtain a dome-shaped PDMS+PC composite film, such as Figure 3 shown.

[0067] (12) At 90° C., using a two-dimensional material transfer platform, using the composite film to adsorb hexagonal boron nitride, and then using the hexagonal boron nitride to adsorb graphene to obtain a graphene / boron nitride heterojunction.

[0068] (13) The graphene / boron nitride heterojunction is suspended above the channel, heated to 190° C., cooled, soaked in CCl3H2O for 20 to 30 seconds to wash away the PC remaining on the surface, and then transferred to deionized water for cleaning to obtain a vacuum transistor based on a suspended graphene / boron nitride heterojunction, such as Figure 2a and 2b shown.

[0069] The vacuum transistor prepared in this example was subjected to electrical testing to obtain a field effect curve (see Figure 4 ), the Dirac point of the device is near 0V, and it has a high mobility. Through characterization, it can be found that the vacuum transistor graphene structure prepared in this embodiment is stable and not easy to break, collapse, curl or wrinkle. At the same time, less impurities are introduced, which improves the doping problem in the existing preparation process.

[0070] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A method for preparing a vacuum transistor based on a suspended graphene / boron nitride heterojunction, characterized in that: The following steps are involved: S1: Metal electrodes and alignment marks are prepared on silicon dioxide / silicon wafers using electron beam exposure and electron beam thermal evaporation; Step S1 is specifically as follows: S11: Spin-coat electron beam photoresist on the surface of the silicon wafer and dry it; S12: designing an electrode pattern, obtaining an exposure area according to the electrode pattern, washing away the electron beam photoresist in the exposure area, exposing the exposure area using an electron beam exposure machine to depict an electrode and a marking pattern in the exposure area, developing for 1 minute after the exposure is completed, and fixing for 30 seconds; S13: sequentially evaporating a chromium layer and a gold layer in the exposure area containing the electrode and the marking pattern; S14: dissolving the electron beam photoresist on the silicon wafer using an acetone solution, and then washing away the acetone solution with isopropyl alcohol to obtain metal electrodes and alignment marks on both sides of the channel region; S2: using an inductively coupled plasma etcher to completely etch the silicon dioxide in the area between the metal electrodes to obtain an etched channel; S3: Using hexagonal boron nitride to adsorb graphene, a two-dimensional material transfer platform is used to suspend the graphene / boron nitride heterojunction as a whole above the channel, thereby obtaining a vacuum transistor based on the suspended graphene / boron nitride heterojunction; Step S3 is specifically as follows: S31: Place a drop of polydimethylsiloxane on a glass slide and dry it; S32: dropping a drop of polycarbonate solution on another glass slide, and then covering the glass slide with the polycarbonate solution with a clean glass slide to allow the polycarbonate solution to spread to all overlapping parts, and then separating the two glass slides in a tangential direction to obtain two polycarbonate films; S33: taking a tape, punching holes in the tape, and using the tape with holes to stick a piece of polycarbonate film onto the electron beam photoresist in step S31 to obtain a composite film; S34: using a two-dimensional material transfer platform at 70-100° C., using the composite film to adsorb hexagonal boron nitride, and then using the hexagonal boron nitride to adsorb graphene to obtain a graphene / boron nitride heterojunction; S35: suspending the graphene / boron nitride heterojunction as a whole above the channel, heating it to 160-200° C., washing away the polycarbonate, and obtaining a vacuum transistor based on the suspended graphene / boron nitride heterojunction.

2. The preparation method according to claim 1, characterized in that The silicon wafer is a SiO2 / Si silicon wafer with a SiO2 thickness of 80-300nm.

3. The preparation method according to claim 1, characterized in that: The electron beam photoresist is a polymethyl methacrylate solution.

4. The preparation method according to claim 1, characterized in that: The thickness of the chromium layer is 5 nm, and the thickness of the gold layer is 50 nm.

5. The preparation method according to claim 1, characterized in that: Step S2 is specifically as follows: S21: spin coating electron beam photoresist on the surface of the silicon wafer with metal electrodes and alignment marks, and drying; S22: washing away the electron beam photoresist in the area between the metal electrodes, exposing the area between the metal electrodes using an electron beam exposure machine to depict a channel pattern, developing for 1 minute after the exposure, and fixing for 30 seconds; S23: using an inductively coupled plasma etcher to completely etch the silicon dioxide containing the channel pattern; S24: dissolving the electron beam photoresist on the silicon wafer using an acetone solution, and then washing away the acetone solution with isopropyl alcohol to obtain an etched channel structure.

6. The preparation method according to claim 5, characterized in that: The specific parameters of the etching are: etching gas is CF4, CF4 flow rate: 30 sccm; upper RF power is 400 W, lower RF power is 100 W; vacuum degree is 5 Torr; etching time is 40 s.

7. A vacuum transistor based on a suspended graphene / boron nitride heterojunction, characterized in that: Prepared by the preparation method according to any one of claims 1 to 6; the channel depth of the vacuum transistor is equal to the thickness of SiO2 in the silicon wafer + the thickness of the metal electrode.

8. An application of a vacuum transistor based on a suspended graphene / boron nitride heterojunction, characterized in that: The vacuum transistor prepared by the preparation method according to any one of claims 1 to 6 or the vacuum transistor according to claim 7 is used in detecting harmful substances, safe high-speed communications, microprocessors and microelectronic transmitters.

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