Edge removal for through-resist plating

By using optimized CIRP and anode shield in the electroplating system combined with a new seal design, the sacrificial layer around the exposed wafer is plating and edge bevel removal after plating, the plating caused by the termination effect in integrated circuit manufacturing is solved. The problem of uneven thickness achieves a more uniform current distribution and plating effect.

CN114729466BActive Publication Date: 2025-01-14LAM RES CORP
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Patent Information

Application Number
CN202080082283.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2019-11-27
Filing Date
2020-11-24
Publication Date
2025-01-14
Estimated Expiration
2040-11-24

AI Technical Summary

Technical Problem

The existing electroplating systems have a terminal effect in integrated circuit manufacturing, resulting in uneven thickness of wafer edge plating, and the existing RDL technology is difficult to achieve local correction during thin seed etching, resulting in uneven current and plating thickness waveforms.

Method used

Using an optimized channel ion resistor plate (CIRP) and anode shield with a new cup + lip seal design, the sacrificial layer around the wafer is exposed during electroplating, and edge bevel removal is performed after plating by electrochemical deposition tools to reduce plating Thickness and correct for terminal effects.

Benefits of technology

It effectively reduces the plating thickness, improves the current distribution, realizes uniform plating of the edges of the wafer, avoids the problem of uneven thickness caused by the terminal effect, and optimizes the EBR time and chemical use in the downstream process.

✦ Generated by Eureka AI based on patent content.

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Abstract

The electroplating cup assembly includes a cup bottom, a lip seal, and an electrical contact structure. The cup bottom at least partially defines an opening configured to expose a wafer located in the cup assembly to an electroplating solution. The lip seal is on the cup bottom and includes a sealing structure extending upward along an inner edge of the lip seal to an apex configured to contact a seed layer of the wafer and adjacent to a sacrificial layer of the wafer. The electrical contact structure is above a portion of the seal. The electrical contact structure is configured to couple to the seed layer of the wafer.
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Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 941,519, filed on November 27, 2019, the entire disclosure of which is incorporated herein by reference. Background Art

[0003] Electroplating is commonly used in integrated circuit manufacturing processes to form conductive structures. For example, in the copper damascene process, electroplating is used to form copper lines and vias in channels that were previously etched into the dielectric layer. In such a process, a seed layer of copper is first deposited into the channel and on the substrate surface by physical vapor deposition. Next, a thicker layer of copper is deposited on the seed layer using electroplating to completely fill the channel. Excess copper is then removed by chemical mechanical polishing to form individual copper features.

[0004] Current electroplating systems can be categorized as "open contact" and "closed contact." Open contact plating systems are those in which the wafer contacts (which deliver current to the seed layer) are exposed to the plating solution during plating. Likewise, closed contact plating systems are those in which the contacts are not exposed to the plating solution.

[0005] When manufacturing integrated circuits, it is generally desired to utilize as many wafer surfaces as possible to manufacture devices to increase the number of devices per wafer. However, electroplating systems generally utilize electrical contacts and other structures that contact the wafer during deposition. Therefore, a limited amount of surface area can be plated. For example, in an open contact plating system, since the electrode is exposed to the plating solution during the plating process, the electrode is plated onto the substrate surface in this process. Removing the electrode exposes the unplated area where the electrode contacts the substrate. Further, removing the contacts may cause the copper layer near the electrode to be damaged. For example, the 2 mm or larger outer periphery of the wafer may become unsuitable for integrated circuit manufacturing.

[0006] Existing RDL technologies use a nominal seed thickness of These thicknesses are susceptible to critical dimension (CD) loss, line roughness, and undercutting during long aggressive seed etch processes. (For example ) have focused on anode adjustment (size, shape, number) to control current distribution. These changes are far from the wafer surface and tend to produce global corrections. Therefore, they cannot achieve the local correction required for terminal effects and often result in wavy, non-uniform current (and subsequently plating thickness) profiles.

[0007] Figure 1 A cross-sectional view of a plating cup assembly 100 according to the prior art is shown. The lip seal of the plating system is coupled to the periphery of the wafer and adjacent to the outermost yielding feature. Plating using the plating cup assembly 100 generally results in a greater thickness of plating at the edge of the wafer relative to the surface of the wafer due to the "terminal effect". The terminal effect occurs when the seed resistance dominates the conductive plating bath equivalent circuit and results in significant electrodeposition at the edge of the wafer relative to the surface of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To easily identify the discussion of any particular element or act, the most significant digit or digits in the reference number refer to the figure number in which the component is first mentioned.

[0009] Figure 1 A cross-sectional view of a plating cup assembly 100 according to the prior art is shown.

[0010] Figure 2 A cross-sectional view of a plating cup assembly 200 is shown according to one embodiment.

[0011] Figure 3 A cross-sectional view of a plating cup assembly 300 is shown according to one embodiment.

[0012] Figure 4 A cross-sectional view of a plating cup assembly 400 is shown according to one embodiment.

[0013] Figure 5 Wafer 500 is shown for use with electroplating cup assembly 200 according to one embodiment.

[0014] Figure 6 A wafer 600 is shown for use with the electroplating cup assembly 200 according to one embodiment.

[0015] Figure 7 Wafer 700 is shown for use with electroplating cup assembly 200 according to one embodiment.

[0016] Figure 8 A wafer 800 is shown for use with the electroplating cup assembly 200 according to one embodiment.

[0017] Fig. 9 A wafer 900 is shown for use with the electroplating cup assembly 200 according to one embodiment. DETAILED DESCRIPTION

[0018] The following description describes the system, method, technology, instruction sequence of the exemplary embodiment of the present theme. In the following description, for the purpose of explanation, many specific details are set forth to provide understanding to the various embodiments of the present theme. However, it will be apparent to those skilled in the art that the embodiments of the present theme can be implemented without some or other of these specific details. Examples represent possible variations only. Unless otherwise clearly stated, structures (e.g., structural components, such as modules) are optional and can be combined or subdivided, and operations (e.g., in programs, algorithms or other functions) can change order or be combined or subdivided.

[0019] The term "wafer" is used herein to refer to a semiconductor substrate. Examples of wafers include slices of crystalline silicon.

[0020] The term "electroplating solution" is used herein to refer to an electrolyte solution used for plating metals.

[0021] The term "lip seal" is used herein to refer to a radial shaft seal.

[0022] The term "edge bevel removal (EBR) tool" is used herein to refer to a tool / system for removing the bevel edge of a wafer. Wafers have two typical edge types: a slanted bevel shape or a rounded bullet shape. The edge on the bevel type is called the bevel area. In one example, EBR is a process that uses sulfuric acid and hydrogen peroxide to remove the edge and backside metal layer.

[0023] Fine-line redistribution layers (RDLs), part of the advanced packaging scheme "high-density fan-out or HDFO," have gained interest as packages trend toward smaller and thinner footprints. Several challenges are associated with fine-line RDLs, particularly during the seed etch removal step in a semi-additive process (SAP). Namely, critical dimension (CD) loss (i.e., line shrinkage), sidewall roughness evolution, and undercutting due to the copper etchant attacking the underlying seed and the lines themselves. One possible way to address these challenges is to reduce the thickness of the underlying copper seed on which the lines are plated. Thinner seeds require less etching time and can utilize less aggressive seed etch chemistries.

[0024] However, thin seed plating has its own challenges, primarily a phenomenon known as the “termination effect.” The termination effect occurs when the potential drop across a thin metal seed (which is more resistive than a thick metal seed) results in thicker plating near the edge of the wafer (at the contact terminals) than at the center of the wafer.

[0025] While CIRP (Channel Ion Resistive Plate) (also known as HRVA or High Resistance Virtual Anode) helps mitigate terminal effects, it alone is not sufficient for ultra-thin seeds. The present system described herein addresses these challenges. The present application describes a thin seed plating process that includes coupling an optimized CIRP and anode shield with a new cup + lip seal design during electroplating. A post-plating EBR (edge ​​bevel removal) process is performed after the electroplating process to remove a sacrificial plating ring. Traditional cup and lip seals are designed to cover the exposed copper seed around the perimeter of the wafer to prevent erosion and plating, while one embodiment intentionally exposes a portion of the seed. With this exposed area, copper can be plated into an annular ring shape at the edge of the wafer. Stealing current from features adjacent to this ring reduces the thickness of the plating. The sacrificial ring can compensate and correct for terminal effects.

[0026] The present application may also include a post-plating step in which a copper-plated sacrificial ring may be removed. Electrochemical deposition tools (e.g., SABRE and SABRE3D of Lam Research Inc.) may be equipped with an optional EBR (edge ​​bevel removal) module to remove Cu deposited on the wafer bevel area (because if left intact, it may affect downstream processing). Although wafer-level packaging (WLP) does not typically use EBR (which is used by inlay and through-silicon vias (TSV)), the present system described herein can reuse the module to remove the sacrificial copper ring. The EBR time, chemical substances, and edge restricted area size may be optimized for the process. In the case of not removing the thick sacrificial copper-plated ring, downstream processes (e.g., wafer cutting) may be impaired.

[0027] In a first embodiment for Cu thin seed plating for RDL applications, the system is applicable to: a) any thin seed Through resist Cu plating applications, not RDL specific; b) Nominal seed thickness ( to ), which has a large pattern keep-out zone. A large pattern keep-out zone can be defined here as an area at the edge of the wafer that has been coated with photoresist but not patterned that is greater than 0.5 mm wide. Unpatterned photoresist will not be plated, so patterned areas adjacent to large non-patterned areas tend to be plated with steep thickness spikes, forming edge-humps.

[0028] In a second embodiment, the process of sacrificial plating and removal can be extended to any metal (Ni, SnAg, Sn, Co) instead of copper. The EBR process can be changed from piranha etch (used for Cu etch in the first embodiment) to nitric acid etch or other chemical etch appropriate for the metal to be etched.

[0029] In an exemplary embodiment, an electroplating cup assembly is described. The electroplating cup assembly includes a cup bottom having an opening and a seal disposed on the cup bottom around the opening. The seal includes a wafer contact vertex substantially located at an inner edge of the seal. The electroplating cup assembly also includes an electrical contact structure disposed above a portion of the seal.

[0030] In an exemplary embodiment, the electroplating cup assembly includes: a cup bottom, which at least partially defines an opening, which is configured to allow a wafer located in the electroplating cup assembly to be exposed to a plating solution; a lip seal, which is coupled to the cup bottom, the lip seal including a sealing structure, which extends upward along the inner edge of the lip seal to an apex, the apex is configured to contact a seed layer of the wafer and a sacrificial layer of the wafer; and an electrical contact structure, which forms a seal with the lip seal, the electrical contact structure is configured to couple with the seed layer at the periphery of the wafer.

[0031] In another exemplary embodiment, a method of electroplating a wafer is described. The method includes: placing a wafer on a plating cup assembly that exposes a surface of the wafer to a plating solution, the surface including a sacrificial layer at a periphery of the wafer; electroplating the exposed surface of the wafer; and after electroplating the exposed surface of the wafer, removing the plated sacrificial layer of the wafer.

[0032] In yet another exemplary embodiment, a system for electroplating a wafer is described. The system includes: a wafer including a seed layer and a sacrificial layer disposed on the seed layer along a perimeter of the wafer; and an electroplating cup assembly configured to support the wafer. The electroplating cup assembly includes: a cup bottom at least partially defining an opening configured to allow a wafer located in the electroplating cup assembly to be exposed to an electroplating solution; a lip seal coupled to the cup bottom, the lip seal including a sealing structure extending upwardly along an inner edge of the lip seal to an apex configured to contact the seed layer of the wafer and the sacrificial layer of the wafer; and an electrical contact structure forming a seal with the lip seal, the electrical contact structure configured to couple with the seed layer at the perimeter of the wafer.

[0033] Figure 2 A cross-sectional view of an electroplating cup assembly 200 according to an embodiment is shown. The electroplating cup assembly 200 may include a wafer 202, a seed layer (e.g., copper seed 204), a photoresist 206, an outermost yielding feature 208, a sacrificial layer 210 (e.g., a sacrificial electroplating (EP) film), an electrical contact structure 212, a cup bottom 214, and a lip seal 216. By intentionally exposing a portion of the seed layer at the periphery of the wafer to plate a sacrificial annular region / ring of copper (e.g., sacrificial layer 210), current may be stolen from features immediately adjacent (e.g., in the range of 5 nm to 10 nm) to the edge of the wafer, thereby reducing its plating thickness. The sacrificial ring may compensate for and correct for terminal effects.

[0034] The cup bottom 214 may at least partially define an opening configured to allow a portion of the surface of the wafer 202 positioned in the electroplating cup assembly to be exposed to the electroplating solution. For example, the exposed portion of the wafer 202 may include the sacrificial layer 210, the outermost yield feature 208, and the photoresist 206. The exposed portion of the wafer 202 is exposed to the electroplating solution.

[0035] The lip seal 216 is coupled to the cup bottom 214. The lip seal 216 includes a sealing structure that extends upward along the inner edge of the lip seal 216 to an apex that is configured to contact the copper seed 204 of the wafer 202. The sealing structure is adjacent to the sacrificial layer 210. For example, the sealing structure contacts a vertical surface of the sacrificial layer 210 of the wafer 202.

[0036] Electrical contact structure 212 contacts copper seed 204 at the periphery of wafer 202 and forms a seal with lip seal 216. For example, surface areas protected by the seal (eg, the edge of wafer 202 and the backside of wafer 202) are not exposed to the electroplating solution.

[0037] Figure 3 A cross-sectional view of an electroplating cup assembly 300 according to an embodiment is shown. The electrical contact structure 212 includes a continuous outer ring that is located below and in contact with the slip ring 302 so that the current from the slip ring 302 can be evenly distributed. Further, the contact structure includes a plurality of protrusions extending upward from the outer ring of the contact structure into a groove 304 formed in the slip ring 302. The protrusions contact the inner edge of the groove 304. The protrusions are configured to center the electrical contact structure 212 at the correct position relative to the lip seal 216 and the cup bottom 214 to ensure that all of the individual contacts on the electrical contact structure 212 (described below) contact the plated seed layer on the wafer 202 located in the cup bottom 214. Further, this feature also helps prevent any contact from sliding past the lip seal 216 when the wafer is clamped in the electroplating cup assembly 300. The slip ring 302 may include a groove 304 that extends partially or completely around the slip ring 302, or may include two or more separate grooves that each accommodate one or more protrusions.

[0038] The electrical contact structure 212 includes a plurality of contacts extending from an outer ring toward the center of the electrical contact structure 212. Each contact includes a downwardly extending portion spaced apart from the lip seal 216, and an upwardly curved portion 306 configured to contact the wafer 202 located in the cup assembly. In this way, each contact acts as a leaf spring that pushes against the surface of the wafer in the cup with some spring force to ensure good contact between the contact and the wafer. This enables the contact to form good electrical contact with the wafer at an angle or on the surface of the wafer. Therefore, this feature accommodates normal variations in angle position.

[0039] Figure 4 A cross-sectional view of an electroplating cup assembly 400 according to an embodiment is shown. The electrical contact structure 212 includes a continuous outer ring that is located below and in contact with the slip ring 302 so that the current from the slip ring 302 can be evenly distributed. Further, the contact structure includes a plurality of protrusions extending upward from the outer ring of the contact structure into a groove 304 formed in the slip ring 302. The protrusions contact the inner edge of the groove 304. The protrusions are configured to center the electrical contact structure 212 at the correct position relative to the lip seal 216 and the cup bottom 214 to ensure that all of the various contacts on the electrical contact structure 212 (described below) contact the plated seed layer on the wafer located in the cup bottom 214. Further, this feature also helps prevent any contact from sliding past the lip seal 216 when the wafer is clamped in the electroplating cup assembly 300. The slip ring 302 may include a groove 304 that extends partially or completely around the slip ring 302, or may include two or more separate grooves that each accommodate one or more protrusions.

[0040] The electrical contact structure 212 includes a plurality of contacts extending from an outer ring toward the center of the electrical contact structure 212. Each contact includes a downwardly extending portion spaced apart from the lip seal 216, and an upwardly curved portion 306 configured to contact the wafer 202 located in the cup assembly. In this way, each contact acts as a leaf spring that pushes against the surface of the wafer in the cup with some spring force to ensure good contact between the contact and the wafer. This enables the contact to form good electrical contact with the wafer at an angle or on the surface of the wafer. Thus, this feature accommodates normal variations in angled position.

[0041] Figure 5 A wafer 500 is shown for use with the electroplating cup assembly 200 according to one embodiment. The wafer 500 includes a PR Edge Exclusion 502, a patterned photoresist 504, a non-patterned photoresist 506, and an exposed copper seed region 508.

[0042] In a first embodiment, the system now described is directed to thin seed electroplating of Cu for RDL applications: (1) Any thin seed Through photoresist Cu plating applications, not specifying RDL and (2) nominal seed thickness ( to ), which has a large pattern keep-out (defined here as the area at the edge of the wafer greater than 0.5 mm wide where photoresist has been applied but not patterned). The unpatterned photoresist will not be plated, so the patterned areas adjacent to the large non-patterned areas tend to plate with steep thickness spikes, forming edge-humps.

[0043] In the second embodiment, the present application processes the sacrificial plating and removes any metal (Ni, SnAg, Sn, Co). The EBR process is modified from the Piranha etch (used for Cu etch in the first embodiment) to a nitric acid etch or other chemical etch appropriate for the metal to be etched.

[0044] Figure 6 A wafer 600 is shown for use with the electroplating cup assembly 200 according to one embodiment. The wafer 600 includes a pattern edge keep-out area 602, a patterned photoresist area 604, a non-patterned photoresist area 606, and an exposed copper seed area 608. The wafer 600 does not include a PR edge keep-out area (e.g., Figure 5 ).

[0045] Figure 7 A wafer 700 is shown for use with the electroplating cup assembly 200 according to one embodiment. The wafer 700 includes a seal 702, a patterned photoresist region 704, a non-patterned photoresist region 706, and a sacrificial layer region 708.

[0046] In this exemplary embodiment, seal 702 is formed in contact with lip seal 216. Seal 702 forms a substantially concentric seal in which sacrificial layer region 708 is plated around the entire perimeter of the PR edge keep-out area (eg, PR edge keep-out 502).

[0047] Figure 8 A wafer 800 is shown for use with the electroplating cup assembly 200 according to one embodiment. The wafer 800 includes a seal 802, a patterned photoresist layer 804, a non-patterned photoresist region 806, and a sacrificial layer region 808.

[0048] In this exemplary embodiment, seal 802 is formed in contact with lip seal 216. Seal 802 forms a substantially concentric seal in which sacrificial layer region 808 is plated around the entire perimeter of the PR edge keep-out area (eg, PR edge keep-out 502).

[0049] In addition, the seal 802 is designed to increase the sacrificial plated area in the preferred azimuthal region. For example, the azimuthal region includes an area with a larger patterned edge keep-out zone: the "missing die" region.

[0050] Fig. 9 A wafer 900 is shown for use with the electroplating cup assembly 200 according to one embodiment. The wafer 900 includes a seal 902, a sacrificial layer region 908, a patterned photoresist region 904, and a non-patterned photoresist region 906.

[0051] In this exemplary embodiment, seal 902 is formed in contact with lip seal 216. Seal 902 forms a substantially concentric seal in which sacrificial layer region 908 is plated around the entire perimeter of the PR edge keep-out area (eg, PR edge keep-out 502).

[0052] In addition, the seal 902 is designed to increase the sacrificial plated area in the preferred azimuth region. For example, the seal 902 is placed outside of the area where only sacrificial copper is plated adjacent to the "missing die" area.

[0053] The above description includes illustrative examples, devices, systems and methods that embody the disclosed subject matter. In the description, for the purpose of explanation, many specific details are set forth to provide an understanding of multiple embodiments of the disclosed subject matter. However, it will be apparent to those skilled in the art that various embodiments of the subject matter can be practiced without these specific details. Further, well-known structures, materials and techniques are no longer shown in detail to avoid making the various illustrated embodiments difficult to understand.

[0054] As used herein, the term "or" may be interpreted in an inclusive or exclusive sense. Further, those skilled in the art will appreciate other embodiments after reading and understanding the disclosed content provided. In addition, those skilled in the art will readily appreciate that various combinations of the techniques and examples provided herein may all be applied in various combinations after reading and understanding the disclosed content provided herein.

[0055] Although various embodiments are discussed separately, these separate embodiments are not intended to be considered independent techniques or designs. As indicated above, each of the multiple parts can be interrelated, and each can be used alone or in combination with other particle sensor calibration system embodiments discussed herein.

[0056] Therefore, it will be apparent to those skilled in the art that many modifications and changes can be made after reading and understanding the disclosure provided herein. In addition to those listed herein, functionally equivalent methods and devices within the scope of the disclosure will be apparent to those skilled in the art based on the foregoing description. Portions and features of some embodiments may be included in or replaced by portions and features of other embodiments. These modifications and changes are intended to fall within the scope of the appended claims. Therefore, the present disclosure is limited only by the terms of the appended claims and the full scope of equivalents granted by these claims. It should also be understood that the terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting.

[0057] An abstract of the disclosure is provided so that the reader can quickly determine the nature of the technical disclosure. Submitting an abstract should be understood as not being used to interpret or limit the claims. In addition, in the foregoing detailed description, it can be seen that, for the purpose of simplifying the disclosure, a variety of features can be grouped together in a single embodiment. This method of disclosure is not to be interpreted as limiting the claims. Therefore, the following claims are thus incorporated into the detailed description, each of which is independently provided as a separate embodiment.

[0058] Example

[0059] Example 1 includes a plating cup assembly, comprising: a cup bottom having an opening, the opening being configured to allow a wafer located in the plating cup assembly to be exposed to a plating solution; a lip seal coupled to the cup bottom, the lip seal comprising a sealing structure extending upward along an inner edge of the lip seal to a vertex, the vertex being configured to contact a seed layer of the wafer and a sacrificial layer of the wafer; and an electrical contact structure forming a seal with the lip seal, the electrical contact structure being configured to couple with the seed layer at a periphery of the wafer.

[0060] Example 2 includes Example 1, wherein the apex is coupled to a wall of the sacrificial layer, the sacrificial layer being disposed along an annular region of the wafer.

[0061] Example 3 includes Example 1, wherein the seed layer and the sacrificial layer include a copper seed layer.

[0062] Example 4 includes Example 3, wherein the copper seed layer of the sacrificial layer has a thickness of less than 1000 angstroms.

[0063] Example 5 includes Example 3, wherein the copper seed layer of the sacrificial layer has a thickness between 1000 angstroms and 3000 angstroms, wherein a pattern keep-out area is at least 0.5 mm.

[0064] Example 6 includes Example 1, wherein the cup bottom comprises a contour, and wherein the seal comprises a mounting structure having a bottom surface configured to mate with the contour.

[0065] Example 7 includes Example 1, wherein the cup bottom includes an inner cup edge, and wherein the inner cup edge of the cup bottom is axially aligned with the inner cup edge of the lip seal.

[0066] Example 8 is an electroplating method, which includes: placing a wafer on a plating cup assembly that exposes a surface of the wafer to a plating solution, the surface including a sacrificial layer at the periphery of the wafer; electroplating the exposed surface of the wafer; and after electroplating the exposed surface of the wafer, removing the plated sacrificial layer of the wafer.

[0067] Example 9 includes Example 8, further comprising: wherein the sacrificial layer includes an annular ring of a seed layer.

[0068] Example 10 includes Example 8, wherein removing the plated sacrificial layer includes applying an edge bevel removal tool to the plated sacrificial layer.

[0069] Example 11 includes Example 8, wherein removing the plated sacrificial layer comprises etching the plated sacrificial layer from the wafer.

[0070] Example 12 includes Example 8, wherein the electroplating cup assembly includes: a cup bottom, which at least partially has an opening, and the opening is configured to enable the surface of the chip located in the electroplating cup assembly to be exposed to the electroplating solution; a lip seal, which is coupled to the cup bottom, and the lip seal includes a sealing structure, which extends upward along the inner edge of the lip seal to an apex, and the apex is configured to contact the seed layer of the chip and the sacrificial layer of the chip; and an electrical contact structure, which forms a seal with the lip seal, and the electrical contact structure is configured to couple with the seed layer at the periphery of the chip.

[0071] Example 13 includes Example 12, wherein the seed layer includes one of Cu, Ni, SnAg, Sn, or Co metal.

[0072] Example 14 is a system comprising: a wafer having a seed layer and a sacrificial layer, the sacrificial layer being disposed on the seed layer along a periphery of the wafer; and a plating cup assembly configured to support the wafer, the plating cup assembly comprising: a cup bottom at least partially defining an opening, the opening being configured to allow the wafer in the plating cup assembly to be exposed to a plating solution; a lip seal coupled to the cup bottom, the lip seal comprising a sealing structure extending upward along an inner edge of the lip seal to an apex, the apex being configured to contact the seed layer of the wafer and the sacrificial layer of the wafer; and an electrical contact structure forming a seal with the lip seal, the electrical contact structure being configured to couple with the seed layer at the periphery of the wafer.

[0073] Example 15 includes Example 14, wherein the apex is coupled to a wall of the sacrificial layer, the sacrificial layer being disposed along an annular region of the wafer.

[0074] Example 16 includes Example 14, wherein the seed layer and the sacrificial layer include a copper seed layer.

[0075] Example 17 includes Example 16, wherein the copper seed layer of the sacrificial layer has a thickness of less than 1000 angstroms.

[0076] Example 18 includes Example 16, wherein the copper seed layer of the sacrificial layer has a thickness between 1000 angstroms and 3000 angstroms, wherein a pattern keep-out area is at least 0.5 mm.

[0077] Example 19 includes Example 14, wherein the cup bottom comprises a contour, and wherein the seal comprises a mounting structure having a bottom surface configured to mate with the contour.

[0078] Example 20 includes Example 14, wherein the cup bottom includes an inner edge, and wherein the inner cup edge of the cup bottom is substantially axially aligned with the inner edge of the lip seal.

Claims

1. An electroplating cup assembly, comprising: a cup bottom having an opening configured to allow a wafer positioned in the electroplating cup assembly to be exposed to an electroplating solution; a lip seal coupled to the cup bottom, the lip seal comprising a sealing structure extending upwardly along an inner edge of the lip seal to an apex, the apex being configured to contact a seed layer of the wafer and a sacrificial layer of the wafer; as well as An electrical contact structure forms a seal with the lipseal, the electrical contact structure being configured to couple with the seed layer at a periphery of the wafer.

2. The electroplating cup assembly of claim 1, wherein the apex is coupled to a wall of the sacrificial layer, the sacrificial layer being disposed along an annular region of the wafer.

3. The electroplating cup assembly of claim 1, wherein the seed layer and the sacrificial layer comprise a copper seed layer.

4. The electroplating cup assembly of claim 3, wherein the copper seed layer of the sacrificial layer has a thickness of less than 1000 angstroms.

5. The electroplating cup assembly of claim 3, wherein the copper seed layer of the sacrificial layer has a thickness between 1000 angstroms and 3000 angstroms, wherein a pattern keep-out zone is at least 0.5 mm.

6. The electroplating cup assembly of claim 1, wherein the cup bottom comprises a contour, and wherein the seal comprises a mounting structure having a bottom surface configured to mate with the contour.

7. The electroplating cup assembly of claim 1, wherein the cup bottom includes an inner cup edge, and wherein the inner cup edge of the cup bottom is axially aligned with the inner edge of the seal.

8. A method for electroplating a wafer, comprising: placing the wafer on a plating cup assembly that exposes a surface of the wafer to a plating solution, the surface including a sacrificial layer at a periphery of the wafer, wherein the plating cup assembly comprises: a cup bottom at least partially having an opening configured to allow the surface of the wafer positioned in the electroplating cup assembly to be exposed to the electroplating solution; a lip seal coupled to the cup bottom, the lip seal comprising a sealing structure extending upwardly along an inner edge of the lip seal to an apex, the apex being configured to contact the seed layer of the wafer and the sacrificial layer of the wafer; and an electrical contact structure that forms a seal with the lipseal, the electrical contact structure being configured to couple with the seed layer at the periphery of the wafer; electroplating the exposed surface of the wafer; and After electroplating the exposed surface of the wafer, the plated sacrificial layer of the wafer is removed.

9. The method according to claim 8, further comprising: Wherein the sacrificial layer comprises an annular ring of seed layer.

10. The method of claim 8, wherein removing the plated sacrificial layer comprises: An edge bevel removal tool is applied to the plated sacrificial layer.

11. The method of claim 8, wherein removing the plated sacrificial layer comprises: The plated sacrificial layer is etched from the wafer.

12. The method of claim 8, wherein the seed layer comprises one of Cu, Ni, SnAg, Sn, or Co metal.

13. A system for electroplating a wafer, comprising: The wafer has a seed layer and a sacrificial layer, wherein the sacrificial layer is disposed on the seed layer along the periphery of the wafer; as well as an electroplating cup assembly configured to support the wafer, the electroplating cup assembly comprising: a cup bottom at least partially defining an opening configured to enable exposure of the wafer positioned in the electroplating cup assembly to an electroplating solution; a lip seal coupled to the cup bottom, the lip seal comprising a sealing structure extending upwardly along an inner edge of the lip seal to an apex, the apex being configured to contact the seed layer of the wafer and the sacrificial layer of the wafer; and An electrical contact structure forms a seal with the lipseal, the electrical contact structure being configured to couple with the seed layer at the periphery of the wafer.

14. The system of claim 13, wherein the apex is coupled to a wall of the sacrificial layer, the sacrificial layer being disposed along an annular region of the wafer.

15. The system of claim 13, wherein the seed layer and the sacrificial layer comprise a copper seed layer.

16. The system of claim 15, wherein the copper seed layer of the sacrificial layer has a thickness of less than 1000 angstroms.

17. The system of claim 15, wherein the copper seed layer of the sacrificial layer has a thickness between 1000 angstroms and 3000 angstroms, wherein a pattern keep-out zone is at least 0.5 mm.

18. The system of claim 13, wherein the cup bottom comprises a contour, and wherein the seal comprises a mounting structure having a bottom surface configured to mate with the contour.

19. The system of claim 13, wherein the cup bottom includes an inner cup edge, and wherein the inner cup edge of the cup bottom is axially aligned with the inner edge of the lip seal.

Citation Information

Patent Citations

  • Semiconductor wafer plating cathode assembly

    US20030085119A1

  • Electroplating cup assembly

    US20110233056A1